Text preview for : Toshiba Satellite C660 - COMPAL LA-6842P PWWAA - REV 0.2.pdf part of TOSHIBA Toshiba Satellite C660 - COMPAL LA-6842P PWWAA - REV 0.2 TOSHIBA Laptop toshiba c665 Toshiba Satellite C660 - COMPAL LA-6842P PWWAA - REV 0.2.pdf
Back to : Toshiba Satellite C660 - | Home
A B C D E
1 1
PWWAA
2
LC Marseille 2
LA-6842P REV 0.2 Schematic
3
Intel Processor(ARD) /PCH(HM55) 3
2010-07-22 Rev 0.2
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/06/21 Deciphered Date 2011/06/21 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWAA LA6842P M/B
Date: W ednesday, July 28, 2010 Sheet 1 of 45
A B C D E
A B C D E
Compal Confidential Fan Control Clock Generator
Intel Arrandale APL5607 RTM890N-631-GRT
Model Name : PWWAA page 6 page 13
File Name : LA-6842P
1 1
rPGA-988 Memory BUS(DDRIII) 200pin DDRIII-SO-DIMM X2
Dual Channel BANK 0, 1, 2, 3 page 11,12
page 5,6,7,8,9,10 1.5V DDRIII 800/1066 MT/s
USB
FDI X8 DMI X4 USB port 0,1
page 25
2.7GHz 2.5GHz
2IN1 RTS5137 Int. Camera
LCD Conn. USB port 10 USB port 11
page 13 USB page 26 page 13
5V 480MHz
CRT
2
page 14 2
PCIeMini Card
WiMax
USB
USB port 13
5V 480MHz page 27
PCIe 1x PCIeMini Card
1.5V 2.5GHz(250MB/s) WLAN
PCIe port 1
page 27
Intel Ibex Peak
SATA port 1 SATA HDD0
5V 3GHz(300MB/s) page 25
RJ45 RTL8105E-GR 10/100M PCIe 1x SATA port 4 SATA ODD
page 28 PCIe port 0 page 28 1.5V 2.5GHz(250MB/s) BGA-951 5V 3GHz(300MB/s) page 25
PCI
3 3
page 16~24
3.3V 33 MHz
LPC BUS
HD Audio 3.3V/1.5V 24MHz
Power/B conn. RTC CKT. HDA Codec
page 32
page 16 SPI ROM Debug Port ENE KB926 E0 ALC259-GR
page 29
page 16 page 32 page 31
DC/DC Interface CKT.
page 34
Int. Ext.
Touch Pad EC ROM MIC CONN MIC CONN HP CONN SPK CONN
Int.KBD (LVDS CONN) page 30 page 30 page 30
page 33 page 32 page 32 page 13
Power Circuit DC/DC
4 4
page 35~44
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/06/21 Deciphered Date 2011/06/21 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWAA LA6842P M/B
Date: W ednesday, July 28, 2010 Sheet 2 of 45
A B C D E
5 4 3 2 1
DESIGN CURRENT 0.1A +3VL
DESIGN CURRENT 0.1A +5VL
B+
Ipeak=5A, Imax=3.5A, Iocp min=7.9 DESIGN CURRENT 5A +5VALW
SUSP#
DESIGN CURRENT 2A +1.8VS
MP2121DQ
D SUSP D
N-CHANNEL DESIGN CURRENT 4A +5VS
SI4800
BCPWON
DESIGN CURRENT 0.5A +5VS_L_BCAS
P-CHANNEL
AO-3413
KB_LED
RT8205EGQW DESIGN CURRENT 400mA +5VS_LED
P-CHANNEL
AO-3413
+5VS
DESIGN CURRENT 300mA +3VS_HDP
LDO
G9191
ODD_EN#
DESIGN CURRENT 1.6A +5VS_ODD
P-CHANNEL
AO-3413
Ipeak=5A, Imax=3.5A, Iocp min=7.7 DESIGN CURRENT 5A +3VALW
WOL_EN#
P-CHANNEL DESIGN CURRENT 330mA +3V_LAN
SUSP AO-3413
C C
N-CHANNEL DESIGN CURRENT 4A +3VS
SI4800
LCD_ENVDD
P-CHANNEL DESIGN CURRENT 1.5A +LCD_VDD
AO-3415
BT_PWR#
DESIGN CURRENT 180mA +BT_VCC
P-CHANNEL
AO-3413
FELICA_PWR
DESIGN CURRENT 0.5A +FLICA_VCC
P-CHANNEL
AO-3413
VR_ON
DESIGN CURRENT 48A +CPU_CORE
ISL62883HRZ
GFXVR_EN
DESIGN CURRENT 15A +GFX_CORE
ADP3211AMNR2G
VTTP_EN
B B
Ipeak=18A, Imax=12.6A, Iocp min=19.8 DESIGN CURRENT 18A +VTT
APW7138NITRL
SUSP#
Ipeak=7A, Imax=4.9A, Iocp min=7.7 DESIGN CURRENT 7A +1.05VS
RT8209BGQW
SUSP#
Ipeak=15A, Imax=10.5A, Iocp min=16.5 DESIGN CURRENT 15A +1.5V
RT8209BGQW SUSP
N-CHANNEL DESIGN CURRENT 2A +1.5V_CPU
FDS6676AS
SUSP
N-CHANNEL DESIGN CURRENT 2A +1.5VS
FDS6676AS
SUSP or 0.75VR_EN#
DESIGN CURRENT 1.5A +0.75VS
A G2992F1U A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/06/21 Deciphered Date 2011/06/21 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Tree
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWAA LA6842P M/B
Date: Wednesday, July 28, 2010 Sheet 3 of 45
5 4 3 2 1
A B C D E
( O MEANS ON X MEANS OFF )
Voltage Rails
+RTCVCC +B +5VL +5VALW +1.5V +5VS
+3VL +3VALW +3VS
+VSB +1.5VS
power
+VGA_CORE
1 plane BTO Option Table 1
+CPU_CORE
+VTT
Function MINI PCI-E SLOT LAN
+1.05VS
+1.8VS description SLOT1 LAN
+1.1VS
explain WLAN/BT 10/100M
State +0.75VS
BTO
Function Camera & Mic
description Camera & Mic
S0
O O O O O O explain Camera & Mic
S1 BTO CAM@
O O O O O O
2 2
S3
O O O O O X Function S3 Power Saving
S5 S4/AC description S3 Power Saving
O O O O X X
explain Power Saving
S5 S4/ Battery only
O O O X X X
BTO
S5 S4/AC & Battery
don't exist
O X X X X X
PCH SM Bus Address
Power Device HEX Address
+3VS DDR SO-DIMM 0 A0 H 1010 0000 b
+3VS DDR SO-DIMM 1 A4 H 1010 0100 b
3 SIGNAL 3
+3VS Clock Generator D2 H 1101 0010 b STATE SLP_S3# SLP_S4# SLP_S5#
+3VS New Card
Full ON HIGH HIGH HIGH
+3VS WLAN/WIMAX
+3VS Clock Generator S1(Power On Suspend) HIGH HIGH HIGH
S3 (Suspend to RAM) LOW HIGH HIGH
S4 (Suspend to Disk) LOW LOW HIGH
S5 (Soft OFF) LOW LOW LOW
EC SM Bus1 Address EC SM Bus2 Address
G3 LOW LOW LOW
Power Device HEX Address Power Device HEX Address
+3VL Smart Battery 16 H 0001 0110 b +3VS PCH 96 H 1001 0110 b
4
Power Device HEX Address 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/06/21 Deciphered Date 2011/06/21 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWAA LA6842P M/B
Date: W ednesday, July 28, 2010 Sheet 4 of 45
A B C D E
5 4 3 2 1
JCPUB
1 2 H_COMP3 AT23
R1 20_0402_1% COMP3
BCLK A16 CLK_CPU_BCLK 21
MISC
MISC
1 2 H_COMP2 AT24 B16
COMP2 BCLK# CLK_CPU_BCLK# 21
R2 20_0402_1%
H_COMP1 G16 CLK_CPU_XDP_R 1 CLK_CPU_XDP
CLOCKS
1 2 COMP1 BCLK_ITP AR30 2
R4 49.9_0402_1% AT30 CLK_CPU_XDP#_R 1 R41 @ 2 0_0402_5% CLK_CPU_XDP#
H_COMP0 AT26 BCLK_ITP# R42 @ 0_0402_5%
1 2 COMP0
R3 49.9_0402_1% E16 CLK_PEG 17
PEG_CLK +VTT
PEG_CLK# D16 CLK_PEG# 17
TP_SKTOCC# AH24
+VTT PAD T41 SKTOCC#
DPLL_REF_SSCLK A18 Unused by Clarksfield rPGA989
D A17 PM_EXTTS#0 R15 2 1 10K_0402_5% D
CATERR# DPLL_REF_SSCLK#
1 2 AK14 CATERR#
THERMAL
THERMAL
R18 49.9_0402_1% PM_EXTTS#_R R13 2 1 10K_0402_5%
F6 SM_DRAMRST#_CPU
SM_DRAMRST#
21 PECI AT15 PECI
SM_RCOMP[0] AL1 SM_RCOMP_0 R6 1 2 100_0402_1%
Power has removed VR_TT# AM1 SM_RCOMP_1 R7 1 2 24.9_0402_1% DDR3 Compensation Signals
SM_RCOMP[1] Layout Note:Please these
SM_RCOMP[2] AN1 SM_RCOMP_2 R8 1 2 130_0402_1% resistors near Processor
+VTT 1 2 H_PROCHOT#_D AN26 R19 unmount for NPS@
+VTT PROCHOT#
R9 68_0402_5% AN15 PM_EXTTS#0
DDR3
MISC
PM_EXT_TS#[0]
PM_EXT_TS#[1] AP15 PM_EXTTS#_R 2 1 PM_EXTTS# 11,12 @
R12 0_0402_5% 2 1
AK15 R19 0_0402_5%
21 H_THERMTRIP# THERMTRIP#
2
R10
68_0402_5% AT28 XDP_PRDY#
PRDY#
S
D
AP27 XDP_PREQ# SM_DRAMRST#_CPU 3 1
@ PREQ# SM_DRAMRST# 11,12
1
1
AN28 XDP_TCK Q41
H_CPURST# XDP_RST#_R H_CPURST# TCK XDP_TMS BSS138_NL_SOT23-3
1 2 AP26 AP28
G
2
RESET_OBS# TMS
PWR MANAGEMENT
PWR MANAGEMENT
R36 1K_0402_5% AT27 XDP_TRST# Routed as a single daisy chain R127
TRST# 100K_0402_5%
JTAG & BPM
RST_GATE 21
AL15 AT29 XDP_TDI_R
18 PMSYNCH
2
PM_SYNC TDI XDP_TDO_R
TDO AR27 C301, Q41,
2
AR29 XDP_TDI_M 2 1 C301
+1.5V_CPU TDI_M +3VS R127 from PS@
2 1 H_PWRGOOD1_R AN14 VCCPW RGOOD_1 TDO_M AP29 XDP_TDO_M R312 1K_0402_5% 0.047U_0402_16V7K
0_0402_5% R25 to mount
1
AN25 XDP_DBRESET#
DBR# XDP_DBRESET# 18
C H_PWRGOOD AN27 C
21 H_PWRGOOD VCCPW RGOOD_0
2
R28 @ AJ22 XDP_BPM#0 Add on 10/28
1.1K_0402_1% DRAMPWROK AK13 BPM#[0] XDP_BPM#1
18 DRAMPWROK SM_DRAMPW ROK BPM#[1] AK22
AK24 XDP_BPM#2
BPM#[2] XDP_BPM#3
AJ24
1
VTTPWROK_CPU AM15 BPM#[3]
39 VTTPWROK_CPU VTTPW RGOOD BPM#[4] AJ25
DRAMPWROK AH22
BPM#[5]
BPM#[6] AK23
TAPPWRGD AM26 AH23 XDP_TDI_R 1 2 XDP_TDI
TAPPW RGOOD BPM#[7]
1
JTAG MAPPING R20 0_0402_5%
750_0402_1% BUF_PLT_RST#_R XDP_TDO_M XDP_TDO
20 BUF_PLT_RST# AL14 RSTIN# 1 @ 2
R29 1.5K_0402_1% R30 Scan Chain STUFF -> R20, R23, R27 R21 0_0402_5%
1
(Default) NO STUFF -> R21, R26
2
R31 R23
750_0402_1% IC,AUB_CFD_rPGA,R0P9 0_0402_5%
@ CPU Only STUFF -> R20, R21
NO STUFF -> R23, R26, R27