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A B C D E

EGRET Block Diagram
200-PIN DDR SODIMM
CLK GEN AMD CPU
ICS DDR 3 33/400 DDR x2
Claw Hammer K8 PCB Layer Stackup
4
ICS950405 8,9,10
3 L1: Signal 1 4

4,5,6,7 L2: GND
TV Encoder L3: Signal 2
SVIDEO/COMP
HyperTransport VIA VT1623M TVOUT 1 7 L4: Signal 3
6.4GB/S 16b/8b 14 L5: VCC
L6: Signal 4
PWR SW TI LVDS Transmitter LVDS
PCMCIA
SLOT
TPS2224AP PCI 7420 VIA VIA VT1631 LCD 18
27 2* Slot Cardbus 15
Support 1* 13 94
K8N800 Battery Charger 46
TypeII PCMCIA I/F AGTL+ CPU I/F + UMA MAX1645BEEI
27 AG P 8x Graphic CONN.
11,1 2,13 RGB CRT INPUTS OUTPUTS
AGP 8X CRT 17
1394 16 AD+ DCBATOUT
25, 26 BAT+
3
Conn 8 bit V-LINK 3
27 SYSTEM DC/DC 43
66MHZ 8x/4x/2x
MAX1999
INPUT OUTPUT

VIA DCBATOUT 5V_S5 ,
3D3V_S5
Mini-PCI PCI Bus / 33MHz VT8235CE SYSTEM DC/DC 44
ACPI 2.0 6xUSB 2.0
USB x 4
802.11a/b/g PCI 24
AC'97 CODEC TPS5110
30 VT1612A Line In 3 2 INPUT OUTPUT

AC LINK MIC In DCBATOUT 2D5V_S3
31 2D5V_S3 1D5V_S0
6- CH
1 0 0 0 Mb
PCI GIGA LAN AC97 2.2
RJ45 TXFM Line Out
Realtek MODEM RJ11 CPU V_CORE41, 42
29 29 28 OP AMP (SPDIF)
RTL8110SBL MDC Card CONN 32 ISL6559CR
29 APA2020
24 32 INPUT OUTPUT

TXFM 1 0/100Mb LAN PHY MII Int. SPKR DCBATOUT VCC_CORE_S0
2 29 VIA VT6103L 2 9 32 2
LPC Bus / 33MHz
LPC I/F SYSTEM POWER 44, 45
FDD6035AL/FDS9412-U
ATA 133 19,2 0,21 FDS9412-U/SI4892DY/LP2951ACM
APL5508-18VC/APL5308-25AC
INPUT OUTPUT

Thermal 2D5V_S5
NS SIO KBC FWH 5V_S0
P IDE

SIDE

& Fan 5V_S3 3D3V_S3
PC87392 G791 2 2 M38859 SST-49LF040 3D3V_S5 3D3V_S0
3D3V_S3 3D3V_LAN_S3
36 33 35 3D3V_S0
DVD/ DCBATOUT
1D8V_S0
HDD +5V_AUX_S5
CD-RW +5V_UP_S5
23 23
2D5V_S0

Parallel FIR Touch Int.
port TFD U6101E Pad KB
37 36 34 34

1 1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Block Diagram
Size Document Number Rev
A3
EGRET SC
Date: Friday, July 23, 2004 Sheet 1 of 50
A B C D E
EGRET REVISION HISTORY PCI RESOURCE TABLE
DEVICE IDSEL PCI IRQ REQ# / GNT#

VGA & AGP P_INTA#

AD22 P_INTB# P_REQ#1/P_GNT#1
PCI7420-CardBus A

PCI7420-CardBus B AD22 P_INTC# P_REQ#1/P_GNT#1

PCI7420-IEEE1394A AD22 P_INTD# P_REQ#1/P_GNT#1

Mini-PCI AD21 P_INTF# P_REQ#0/P_GNT#0

Giga LAN AD23 P_INTG# P_REQ#2/P_GNT#2
RTL8110SBL

5,8 VREF_DDR_MEM VREF_DDR_MEM

4,11,13,39,45 1D2V_HT0A_S0 1D2V_HT0A_S0

4,6 1D2V_HT0B_S0 1D2V_HT0B_S0

5,6,7,9,10,39,45 1D25V_S3 1D25V_S3

12,13,14,15,16,44,50 1D5V_S0 1D5V_S0

6,12,14,15,16,19,20,21,38,39,50 2D5V_S0 2D5V_S0

5,6,7,8,10,38,39,44,45,50 2D5V_S3 2D5V_S3

19,20,21,39 2D5V_S5 2D5V_S5

3,6,8,11,12,13,14,15,16,17,18,19,20,21,24,25,26,27,28,30,31,32,33,34,35,36,38,41,47,49,50 3D3V_S0 3D3V_S0

18,33,34,38,50 3D3V_S3 3D3V_S3

13,18,19,20,21,22,24,28,29,33,38,43,49,50 3D3V_S5 3D3V_S5

16,17,18,19,20,21,22,23,24,27,30,31,32,33,34,37,38,39,41,42,47,48,49,50 5V_S0 5V_S0

21,38,39,43,44,45,46,48,49 5V_S5 5V_S5

19,21,22,34,38,39,45,46,49 +5V_AUX_S5 +5V_AUX_S5

18,48,50 +5V_UP_S5 +5V_UP_S5

16,18,38,41,43,44,45,46,47,50 DCBATOUT DCBATOUT

7,41,42 VCC_CORE_S0 VCC_CORE_S0

46,47 AD+ AD+

46,47 BT+ BT+

41,42 DCBATOUT_ISL DCBATOUT_ISL

24,28,29 3D3V_LAN_S5 3D3V_LAN_S5

25,27 VCC_ASKT_S0 VCC_ASKT_S0

27 VPP_ASKT_S0 VPP_ASKT_S0

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
REVISION HISTORY
Size Document Number Rev
A3 SC
EGRET
Date: Friday, July 23, 2004 Sheet 2 of 50
A B C D E

6,8,11,12,13,14,15,16,17,18,19,20,21,24,25,26,27,28,30,31,32,33,34,35,36,38,41,47,49,50 3D3V_S0 3D3V_S0
3D3V_S0 3D3V_CLK_S0
L9 BLM21A121S
1 2 3D3V_CLK_S0

1

1

1

1

1

1
SC10U10V6ZY-U
C156 C593 C592 C594 C645 C646

SCD1U SCD1U SCD1U SCD1U SCD1U FS0~FS2 Have internal Pull-up resistor

2

2

2

2

2

2
FS3 Have internal Pull-down resistor
4 4

1

1

1

1

1
C599 C595 C596 C597 C598
U15
SCD1U SCD1U SCD1U SCD1U SCD1U SB

2

2

2

2

2
2 13 PCICLK0 R105 1 2 22R3
VDD PCI33_0 CLK33_CARDBUS 25
9 14 PCICLK1 R107 1 2 DY-22R3
VDD PCI33_1 CLK33_LAN 28
16 17 PCICLK2 R126 1 2 ZZ.22034.151 CLK33_MINI 30
VDD PCI33_2 22R3
19 VDD PCI33_3 18
PCICLK4 RN13
CLK33_LAN Damping only
29 VDD PCI33_4 21 4 5 CLK33_KBC 33
35 22 PCICLK5 3 6 Stuff for RTL8110SB
SC 38
VDD PCI33_5
23 PCICLK6 SRN22-1 2 7
CLK33_SIO 36
VDD PCI33_6 CLK33_LPCROM 35
46 24 PCICLK7 1 8
VDD PCI33_7 CLK33_SB 21
C154
XI_CLK CLK33_HT66SEL#0
By KDS suggested change 1 2 43 VDDA HT66_0/PCIHT66SEL0# 6
CLK33_HT66SEL#1 R101 1 2 22R3
Library Issue PCI33_8_HT66_1/PCIHT66SEL1# 7 CLK66_NB 12

1
From 78.33034.1B1 SC12P CLK_PD# 32 8 PCI33_HT66_2 R106 1 2 DY-22R3
VDDF PCI33_9_HT66_2 CLK66_VGA 16
X3 Pin32: PD# 11 PCI33_HT66_3 R102 1 2 22R3
PCI33_11_HT66_3 CLK66_VCLK 21
To 78.12034.1B1 XTAL-14D318M-2 PCI33_10 12
C155 3

2
XO_CLK XIN
1 2 4 XOUT CLK66_VGA Damping only
SRESET#/PD# 44
SC12P R108 15R3F Stuff for K8N800 Discrete
1 2 CPUCLK_CY 41 28 CLK_24_48SEL# R127 1 2 22R3
6 CPUCLK CPUT0 24_48MHZ/SEL# CLK48_CARDBUS 25
37 CPUT1

1
R112 15R3F 33 R128
CPUCLK#_CY 40 VSSF 10KR3
6 CPUCLK# 1 2 CPUC0
3 3
GUICLK Damping only 36 CPUC1 VSSA 42

2
Stuff for K8N800 UMA 12 GUICLK
R86 1 2 22R3 5
FS0 VSS
1 FS0/REF0 VSS 10
R88 1 2 22R3 FS1 48 15
21 APICCLKSB FS1/REF1 VSS
R109 1 2 22R3 FS2 45 20
20 SIO_OSC FS2/REF2 VSS
R110 1 2 22R3 FS3 31 27
36 CLK14_SIO USB/FS3 VSS
VSS 30
8,21 SMBC_SB 25 SCLK VSS 34
VSS 39
8,21 SMBD_SB 26 SDATA VSS 47

ICS950405

3D3V_CLK_S0
R85 10KR3
1 2 FS0
R111 1 2 22R3 FS3
19 CLK48_USB
R87 10KR3
1 2 FS1

R114 10KR3
1 2 FS2

Input Configuration Clock Generator Output
24_48 SEL# 24_48MHz
2 FS3 FS2 FS1 FS0 CPU (MHz) PCI33_HT66 (MHz) PCI33 (MHz) 3D3V_CLK_S0 2
* 0 48MHz
0 0 0 0 100.90 67.27 33.63 All output Tri-state R113 10KR3
1 24MHz CLK_PD#
0 0 0 1 133.90 66.95 33.48 1 2

0 0 1 0 168.00 67.20 33.60 CLK33_HT66SEL#1 1 2
R103 10KR3
0 0 1 1 202.00 67.33 33.67 CLK33_HT66SEL#0 1 2
R104 10KR3
0 1 0 0 100.20 66.80 33.40
0 1 0 1 133.50 66.75 33.38
0 1 1 0 166.70 66.68 33.34 PCIHT66 SEL[1:0]# PCI33_HT66[3:0]
* 0 1 1 1 200.40 66.80 33.40 Normal Hammer operation
SEL0 SEL1 PIN7 PIN8 PIN11
1 0 0 0 150.00 60.00 30.00
0 0 HT66 HT66 PCI33
1 0 0 1 180.00 60.00 30.00
* 0 1 HT66 HT66 HT66
1 0 1 0 210.00 70.00 35.00
1 0 PCI33 PCI33 PCI33
1 0 1 1 240.00 60.00 30.00
1 1 HT66 PCI33 PCI33
1 1 0 0 270.00 67.50 33.75
1 1 0 1 233.33 66.67 33.33
1 1
1 1 1 0 266.67 66.67 33.33
1 1 1 1 300.00 75.00 37.50 Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
CLKGEN_ICS950405
Size Document Number Rev
A3 SC
EGRET
Date: Friday, July 23, 2004 Sheet 3 of 50
A B C D E
A B C D E

11,13,39,45 1D2V_HT0A_S0 1D2V_HT0A_S0
1D2V_HT0A_S0

6 1D2V_HT0B_S0 1D2V_HT0B_S0

1

1

1

1
C105 C107 C106 C109
SCD22U16V3ZY SCD22U16V3ZY SCD22U16V3ZY SCD22U16V3ZY

2

2

2

2
4 4

HTT for CPU sideA HTT for CPU sideB
Transmit power Receive power
and NB sideA Receive and NB sideA
power Transmit power

1D2V_HT0A_S0 U11A 1D2V_HT0B_S0

D29 VLDT0_A VLDT0_B AH29 LAYOUT: Place bypass cap on topside of board near
D27 AH27
D25
VLDT0_A VLDT0_B
AG28 HTT power pins that are not connected directly to
3 VLDT0_A VLDT0_B C469 3
C28 VLDT0_A VLDT0_B AG26 downstream HTT device, but connected internally to
C26 AF29 SC4D7U10V5ZY
B29
VLDT0_A VLDT0_B
AE28
other HTT power pins.
VLDT0_A VLDT0_B
B27 VLDT0_A VLDT0_B AF25
NB0CADOUT15 T25 N26 CPUCADOUT15
11 NB0CADOUT[15..0] L0_CADIN_H15 L0_CADOUT_H15 CPUCADOUT[15..0] 11
NB0CADOUTJ15 R25 N27 CPUCADOUTJ15
11 NB0CADOUTJ[15..0] L0_CADIN_L15 L0_CADOUT_L15 CPUCADOUTJ[15..0] 11
NB0CADOUT14 U27 L25 CPUCADOUT14
NB0CADOUTJ14 L0_CADIN_H14 L0_CADOUT_H14 CPUCADOUTJ14
U26 L0_CADIN_L14 L0_CADOUT_L14 M25
Used SideB Power Plane NB0CADOUT13 V25 L26 CPUCADOUT13 Used SideA Power Plane
NB0CADOUTJ13 L0_CADIN_H13 L0_CADOUT_H13 CPUCADOUTJ13
U25 L0_CADIN_L13 L0_CADOUT_L13 L27
NB0CADOUT12 W27 J25 CPUCADOUT12
NB0CADOUTJ12 L0_CADIN_H12 L0_CADOUT_H12 CPUCADOUTJ12
W26 L0_CADIN_L12 L0_CADOUT_L12 K25
NB0CADOUT11 AA27 G25 CPUCADOUT11
NB0CADOUTJ11 L0_CADIN_H11 L0_CADOUT_H11 CPUCADOUTJ11
AA26 L0_CADIN_L11 L0_CADOUT_L11 H25
NB0CADOUT10 AB25 G26 CPUCADOUT10
NB0CADOUTJ10 L0_CADIN_H10 L0_CADOUT_H10 CPUCADOUTJ10
AA25 L0_CADIN_L10 L0_CADOUT_L10 G27
NB0CADOUT9 AC27 E25 CPUCADOUT9
NB0CADOUTJ9 L0_CADIN_H9 L0_CADOUT_H9 CPUCADOUTJ9
AC26 L0_CADIN_L9 L0_CADOUT_L9 F25
NB0CADOUT8 AD25 E26 CPUCADOUT8
NB0CADOUTJ8 L0_CADIN_H8 L0_CADOUT_H8 CPUCADOUTJ8
AC25 L0_CADIN_L8 L0_CADOUT_L8 E27
NB0CADOUT7 T27 N29 CPUCADOUT7
NB0CADOUTJ7 L0_CADIN_H7 L0_CADOUT_H7 CPUCADOUTJ7
T28 L0_CADIN_L7 L0_CADOUT_L7 P29
NB0CADOUT6 V29 M28 CPUCADOUT6
NB0CADOUTJ6 L0_CADIN_H6 L0_CADOUT_H6 CPUCADOUTJ6
U29 L0_CADIN_L6 L0_CADOUT_L6 M27
NB0CADOUT5 V27 L29 CPUCADOUT5
NB0CADOUTJ5 L0_CADIN_H5 L0_CADOUT_H5 CPUCADOUTJ5
V28 L0_CADIN_L5 L0_CADOUT_L5 M29
NB0CADOUT4 Y29 K28 CPUCADOUT4
NB0CADOUTJ4 L0_CADIN_H4 L0_CADOUT_H4 CPUCADOUTJ4
W29 L0_CADIN_L4 L0_CADOUT_L4 K27
2 NB0CADOUT3 CPUCADOUT3 2
AB29 L0_CADIN_H3 L0_CADOUT_H3 H28
NB0CADOUTJ3 AA29 H27 CPUCADOUTJ3
NB0CADOUT2 L0_CADIN_L3 L0_CADOUT_L3 CPUCADOUT2
AB27 L0_CADIN_H2 L0_CADOUT_H2 G29
NB0CADOUTJ2 AB28 H29 CPUCADOUTJ2
NB0CADOUT1 L0_CADIN_L2 L0_CADOUT_L2 CPUCADOUT1