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5 4 3 2 1
SYSTEM DC/DC
RT8223 47
TUCANA Block Diagram PROJECT CODE : 91.4KK01.001
PCB P/N
REVISION
: 48.4KK01.0SB
: S0201-SB
INPUTS OUTPUTS
5V_S5(6A)
3D3V_S5(5A)
DCBATOUT
Clock Generator 5V_AUX_S5
D
ICS9LVS3197BKLFT 3D3V_AUX_S5
D
3 Slot 0 DDRIII Channel A
DDRIII Intel CPU
800 21 RT8209 49
Thermal Sensor Slot 1 SFF INPUTS OUTPUTS
GMT G787 DDRIII DDRIII Channel B
37 800 22 DCBATOUT 1D05V_S0(20A)
4,5,..,10,11
RT8209 48
FDIx8 DMIx4
INPUTS OUTPUTS
LVDS LCD DCBATOUT 1D5V_S3(9.4A)
Int MIC 23
INTEL
RGB CRT RT9026 51
Codec 24
C
Line Out
Realtek AZALIA PCH INPUTS OUTPUTS
C
ALC269 31~33 14 USB 2.0/1.1 ports PCIe HDMI
ETHERNET (10/100/1000Mb)
25 5V_S5 DDR_VREF_S3
1.2A
MIC In High Definition Audio
6 SATA ports 9
CAMERA CHARGER
SPKR 8 PCIE ports 23 BQ24751 52
1.5W ACPI 1.1
LPC I/F USB 0,1,4 INPUTS OUTPUTS
USB Port x 3 28
PCI/PCI BRIDGE DCBATOUT CHG_PWR
12 18V 6.0A
Blue Tooth 27 CPU DC/DC
2 Cardreader ADP3211 46
MS Pro Duo
HDD 0 SATA Realtek RTS5186 34 /SD(SDHC) 34 INPUTS OUTPUTS
B B
26
8 Mini 1 Card DCBATOUT
VCC_CORE
27A
WLAN/ WIMAX
Flash ROM SPI 1 35
4MB GFX Core
39 ADP3211 50
Giga LAN
PCIe 3 TXFM RJ45 INPUTS OUTPUTS
Atheros AR8131M 30 30
12,13,...,19,20 29
DCBATOUT VCC_GFXCORE
LPC
11A
PCB STACKUP
KBC
Winbond SPI Flash ROM LPC
NPCE781L 128KB SMbus ADDRESS
A TOP L1 39 DEBUG DVT 1ST A
38 CONN.39 DIMM 1 1010 000x b
VCC L2 DIMM 2 1010 001x b
S L3
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
CLK GEN 1110 001x b Taipei Hsien 221, Taiwan, R.O.C.
S L4 Thermal Sensor 0101 110x b
GND L5 Touch INT. Title
CHARGER 0001 001x b BLOCK DIAGRAM
BOTTOM L6 Pad 40 KB 38 Size Document Number Rev
BATTERY 0001 110x b
A3
TUCANA SB
Date: W ednesday, July 07, 2010 Sheet 1 of 56
5 4 3 2 1
A B C D E
PCH
Strapping Processor Strapping
Name Schematics Notes Pin Name Strap Description Configuration (Default value for each bit is Default
SPKR Reboot option at power-up 1 unless specified otherwise) Value
Default Mode: Internal weak Pull-down.
4 No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-k
CFG[4] Embedded 1: Disabled - No Physical Display Port attached to 1 4
- 10-k weak pull-up resistor. DisplayPort Embedded DisplayPort.
Presence 0: Enabled - An external Display Port device is
INIT3_3V# Weak internal pull-down. Do not pull high. connected to the Embedded Display Port.
GNT3#/ Default Mode: Internal pull-up. CFG[3] PCI-Express Static 1: Normal Operation. 1
GPIO55 Low (0) = Top Block Swap Mode (Connect to ground with 4.7-k weak Lane Reversal 0: Lane Numbers Reversed 15 -> 0, 14 -> 1, ...
pull-down resistor).
CFG[0] PCI-Express 1: Single PCI-Express Graphics 1
INTVRMEN High (1) = Integrated VRM is enabled Configuration 0: Bifurcation enabled
Low (0) = Integrated VRM is disabled Select
GNT0#, Default (SPI): Left both GNT0# and GNT1# floating. No pull up
GNT1# required. CFG[7] Reserved - Clarksfield (only for early samples pre-ES1) - 0
Temporarily used Connect to GND with 3.01K Ohm/5% resistor
Boot from PCI: Connect GNT1# to ground with 1-k pull-down
resistor. Leave GNT0# Floating. for early Note: Only temporary for early CFD samples
Clarksfield (rPGA/BGA) [For details please refer to the WW33
Boot from LPC: Connect both GNT0# and GNT1# to ground with 1-k samples. MoW and sighting report].
pull-down resistor. For a common motherboard design (for AUB and CFD),
GNT2#/ Default - Internal pull-up. the pull-down resistor should be used. Does not
GPIO53 Low (0)= Configures DMI for ESI compatible operation (for servers impact AUB functionality.
only. Not for mobile/desktops).
GPIO33 Default: Do not pull low.
3 Disable ME in Manufacturing Mode: Connect to ground with 1-k 3
pull-down resistor.
SPI_MOSI Enable iTPM: Connect to Vcc3_3 with 8.2-k weak pull-up resistor.
Disable iTPM: Left floating, no pull-down required.
NV_ALE Enable Danbury: Connect to Vcc3_3 with 8.2-k weak pull-up
resistor.
Disable Danbury: Connect to ground with 4.7-k weak pull-down
resistor.
NC_CLE Weak internal pull-up. Do not pull low.
HAD_DOCK_EN# Low (0): Flash Descriptor Security will be overridden.
/GPIO[33] High (1) : Flash Descriptor Security will be in effect.
HDA_SDO Weak internal pull-down. Do not pull high.
HDA_SYNC Weak internal pull-down. Do not pull high.
GPIO15 Weak internal pull-down. Do not pull high.
GPIO8 Weak internal pull-up. Do not pull low.
GPIO27 Default = Do not connect (floating)
High(1) = Enables the internal VccVRM to have a clean supply for
analog rails. No need to use on-board filter circuit.
2 Low (0) = Disables the VccVRM. Need to use on-board filter 2
circuits for analog rails.
Resistor Capacitor
100R2J-2-GP
SC4D7U10V5ZY-3GP
-GP=RoHS Part
Before "R" is the Resistance -PAD=no component just
ex: 100R=100 ohm; 49K9R=49.9K ohm layout pad connected 4D7U is the Capacitance -3GP is serial #
ex:4D7U =4.7UF; SC100P=100PF 0=1210 and RoHS Part
80D6R=80.6 ohm 2=0402
2=0402 Serial #; 3=0603 Tolerance
3=0603 Some parts no this # 10V is the Rated Voltage 5=0805 ZY=Y5V
J=5%
5=0805 F=1% 6=1206 MX=X5R
D=0.5% KX=X5R
1 JN=NPO
DVT 1ST
1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
1
C1 DY Title
SC33P50V2JN-3GP
Reference
2
Size Document Number Rev
DY means de-populate A3
TUCANA SB
Date: W ednesday, July 07, 2010 Sheet 2 of 56
5 4 3 2 1
1D5V_S0_CLKGEN
1
1
1
1
C1 C2 C3 C4
SC10U6D3V3MX-GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2
2
2
2
D D
1D5V_S0 1D5V_S0_CLKGEN
1 2
R1
0R3J-0-U-GP
3D3V_S0
1 2 3D3V_CK505
14.31818M HZ
CL=10pF