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5 4 3 2 1
A@ --> Arrandale use
E@ --> Discrete use
ZYB & ZYBA SYSTEM BLOCK DIAGRAM GPU CORE PWR
ISL6264 P44
CHARGER
ISL88731 P38
SW@ --> Switch use GPU IO PWR 3/5V SYS PWR
ISL62827 P45 ISL6237 P39
IV@ --> UMA use
D DISCHARGER CPU CORE PWR D
DDR SYSTEM MEMORY
+3V,+ 5V,+1.5V,+1.05V,+1.1V_VTT
P47 ISL62882 P40
CLOCK GENERATOR Fan Driver
SELGO: SLG8SP595V
BCLK: 133MHz
PEG_CLK: 100MHz
DPLL_REF_SSCLK: 120MHz
intel (PWM Type) +1.0V/+1.5V CPU VTT
ARD: 1.05V
CFD: 1.1V
X'TAL
14.318MHz P3
P36 G93334 + Linear P47 UP61111AQDD P41
Clarksfield w/4 DIMM> * CPU & PCH ISL62881 P46 UP61111AQDD P42
DDR III Dual Channel XDP Conn.
SO-DIMM 0 Arrandale
SO-DIMM 1
800/ 1066 MHz P16 THERMAL DDR3 PWR
SO-DIMM 2 800 MT/s 1066 MT/s
Auburndale PROTECTION P48 TPS5116 P43
SO-DIMM 3 P14, 15 .16. 17 rPGA 989
(37.5mm X 37.5mm)
PCI-E PCIE
X16
P4.5.6.7 AMD GPU
FDI DMI 2.5GT/s HDMI
Broadway-Pro / Madison-Pro
1GB CRT
LVDS
C
*[Arrandale Only] X4 DMI interface P19,20,21,22,23,24,25,26 HDMI P26
C
X'TAL
27.0MHz
Graphics Interfaces
FDI DMI LVDS_CRT_HDMI
INT_HDMI *[Arrandale Only] CRT
HDD (SATA) *2
intel INT_CRT *[Arrandale Only]
Switch Graphics P25
Note:
HM55 does not support USB 6 & 7
HM55 does not support SATA 2 & 3 P31 SATA0
INT_LVDS *[Arrandale Only] P25, 26 LVDS P25
SATA
SATA5 3.0 GT/s
Ibex Peak_M PS8101
SATA1
ODD (SATA) LS
P31 PCI-E
PCI-Express
2.5GT/s
SATA4
USB Port x 4
USB 1, 3, 11, 12 P34 USB 2.0 PCIE-1 & 2
B
(Debug)
USB mBGA 676
(27mm X 25mm) CLKOUT_PEG_1&3
Mini Card B
WLAN / 2
Bluetooth Azalia P8.9.10.11.12.13 RTC USB 10 & 13 P32
HDA P9 PCIE-6
USB 4 P36 X'TAL
CLKOUT_PEG_B
32.768KHz Lan/B
SPI LPC USB10 & 13
CCD
USB 8 P29
Atheros
Giga-LAN
Relteak SPI ROM Winbond
4MB x1 (Basic ME+Braidwood) AR8151
Audio CODEC P9
EC (WPC781) P37 P28 X'TAL
Alcor ALC669X P29 25MHz
CardReader
AU6437
Transformer P28
SPI ROM
P37
A A
Sub-Amplifier Rear Audio Amp
RJ45 Connector
P28
Card Reader
Connector (TPA3111D1) & Head phone
GMT G1453L
Touch Pad
P26 P30
P36 SSID: DISCRETE: 030A
SSID: SWITCH GFX: 0308
PROJECT : ZYB & ZYBA
SUBWOOFER Main SPK S/PDIF Line in MIC Jack Int. D-MIC Quanta Computer Inc.
K/B COON. SVID: 1025
Size Document Number Rev
P30 P30 P30 P30 P30 P125 P30 P36 1A
ZYB Block Diagram
Date: Tuesday, January 12, 2010 Sheet 1 of 51
5 4 3 2 1
1 2 3 4 5 6 7 8
GPU PWR CTRL Option 1 (Default/ VDDR3 before VDDC)
2
+3.3V VIN +1.05V +1.5V +1.5V_SUS +1.8V +5V
dGPU_VRON VDDR3 +3V_D VDDC PG_GPUIO_EN VDDCI PG_1V_EN +1V (DP PLL PWR) PG_1.5V_EN VDDR1 PG_1.5V_EN VDDR4 PG_1.5V_EN BJT dGPU_PWROK
dGPU_PWR_EN# MOS
MOS (AO3413) MAX17007 AO4468 G9334ADJ & MOS MOS (AO4710) MOS (AO6402) AO3413
P22 P44 P45 P47 P43 P43 P22 P22
A +3.3V_GFX (12A) +VGPU_CORE (36A) +1.05V_GFX(2.9A) +1V (3A) +1.5V_GPU (10A) +1.8V_GPU (3A) +5_GPU A
GPU PWR CTRL Option 2 (VDDR3 after VDDR1)
VIN VIN +1.5V +1.5V_SUS +3.3V +1.8V +5V
dGPU_VRON
VDDC PG_GPUIO_EN VDDCI PG_1V_EN +1V (DP PLL PWR) PG_1.5V_EN VDDR1 +1.5V_GPU VDDR3 +3V_D VDDR4 PG_1.5V_EN BJT dGPU_PWROK
dGPU_PWR_EN# MOS
ISL6264 ISL62872 G9334ADJ & MOS MOS (AO4710) MOS (AO3413) MOS (AO6402) AO3413
P44 P45 P47 P43 P22 P43 P22 P22
+VGPU_CORE (20A) +VGPU_IO (4.5A) +1V (3A) +1.5V_GPU (10A) +3_D (0.5A) +1.8V_GPU (3A) +5_GPU
Thermal Follow Chart
Power States
CONTROL
POWER PLANE VOLTAGE DESCRIPTION SIGNAL ACTIVE IN
B
VIN +10V~+19V MAIN POWER ALWAYS ALWAYS B
+VCCRTC +3V~+3.3V RTC POWER ALWAYS ALWAYS NTC
Thermal
+3VPCU +3.3V EC POWER ALWAYS ALWAYS
Protection
+5VPCU +5V CHARGE POWER ALWAYS ALWAYS
+15V +15V CHARGE PUMP POWER ALWAYS ALWAYS
+3V_S5 +3.3V LAN/BT/CIR POWER S5_ON S0-S5 CPU 3V/5 V
H_ORICHOT# PM_THRMTRIP# SYS_SHDN#
CPU
+5V_S5 +5V USB POWER S5_ON S0-S5 CORE PWR H/W Throttling WIRE-AND SYS PWR
+5V +5V HDD/ODD/Codec/TP/CRT/HDMI POWER MAINON S0
+3V +3.3V PCH/GPU/Peripheral component POWER MAINON S0
SML1ALERT#
+1.5V_SUS +1.5V CPU/SODIMM CORE POWER SUSON S0-S3
PCH FAN Driver FAN
+0.75V_DDR_VTT +0.75V SODIMM Termination POWER MAINON S0
+VGFX_AXG variation Internal GPU POWER GFX_ON S0
SM-Bus
+1.8V +1.8V CPU/PCH/Braidwood POWER MAINON S0
C C
+1.5V +1.5V MINI CARD/NEW CARD POWER MAINON S0
EC
+1.1V_VTT +1.05V or +1.1V CPU VTT POWER MAINON S0 CPUFAN#
+1.05V +1.05V PCH CORE POWER MAINON S0
+VCC_CORE variation CPU CORE POWER VRON S0
LCDVCC +3.3V LCD POWER LVDS_VDDEN S0
+VGPUCORE +0.9V~+1.1V GPU CORE POWER dGPU_VRON Discrete enable
+1.05V_GFX +0.9V~+1.1V GPU I/O POWER dGPU_VRON Discrete enable
+1.5V_GFX +1.5V VRAM CORE POWER dGPU_VRON Discrete enable
+1.8V_VGA +1.8V LVDS/PLL POWER dGPU_VRON Discrete enable
+3.3V_GFX +3.3V PEG/HDMI/CRT POWER dGPU_VRON Discrete enable
D D
PROJECT : ZYB & ZYBA
Quanta Computer Inc.
Size Document Number Rev
PWR Status & GPU PWR CRL & THRM 1A
Date: Tuesday, January 12, 2010 Sheet 2 of 51
1 2 3 4 5 6 7 8
5 4 3 2 1
+1.5V U21
L40 *BKP1608HS181T_6_1.5A
3
150mA(30mil) +3V
L38 595@BLM18AG601SN1D/200mA/600ohm_6 +1.5V_CLK 1 80mA(20mil)
C856 VDD_DOT +VDDIO_CLK L41 BKP1608HS181T_6_1.5A
17 15 +1.05V
C855 C524 C529 C548 VDD_SRC VDD_SRC_I/O
24 18
*10u/6.3V_8 VDD_CPU VDD_CPU_I/O C542 C556 C543 C551
D 5 D
*.1u/16V_4 R400 *0_6 .1u/16V_4 .1u/16V_4 .1u/16V_4 VDD_27 C308 may be can save
29 3 CLK_BUF_DREFCLK 10
VDD_REF DOT_96 .1u/16V_4 .1u/16V_4 10u/Y5V_8 10u/Y5V_8
4 CLK_BUF_DREFCLK# 10
CLK_SDATA DOT_96#
31
CLK_SCLK SDA R420 0_4 Place each 0.1uF cap as close as
20mil 32
SCL 27M
6 27M_CLK 20
+3V L39 BLM18AG601SN1D/200mA/600ohm_6 +3V_CLK 7 R427 *0_4 possible to each VDD IO pin. Place
27M_SS
the 10uF caps on the VDD_IO plane.
R386 33_4 CPU_SEL 30 10
10 CLK_ICH_14M REF_0/CPU_SEL SRC_1/SATA CLK_BUF_PCIE_3GPLL 10
C511 C515 C537 11
SRC_1#/SATA# CLK_BUF_PCIE_3GPLL# 10
C516 33p_4 13
SRC_2 CLK_BUF_DREFSSCLK 10
10u/6.3V_8 0.1u/10V_4 0.1u/10V_4 14
SRC_2# CLK_BUF_DREFSSCLK# 10
1
XTAL_IN 28
Y2 XTAL_IN +3V
14.318MHZ XTAL_OUT 27 16 R432 10K_4
Modify on 9/15
XTAL_OUT *CPU_STOP#
2
C517 33p_4 2 20
VSS_DOT CPU_1 TP41
8 19 TP42
VSS_27 CPU_1#
9 23 CLK_BUF_BCLK 10
VSS_SATA CPU_0
12 22 CLK_BUF_BCLK# 10
VSS_SRC CPU_0#
21
VSS_CPU CK_PWRGD_R
26 25
VSS_REF CKPWRGD/PD#
IDT: AL003197002 (ICS9LVS3197BKLFT) 33
GND
Realtek: AL000890000 (RTM890N-632-GRT)
SLG8LV595V
Silego: AL000595000 (SLG8LV595VTR)
C C
CLK Enable
CPU_CLK select Modify on C test SMBus
+3V
+3V +1.05V +3V
R349
2
R464 R359 2.2K_4 R391
*10K_4 *10K_4 1K/F_4
3 1 CLK_SDATA CLK_SDATA 14,15,16,17,34
10,18 ICH_SMBDATA
CPU_SEL Q24 CK_PWRGD_R
2N7002K
3
B Q25 B
R372 2N7002K
10K_4 C518 +3V
*10p/50V/COG_4 41 VR_PWRGD_CK505# 2 R390
100K/F_4
R350
1
2
2.2K_4
0 1
3 1 CLK_SCLK
10,18 ICH_SMBCLK CLK_SCLK 14,15,16,17,34
CPU_SEL CPU0/1=133MHz CPU0/1=100MHz Q23
(default) 2N7002K
A A
PROJECT : ZYB & ZYBA
Quanta Computer Inc.
Size Document Number Rev
1A
Clock Generator
Date: Tuesday, January 19, 2010 Sheet 3 of 51
5 4 3 2 1
5 4 3 2 1
AUBURNDALE/CLARKSFIELD PROCESSOR (DMI,PEG,FDI) AUBURNDALE/CLARKSFIELD PROCESSOR (CLK,MISC,JTAG)
Processor Compensation Signals
4
U27A U27B
B26 PEG_COMP R495 49.9/F_4 R517 20/F_4 H_COMP3 AT23
PEG_ICOMPI COMP3
A26 A16 CLK_CPU_BCLK 11
PEG_ICOMPO BCLK
MISC
A24 B27 R519 20/F_4 H_COMP2 AT24 B16
8 D