Text preview for : MS-6373.pdf part of Microstar MS-6373 Microstar MS-6373.pdf
Back to : MS-6373.pdf | Home
Title Page
Cover Sheet 1
MS-6373 ATX Block Diagram 2
GPIO SPEC 3
Revision 0.B 4 6 2 PGA Socket 4,5
AMD Socket A Processor P L L D e l a y & C P U Ratio Set 6
nVIDIA CRUSH-12/MCP-1 Chipset CRUSH12 7,8,9,10,11
Winbond 83627HF-AW LPC I/O A G P C o nnector 12
ICS 1893 LAN PHY V i d e o s C o nnectors 13
S y s t e m M e mory 1 4 ,15,16
DDR Terminations 17,18
MCP-1 1 9 ,20,21
Last Schematic Update Date: P C I 5 & BIOS 22
CNR Riser 23
08/23/2001
A C ' 9 7 Codec 24
Audio Amplifier 25
Model option table Audio Connectors 26
Model type Function BOM Config ERP BOM No. L A N (PHY) 27
MS6373 Option:STD(Wo/TV) Cfg6373-00B-STD 65/60 1-6373-B10 L A N C o nnector 28
MS6373 Option:A(w/TV) Cfg6373-00B-A 65/60 1-6373-B20 P C I C o nnectors 29,30
MS6373F2 For 4MBO Cfg6373F2-00B-STD 65/60 1-6373-B30 A T A 1 00 Connector 31
USB Connectors 32,33
P C t o P C N e t workling 34
L P C I/O 35
Hardware monitor 36
Parallel Port 37
Serial Port 38
Game Port 39
Keyboard/Mouse Connectors 40
V R M 9 .0 41
Vcore Adjustable & D-LED 42
DDR Regulators 43
System Voltage Regulators 44
Front Panel 45
Pull-up Resistors 46
V R M D e c o upling 47
System Decoupling 48
T V - E ncoder 49 Micro Star Restricted Secret
Title Rev
A u t o B O M M a n ual parts 50 Cover Sheet
Document Number 0B
MS-6373
History 51 MICRO-STAR INT'L CO.,LTD. Last Revision Date:
Wednesday, August 29, 2001
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan Sheet
http://www.msi.com.tw 1 of 50
VRM 462-Pin Socket Processor
Block Diagram
K7 FSB
1 DDR
DIMM
64bit DDR Module
AGP 1.5V 4X w/Fast Write
Connector
CRUSH-12
64 bit DDR
2 DDR
TV -Out
DIMM
EnCoder Modules
LDT Link
UltraDMA 33/66/100
PCI CNTRL
PCI Conn 1~5
IDE Primary & Secondary
MCP-1 PCI ADDR/DATA
USB
USB Port 1 & 2 (Rear)
Power Nets
USB Port 3 & 4 (Front)
VBAT RTC
Flash ROM
USB Port 5 LPC Bus Voltage
5VDUAL Switch
(Front)
MII
LPC SIO Floopy
USB Port 6
VCORE
PWM HIP6301
(Front)
AC'97 Link Game Conn VDD
Onboard
VCC2
VCC2_5 REGULATOR
AC'97 Codec
+5VR
VTT_DDR
Serial
VDDQ
PC to PC
3VDUAL
9VDUAL
Controller
CNR
Parallel
VCC3
5VSB ATX
VCC5
+12V POWER
-12V
-5V
Keyboard Mouse
10/100BaseT
PHY
Micro Star Restricted Secret
Title Rev
Block Diagram
Document Number 0B
MS-6373
MICRO-STAR INT'L CO.,LTD. Last Revision Date:
Wednesday, August 29, 2001
No. 69, Li-De St, Jung-He City, Sheet
Taipei Hsien, Taiwan
http://www.msi.com.tw 2 of 50
1
General Spec.
MCP-1 PCI Config. DDR DIMM Config.
GPIO Pin Type Function DEVICE MCP1 INT Pin REQ#/GNT# IDSEL CLOCK CLK GEN PIN OUT DEVICE ADDRESS CLOCK
GPIO 0 I/O PCI_REQ#4 (multifunction pin)
PCI Slot 1 INTA# PCI_REQ#0 AD16 PCICLK0 MCP1/AB20 (PCI_CLK0) DIMM 1 1010000B MCLK_A0/MCLK_A0#
GPIO 1 I/O PCI_GNT#4 (multifunction pin) INTB# PCI_GNT#0 (A0h) MCLK_A1/MCLK_A1#
INTC# MCLK_A2/MCLK_A2#
GPIO 2 I/O PCI_PERR# (multifunction pin)
INTD#
GPIO 3 I PCI_IRQ#E (multifunction pin) DIMM 2 1010001B MCLK_B0/MCLK_B0#
PCI Slot 2 INTB# PCI_REQ#1 AD17 PCICLK1 MCP1/AB18 (PCI_CLK1) (A2h) MCLK_B2/MCLK_B2#
GPIO 4 I MII_RXER (multifunction pin)
INTC# PCI_GNT#1 MCLK_B4/MCLK_B4#
GPIO 5 I Pull up through 8.2K ohms (LPC_DRQ#1) INTD#
INTA# DIMM 3 1010010B MCLK_B1/MCLK_B1#
GPIO 6 I USB_OC1# (multifunction pin) (A4h) MCLK_B3/MCLK_B3#
GPIO 7 I USB_OC2# (multifunction pin) PCI Slot 3 INTC# PCI_REQ#2 AD18 PCICLK2 MCP1/AB12 (PCI_CLK2) MCLK_B5/MCLK_B5#
INTD# PCI_GNT#2
GPIO 8 I USB_OC2# (multifunction pin)
INTA#
GPIO 9 I USB_OC3# (multifunction pin) INTB#
MII EEPROM Config.
GPIO 10 I USB_OC3# (multifunction pin)
PCI Slot 4 INTD# PCI_REQ#3 AD19 PCICLK3 MCP1/AB8 (PCI_CLK3) 1010011B (A6h)
GPIO 11 I AC_SDIN1 (multifuntion pin) INTA# PCI_GNT#3
INTB#
GPIO 12 I A20GATE (multifuntion pin)
INTC# CNR Config.
GPIO 13 O SPDIF OUT(multifuntion pin) 1010100B (A8h)
PCI Slot 5 INTA# PCI_REQ#4 AD20 PCICLK4 MCP1/AB6 (PCI_CLK4)
GPIO 14 I/O CNR Detected
INTB# PCI_GNT#4
GPIO 15 I/O SPDIF switch control INTC# W83601 Config.
INTD#
GPIO 16 I/O P u l l Up to 3.3V through 1K ohms (BIOS protect) 1010111B (AEh)
GPIO 17 I/O Pull up through 8.2K ohms (PRDY#)
A
GPIO 18 I/O P r imary IDE ATA66/100 detection (CPUSLP#)
LPC I/O W83601 A
GPIO 19 I/O SLPBTN# (multifunction pin)
GPIO Pin Type Function GPIO Pin Type Function
GPIO 20 I/O S e condary IDE ATA66/100 detection (SLP_S1#)
GPIO 24 I/O D-LED 1 (H=Green;L=Red) GP10 I/O CPU FID0
GPIO 21 I/O EXTSMI# (multifunction pin)
GPIO 32 I/O D-LED 4 (H=Red;L=Green) GP11 I/O CPU FID1
GPIO 22 I/O THERM# (multifuntion pin)
GPIO 33 I/O D-LED 2 (H=Red;L=Green) GP12 I/O CPU FID2
GPIO 23 I/O N/C (INTRUDER#)
GPIO 34 I/O D-LED 3 (H=Red;L=Green) GP13 I/O CPU FID3
GPIO 24 I/O RI# (multifuntion pin)
GP14 I/O R A TIO_SET (H=H/W Default ; L=BIOS Setting)
GPIO 25 I/O KBRST# (multifuntion pin)
GP15 I/O H/W Reset#
SPIO 0 I/O SM_CLK0 (multifuntion pin)
GP16 I/O FSB Clock (H=100;L=133)
SPIO 1 I/O SM_DATA0 (multifuntion pin)
GP17 I/O N/C
SPIO 2 I/O SM_CLK1 (multifuntion pin)
GP20 I/O Pull-High (A0)
SPIO 3 I/O SM_DATA1 (multifuntion pin)
GP21 I/O Pull-High (A1)
SPIO 4 I/O DDC_CLK (multifuntion pin)
GP22 I/O Pull-High (A2)
SPIO 5 I/O DDC_DATA (multifuntion pin)
GP23 I/O DDR SET1
SPIO 6 I Pull up through 4.7K ohms (SMB_ALERT#)
GP24 I/O DDR SET2
GP25 I/O N/C
BIOS Protect Config. SPDIF output control Config. GP26 I/O N/C
BIOS Un_Protected 1 Analog output 1(default)
BIOS Protected 0 SPDIF output 0
DDR Voltage SET1 SET2
2.5V 1 1
2.6V 1 0
2.7V 0 1
Micro Star Restricted Secret
2.8V 0 0 Title Rev
GPIO SPEC
Document Number 0B
MS-6373
MICRO-STAR INT'L CO.,LTD. Last Revision Date:
Wednesday, August 29, 2001
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan Sheet
http://www.msi.com.tw 3 of 50
1
SDATA#0 AA35 AE1 A20M#
SDATA0 A20M A20M# (20)
Socket A Part 1
SDATA#1 W37 AG1 FERR
SDATA1 FERR
SDATA#2
**All CPU interface are 2.5V tolerant**
W35 AJ3 CPUINIT#
SDATA#3 SDATA2 INIT CPUINIT# (20,22) VCORE
Y35 AL1 INTR
SDATA#4 U35 SDATA3 INTR AJ1 IGNNE# INTR (20)
SDATA#5 U33 SDATA4 IGNNE AN3 NMI IGNNE# (20)
SDATA#6 SDATA5 NMI CPURST# NMI (20) VCC2 DBREQ# R126 1
S37 AG3 2 510
SDATA#7 S33 SDATA6 RESET AN5 SMI# CPURST# (7,20)
SDATA7 SMI SMI# (20)
SDATA#8 AA33 AC1 STPCLK# C615 1 2 X_68p PLLTEST# R1291 2 510
SDATA#9 AE37 SDATA8 STPCLK STPCLK# (20)
SDATA#10 AC33 SDATA9 AE3 APICD0# R217 1 2 220_0603
SDATA10 PWROK PWRGOOD (44)
SDATA#11 AC37 C104 1 2 68p RN33
SDATA#12 SDATA11 APICD1# R220 1
Y37 2 220_0603 CPU_TDI 1 2
SDATA#13 AA37 SDATA12 N1 APICCLK_CPU CPU_TRST# 3 4
SDATA13 PICCLK APICCLK_CPU (7)
SDATA#14 AC35 N3 APICD0# CPU_TCK 5 6
SDATA14 PICD0/BYPASSCLK APICD0# (20) COREFB# (40)
(7) SDATA#[63..0] SDATA#[63..0] SDATA#15 S35 N5 APICD1#
APICD1# (20)
CPU_TMS 7 8
1
SDATA#16 Q37 SDATA15 PICD1/BYPASSCLK
SDATA#17 Q35 SDATA16 AG13 COREFB# C562 VCORE 8P4R-510
SDATA#18 N37 SDATA17 COREFB- AG11 COREFB X_102P
SDATA18 COREFB+
2
SDATA#19 J33 RN35
COREFB (40)
1
SDATA#20 SDATA19 CPUCLK_R VCORE NMI
G33 AN17 1 2
2
2
SDATA#21 G37 SDATA20 CLKIN AL17 CPUCLK#_R INTR 3 4
SDATA#22 E37 SDATA21 CLKIN R210 SMI# 5 6
1
SDATA#23 G35 SDATA22 AN19 R135 R136 100 CPUINIT# 7 8
SDATA#24 Q33 SDATA23 RSTCLK AL19 10K 10K
SDATA24 RSTCLK
2
SDATA#25 N33 R206 FERR# 8P4R-680
SDATA25 FERR# (20)
SDATA#26 CLKOUT 680
1
1
L33 AL21
SDATA#27 N35 SDATA26 K7CLKOUT AN21 CLKOUT# RN36
SDATA#28 SDATA27 K7CLKOUT VCORE FERR Q25 STPCLK#
2
L37 1 2
SDATA#29 J37 SDATA28 T h e farest VCORE and GND 2N3904S A20M# 3 4
SDATA#30 A37 SDATA29 AJ13 IGNNE# 5 6
SDATA#31 E35 SDATA30 ANALOG 7 8
SDATA#32 E31 SDATA31 AA5 VREFMODE
SDATA#33 E29 SDATA32 SYSVREFMODE W5 VREF_SYS 8P4R-680
SDATA#34 A27 SDATA33 VREF_SYS
SDATA#35 A25 SDATA34 AC5 ZN PLLMON1 R1331 562
SDATA#36 E21 SDATA35 ZN AE5 ZP VCORE
SDATA#37 C23 SDATA36 ZP RN24 PLLMON2 R1321 562
SDATA#38 SDATA37 PLLBP#
462-Pin Socket
C27 AJ25 1 2
SDATA#39 A23 SDATA38 PLLBYPASS AN15 3 4 VCORE FLUSH# R1311 680
2
SDATA#40 SDATA39 PLLBYPASSCLK (7) CPUCLK0
A35 AL15 5 6
SDATA#41 C35 SDATA40 PLLBYPASSCLK 7 8 C140 PLLBP# R1151 680
2
SDATA#42 SDATA41 PLLMON1 R112
C33 AN13 CPUCLK_R 1 2 1 2
SDATA#43 C31 SDATA42 PLLMON1 AL13 PLLMON2 8P4R-100
Part 1
X_60.4RST
1
SDATA#44 A29 SDATA43 PLLMON2 AC3 PLLTEST# 680P CPURST# R617 680
SDATA#45 C29 SDATA44 PLLTEST
SDATA#46 E23 SDATA45 R121
SDATA#47 C25 SDATA46 S1 SCANCLK1 X_301RST
SDATA#48 E17 SDATA47 SCANCLK1 S5 SCANCLK2 C141 RN32
SDATA48 SCANCLK2 R113
2
SDATA#49 E13 S3 SINTVAL CPUCLK#_R 1 2 1 2 SSHIFTEN 1 2
SDATA#50 E11 SDATA49 SCANINTEVAL
Q5 SSHIFTEN SCANCLK1 3 4
SDATA#51 C15 SDATA50 SCANSHIFTEN 680P X_60.4RST SINTVAL 5 6
SDATA#52 SDATA51 SCANCLK2
E9
SDATA52 DBRDY
AA1 (7) CPUCLK#0 Near socket-A 7 8
SDATA#53 A13 AA3 DBREQ#
SDATA#54 C9 SDATA53 DBREQ
AL3 FLUSH# 8P4R-270
SDATA#55 A9 SDATA54 FLUSH
SDATA#56 C21 SDATA55 Q1 CPU_TCK
SDATA#57 A21 SDATA56 TCK U1 CPU_TDI FILVAL# R101 1 2 270 VCORE
SDATA#58 E19 SDATA57 TDI
U5 DOVAL# R102 1 2 270
SDATA#59 C19 SDATA58 TDO Q3 CPU_TMS AIN#0 R98 1 2 680
SDATA#60 C17 SDATA59 TMS
U3 CPU_TRST# AIN#1 R99 1 2 680
SDATA#61 A11 SDATA60 TRST VCORE
SDATA#62 SDATA61
A17
SDATA#63 A15 SDATA62 L1 VIDA0 VIDA0 (41)
1
SDATA63 VID0 L3 VIDA1
VID1 VIDA1 (41) VCORE
L5 VIDA2
VIDA2 (41)
DICLK#[3..0] DICLK#0 VID2 VIDA3 R120
(7) DICLK#[3..0] W33 L7 VIDA3 (41)
SDATAINCLK0 VID3
DICLK#1 J35
SDATAINCLK1 VID4
J7 VIDA4
VIDA4 (41) 0.5 X VCORE 100RST ZN R128 56
DICLK#2 E27
SDATAINCLK2 Power Up Strappings :
2
DICLK#3 E15 VREF_SYS ZP R130 56
SDATAINCLK3 W1 FID0
FID0 (6)
1
-DIVAL AN33 FID0 W3 FID1
(7) -DIVAL FID1 (6) CFID[3:0] => CPU Clock Multiplier
1
1
SDATAINVAL FID1 FID2
Y1 FID2 (6)
FID2
(7) DOCLK#[3..0]
DOCLK#[3..0] DOCLK#0 AE35
SDATAOUTCLK0 FID3
Y3 FID3
FID3 (6) 0000 3 1000 7 C137 C136 R124 match the transmission line
DOCLK#1 C37 0001 3.5 1001 7.5 473P 104P 100RST Push-Pull compensation circuit
SDATAOUTCLK1
2
2
DOCLK#2 A33 0010 4 1010 8
DOCLK#3 SDATAOUTCLK2
0011 4.5 1011 8.5
2
C11 U37
SDATAOUTCLK3 SCHECK0 Y33 VCORE
SCHECK1 0100 5 1100 9
DOVAL# AL31 L35 0101 5.5 1101 9.5 RN23
SDTATOUTVAL SCHECK2 E33 1 2
AIN#0 SCHECK3 0110 6 1110 10
CLKOUT#
AJ29
SADDIN0 SCHECK4
E25 0111 6.5 1111 Reserved 3 4
AIN#1 AL29 A31 CLKOUT 5 6
AIN#[14..2] AIN#2 AG33 SADDIN1 SCHECK5 C13 7 8
(7) AIN#[14..2] SADDIN2 SCHECK6
AIN#3 AJ37 A19
AIN#4 AL35 SADDIN3 SCHECK7 VCORE 8P4R-100
AIN#5 AE33 SADDIN4 J1
AIN#6 SADDIN5 SADDOUT0
AJ35 J3 * Trace lengths of CLKOUT
1
AIN#7 AG37 SADDIN6