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8 7 6 5 4 3 2 1
Cover Sheet 1
Block Diagram 2
D D
MAIN CLOCK GEN & DDR CLOCK BUFFER 3
mPGA478-B INTEL CPU Sockets 4-5
MS-6533 VERSION:2.0 SIS 645/650 NORTH BRIDGE 6-9
SIS 645/650 CHIPSET DDR SLOT 10
Willamette/Northwood 478pin mPGA-B Processor Schematics DDR TERMINATOR 11
SIS 961A SOUTH BRIDGE 12 - 14
AGP SLOT 15
CPU: PCI SLOTS 16
C Willamette/Northwood mPGA-478B Processor C
LAN CONTROLLER 17
System Brookdale Chipset: RJ45 CONNECTOR 18
SIS 645/650 (North Bridge) IDE CONNECTOR 19
+961A (South Bridge)
USB CONNECTOR 20
On Board Chipset: AC'97 CODEC 21
LPC Super I/O -- W83697HF AUDIO CONNECTOR 22
Expansion Slots: CNR & FAN 23
B AGP2.0 SLOT * 1 LPC I/O(W83697HF) 24 B
PCI2.2 SLOT* 3 PARALLEL & SERIAL PORT 25
CNR SLOT * 1 VRM 9.X 26
ACPI CONTROLLER 27
ATX POWER CON & VGA CON 28
FRONT PANEL 29
Decoupling Capacitor 30
History 31
A A
MICRO-STAR INT'L CO.,LTD.
Title
COVER PAGE
Size Document Number Rev
MS-6533 20
Date: Tuesday, January 15, 2002 Sheet 1 of 32
8 7 6 5 4 3 2 1
5 4 3 2 1
System Block Diagram GPIO Table on SIS961
GPIO_0 I/O MAIN Pull-Down
D
GPIO_1 I/O MAIN Pull-Down D
GPIO_2 I/O MAIN THERM#
SOCKET-478 GPIO_3 I/O MAIN EXTSMI#
GPIO_4 I/O MAIN Pull-Down
GPIO_5 I/O MAIN PREQ#5(Pull-Up)
GPIO_6 I/O MAIN PGNT#5(Pull-Up)
GPI_7 I/O RESUME Pull-Down
Host Bus GPI_8 I RESUME RING
GPI_9 I RESUME RESERVED
GPI_10 I RESUME Pull-Down
Support Dual Monitor
SSTL-2 Termination GPIO_11 I/O RESUME RESERVED
VGA
D-SUB
AGP SLOT DDR SDRAM (Only for DDR) GPIO_12 I/O RESUME Pull-Down
GPIO_13 I/O RESUME Flash Rom protection H: Disable, L: Enable
SIS645/650 GPIO_14 I/O RESUME LAN_WAKE#
DIMM 1 DIMM 2 Rtt
VGA Connector VGA CONNECTOR VGA GPIO_15 I/O RESUME KBDAT
C
GPIO_16 I/O RESUME KBCLK C
GPIO_17 I/O RESUME MSDAT
GPIO_18 I/O RESUME MSCLK
GPIO_19 I/O RESUME SMBCLK
HyperZip Analog In GPIO_20 I/O RESUME SMBDAT
Support Max to six-PCI Devices
512 MB
AC'97
Audio Codec
Lan PCI SLOT 3 PCI SLOT 2 PCI SLOT 1 Analog Out
SiS961 CNR
IDE 1 IDE 2
KEYBOARD PS/2
/MOUSE
USB 0 USB 2
B USB 1 USB 3 B
LPC Bus
FAN FAN FAN CONTROL VOLTAGE MONITOR
1 2
TEMPERATURE MONITOR
LPC Super I/O
Legacy
ROM
GPIOs IR/CIR GAME/MIDI SERIAL PARALLEL FLOPPY
A A
MICRO-STAR INT'L CO.,LTD.
Title
System Block Diagram
Size Document Number Rev
MS-6533 20
Date: Tuesday, January 15, 2002 Sheet 2 of 32
5 4 3 2 1
5 4 3 2 1
VCC3
VCC3
Main Clock Generator
CE11
CB195 CB184
10u CPUCLK0 R215 49.9
L48 CP24 0.1u 1000p CPUCLK-0 R216 49.9
X_COPPER
CPUCLK1 R213 49.9
X_80_0805 CPUCLK-1 R214 49.9
U15
D ICS-ICS952001AF-SSOP48 D
SDCLK C110 X_10p
1
11 VDDREF
13 VDDZ AGPCLK0 C111 X_10p_0603
19 VDDPCI
28 VDDPCI AGPCLK1 C112 X_10p_0603
CE7 CB178 CB177 CB196 CB197 CB179 29 VDD48
0.1u 0.1u 0.1u CB180 0.1u CB182 CB198 42 VDDAGP
10u 0.1u 0.1u 0.1u 0.1u 48 VDDCPU 40 R237 CPUCLK0 ZCLK0 C163 X_10p_0603
33 CPUCLK0 4
VDDSD CPUCLK0 39 R238 CPUCLK-0
33 CPUCLK-0 4
12 CPUCLK#0 ZCLK1 C164 X_10p_0603
45 PCI_STOP# 44 R235 33 CPUCLK1
CPU_STOP# CPUCLK1 43 R236 CPUCLK-1 CPUCLK1 6
33 CPUCLK-1 6
CPUCLK#1
5 47 R234 22 SDCLK CN18 X_10p
VSSREF SDCLK SDCLK 7
8 PCICLK2 1 2
18 VSSZ 31 R239 22 AGPCLK0 PCICLK1 3 4
VSSPCI AGPCLK0 AGPCLK0 6
24
VSSPCI AGPCLK1
30 R240 22 AGPCLK1
AGPCLK1 15 MULTISEL internal Pull-Up 120K SIOPCLK 5 6
25 96XPCLK 7 8
32 VSS48 9 R289 ZCLK0
22 ZCLK0 8
41 VSSAGP ZCLK0 10 R290 22 ZCLK1 R243 X_4.7K
46 VSSCPU ZCLK1 ZCLK1 12 VCC3
CN19 1 2 X_10p
VSSSD 14 FS3 RN76 7 8 33 96XPCLK MULTISEL R220 X_4.7K PCICLK5 3 4
PCICLK_F0/FS3 96XPCLK 12
VCC3 VCC3 15 FS4 5 6 SIOPCLK PCICLK4 5 6
PCICLK_F1/FS4 SIOPCLK 24
16 3 4 PCICLK1 PCICLK3 7 8
PCICLK0 PCICLK1 16
17 1 2 PCICLK2
PCICLK1 20 PCICLK2 16
RN77 33
R219 R218 PCICLK2 21 7 8 PCICLK3 APICCLK C161 X_10p_0603
PCICLK3 PCICLK3 16
10K 10K 22 5 6 PCICLK4
PCICLK4 PCICLK4 16
23 3 4 PCICLK5
C PCICLK5 PCICLK5 17 C
1 2 REFCLK0 C153 X_10p_0603
33 2 FS0
VCCP PD#/VTT_PWRGD REF0/FS0 3 FS1 R283 REFCLK0 REFCLK1 C160 X_10p_0603
33 REFCLK0 8
REF1/FS1 4 FS2 R285 REFCLK1
R207 33 REFCLK1 13
Q27 Q26 R217 38 REF2/FS2 R286 APICCLK REFCLK2 C162 X_10p_0603
475 33 APICCLK 13
IREF 27 R287 X_33 REFCLK2
48M 26 REFCLK2 21
10K NPN-MBT3904LT1-S-SOT23
NPN-MBT3904LT1-S-SOT23 24_48M/MULTISEL R241 UCLK48M UCLK48M C113 10p_0603
22 UCLK48M 14
MULTISEL R242 22 SIO48M
SIO48M 24
CP26 X_COPPER SIO48M C114 10p_0603
35
VCC3 SCLK 34
SDATA
L49 SMBCLK SMBCLK C251 X_10p
SMBCLK 10,13,23,27
36 SMBDAT
VDDA SMBDAT 10,13,23,27
X_80_0805 SMBDAT C252 X_10p
CB194 CB187 CB181 VCC3
F0~F4 internal Pull-Down 120K
0.1u 0.1u 1000p
37
VSSA FS0 BSEL0 4
R291 2.7K
R292 X_2.7K FS1
XOUT
R288 X_2.7K R542 X_10K FS2 DDRCLK0 C58 X_10p_0603
XIN
R271 X_2.7K FS3
R276 X_2.7K R543 X_10K FS4 DDRCLK1 C59 X_10p_0603
CP11 X_COPPER
6
7
DDRCLK2 C62 X_10p_0603
VCC2.5V
L28 Y1 DDRCLK3 C64 X_10p_0603
B B
CBVDD FS4 FS3 FS2 FS1 FS0 CPU SDRAM ZCLK AGP PCI
X_80_0805
14M-32pf-HC49S-D 0 0 0 0 1 100 100 66 66 33
CB87 CB110 CB111
C143 C134
0.1u 0.1u 0.1u
27p 27p 1 0 1 0 1 133 100 66 66 33
DDRCLK8 C39 X_10p_0603
CE5 + CB126 CB127
0.01u DDRCLK7 C42 X_10p_0603
10u 0.1u
U7
ICS-ICS93722BF-SSOP28
Clock Buffer (DDR) DDRCLK-0 C57 X_10p_0603
DDRCLK-1 C60 X_10p_0603
CP14 X_COPPER CBVDD 3
12 VDD 2 R111 DDRCLK0 DDRCLK-2 C61 X_10p_0603
0
23 VDD CLK0 4 R112 DDRCLK1 DDRCLK[0..8]
0 DDRCLK[0..8] 10
VDD CLK1 13 R115 0 DDRCLK2 DDRCLK-3 C63 X_10p_0603
L32 CLK2 17 R118 0 DDRCLK3 DDRCLK-[0..8]
10 CLK3 24 R82 DDRCLK8 DDRCLK-[0..8] 10
0
VCC2.5V AVDD CLK4 26 R85 DDRCLK7
0
X_80_0805 + CE4 CB124 CB118 CLK5
10u R116 0 7 1 R110 0 DDRCLK-0
0.1u 0.01u R86 0 22 SCLK CLK#0 5 R113 0 DDRCLK-1 DDRCLK-8 C40 X_10p_0603
SDATA CLK#1 14 R114 DDRCLK-2
0
8 CLK#2 16 R117 DDRCLK-3 DDRCLK-7 C41 X_10p_0603
0
SMBCLK CLK_IN CLK#3 25 R83 DDRCLK-8
0
SMBDAT CLK#4 27 R84 0 DDRCLK-7
20 CLK#5
A FB_IN A
FWDSDCLKO
7 FWDSDCLKO
9 19 R87 22 FB_OUT
18 NC FB_OUT
21 NC
NC C43 MICRO-STAR INT'L CO.,LTD.
GND
GND
GND
GND
10p_0603
Title
11
15
28
6
MAIN CLOCK GEN & BUFFER
Size Document Number Rev
MS-6533 20
Date: Monday, February 25, 2002 Sheet 3 of 32
5 4 3 2 1
8 7 6 5 4 3 2 1
C P U G T L R E F E RNCE VOLTAGE BLOCK
VCCP
Length < 1.5inch. R61
CPU SIGNAL BLOCK GTLREF1
2/3*Vccp 49.9
C21 C22 C30 R62
220p 220p 1u 100
6 HA#[3..31]
D D
VID[0..4] 26
HA#31
HA#30
HA#29
HA#28
HA#27
HA#26
HA#25
HA#24
HA#23
HA#22
HA#21
HA#20
HA#19
HA#18
HA#17
HA#16
HA#15
HA#14