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A B C D E
1 1
2
Compal Confidential 2
Schematics Document
AMD S1/ ATI RS690MC / SB600
2007 / 1 / 10 Rev:0.3
3 3
4 4
Security Classification Compal Secret Data
Issued Date 2008/1/3 Deciphered Date 2009/01/3 Title
Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4191P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 14, 2008 Sheet 1 of 39
A B C D E
A B C D E
Compal confidential
Project Code: ANRJBL3000(JBL30) AMD S1g1 CPU
Thermal Sensor Clock Generator Turion64 x2 TLxx / Sempron DDR2 DDR2-SO-DIMM X2
File Name : LA-4191P
ADM1032ARM ICS951462 page 8,9
1 PCB P/N: DA600007000 page 4,5,6,7 1
page 6 page 13 Dual Channel DDR2
HT 16x16 800MHZ
USB port0~3
CRT RGB USB conn x 4
page 28
page 14 ATI-RS690M(C)
USB port8
LCD CONN LVDS BGA465 Mini Card
page 25
page 14 page 10,11,12
USB port6
Express Card
page 27
PCI EXPRESS A-Link Express
4 x PCIE USB port5
Finger Printer
page 28
USB port7
2 Realtek Express Card Mini Card Bluetooth
2
RTL8111C/8102E (New Card) WLAN USB2.0 page 28
page 22
page 27 page 25
ATI-SB600 USB port9
BGA548 Camera Mic Array
page 28
RJ45 CONN
page 22 USB port4
PCI BUS Felica Conn
page 15,16,17,18 page 28
Audio CKT
HD-Interface AMP & Audio Jack
ALC268 page 24
Media Card Controller page 23
O2 OZ129
page 20 LPC BUS SATA HDD Conn.
SATA page 19
3 3
Media Card 1394
Conn. PATA CDROM Conn.
page 20 page 28 page 19
Option
Power On/Off CKT.
page 29
TPM1.2
page 26
DC/DC Interface CKT. RTC CKT.
page 30 page 15
ENE KB926
page 26
Power Circuit DC/DC Power OK CKT.
page 31~38 page 29
Int. KBD
page 27
4
Touch Pad 4
CONN.page 27 SPI BIOS
page 26
Security Classification Compal Secret Data
Issued Date 2008/1/3 Deciphered Date 2009/01/3 Title
Block Diagrams
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4191P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 14, 2008 Sheet 2 of 39
A B C D E
A B C D E
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
Power Plane Description S1 S3 S4/ S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
VIN Adapter power supply (19V) ON ON ON S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
B+ AC or battery power rail for power circuit. ON ON ON
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+CPU_CORE Core voltage for CPU ON OFF OFF
+1.2V_HT 1.2V switched power rail ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+0.9V 0.9V switched power rail for DDR terminator ON ON OFF
+1.2VALW 1.2V always on power rail ON ON ON
+1.5VS 1.5V switched power rail ON OFF OFF Board ID Table for AD channel
+1.8VS 1.8V switched power rail ON OFF OFF Vcc 3.3V +/- 5%
+1.8V 1.8V power rail for DDR ON ON OFF Ra / Rc 100K +/- 5%
+3VALW 3.3V always on power rail ON ON ON Board ID Rb / Rd V AD_BID min V AD_BID typ V AD_BID max
+3V 3.3V power rail ON ON OFF 0 0 0 V 0 V 0 V
+3VS 3.3V switched power rail ON OFF OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+5VALW 5V always on power rail ON ON ON 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+5VS 5V switched power rail ON OFF OFF 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+RTCVCC RTC power ON ON ON 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
5 100K +/- 5% 1.453 V 1.650 V 1.759 V
6 200K +/- 5% 1.935 V 2.200 V 2.341 V
7 NC 2.500 V 3.300 V 3.300 V
2 2
BOARD ID Table BTO Option Table
External PCI Devices Board ID PCB Revision BTO Item BOM Structure
Device IDSEL# REQ#/GNT# Interrupts 0 0.1 0.2
OZ129 AD21 0 PIRQG 1 0.3
2
3
4
5
6
7
EC SM Bus1 address EC SM Bus2 address
3 3
Device Address Device Address
Smart Battery 0001 011X b? ADM1032 1001 110X b?
EEPROM(24C16/02) 1010 000X b?
(24C04) 1011 000Xb?
SB600 SM Bus address
Device Address
Clock Generator 1101 001Xb?
(ICS 951462AGT)
DDRII DIMM0 1001 000Xb?
DDRII DIMM2 1001 010Xb?
4 4
Security Classification Compal Secret Data
Issued Date 2008/1/3 Deciphered Date 2009/01/3 Title
Notes
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4191P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 14, 2008 Sheet 3 of 39
A B C D E
5 4 3 2 1
H_CADIP[0..15] H_CADOP[0..15]
10 H_CADIP[0..15] H_CADOP[0..15] 10
H_CADIN[0..15] H_CADON[0..15]
10 H_CADIN[0..15] H_CADON[0..15] 10
PROCESSOR HYPERTRANSPORT INTERFACE
VLDT_Ax AND VLDT_Bx ARE CONNECTED TO THE LDT_RUN POWER
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
D D
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE
+1.2V_HT
CPU1A
1A D4 VLDT_A3 VLDT_B3 AE5 1 2
D3 AE4 C394 4.7U_0805_6.3V6K~N
VLDT_A2 VLDT_B2
D2 VLDT_A1 VLDT_B1 AE3
D1 VLDT_A0 VLDT_B0 AE2
H_CADIP15 N5 T4 H_CADOP15
H_CADIN15 L0_CADIN_H15 L0_CADOUT_H15 H_CADON15
P5 L0_CADIN_L15 L0_CADOUT_L15 T3
H_CADIP14 M3 V5 H_CADOP14
H_CADIN14 L0_CADIN_H14 L0_CADOUT_H14 H_CADON14
M4 L0_CADIN_L14 L0_CADOUT_L14 U5
H_CADIP13 L5 V4 H_CADOP13
H_CADIN13 L0_CADIN_H13 L0_CADOUT_H13 H_CADON13
M5 L0_CADIN_L13 L0_CADOUT_L13 V3
H_CADIP12 K3 Y5 H_CADOP12
H_CADIN12 L0_CADIN_H12 L0_CADOUT_H12 H_CADON12
K4 L0_CADIN_L12 L0_CADOUT_L12 W5
H_CADIP11 H3 AB5 H_CADOP11
H_CADIN11 L0_CADIN_H11 L0_CADOUT_H11 H_CADON11
H4 L0_CADIN_L11 L0_CADOUT_L11 AA5
H_CADIP10 G5 AB4 H_CADOP10
H_CADIN10 L0_CADIN_H10 L0_CADOUT_H10 H_CADON10
H5 L0_CADIN_L10 L0_CADOUT_L10 AB3
H_CADIP9 F3 AD5 H_CADOP9
H_CADIN9 L0_CADIN_H9 L0_CADOUT_H9 H_CADON9
F4 L0_CADIN_L9 L0_CADOUT_L9 AC5
H_CADIP8 E5 AD4 H_CADOP8
H_CADIN8 L0_CADIN_H8 L0_CADOUT_H8 H_CADON8
F5 L0_CADIN_L8 L0_CADOUT_L8 AD3
H_CADIP7 N3 T1 H_CADOP7
H_CADIN7 L0_CADIN_H7 L0_CADOUT_H7 H_CADON7
N2 L0_CADIN_L7 L0_CADOUT_L7 R1
H_CADIP6 L1 U2 H_CADOP6
H_CADIN6 L0_CADIN_H6 L0_CADOUT_H6 H_CADON6
M1 L0_CADIN_L6 L0_CADOUT_L6 U3
C H_CADIP5 H_CADOP5 C
L3 L0_CADIN_H5 L0_CADOUT_H5 V1
H_CADIN5 L2 U1 H_CADON5
H_CADIP4 L0_CADIN_L5 L0_CADOUT_L5 H_CADOP4
J1 L0_CADIN_H4 L0_CADOUT_H4 W2
H_CADIN4 K1 W3 H_CADON4
H_CADIP3 L0_CADIN_L4 L0_CADOUT_L4 H_CADOP3
G1 L0_CADIN_H3 L0_CADOUT_H3 AA2
H_CADIN3 H1 AA3 H_CADON3
H_CADIP2 L0_CADIN_L3 L0_CADOUT_L3 H_CADOP2
G3 L0_CADIN_H2 L0_CADOUT_H2 AB1
H_CADIN2 G2 AA1 H_CADON2
H_CADIP1 L0_CADIN_L2 L0_CADOUT_L2 H_CADOP1
E1 L0_CADIN_H1 L0_CADOUT_H1 AC2
H_CADIN1 F1 AC3 H_CADON1
H_CADIP0 L0_CADIN_L1 L0_CADOUT_L1 H_CADOP0
E3 L0_CADIN_H0 L0_CADOUT_H0 AD1
H_CADIN0 E2 AC1 H_CADON0
L0_CADIN_L0 L0_CADOUT_L0
H_CLKIP1 J5 Y4 H_CLKOP1
10 H_CLKIP1 L0_CLKIN_H1 L0_CLKOUT_H1 H_CLKOP1 10
H_CLKIN1 K5 Y3 H_CLKON1
10 H_CLKIN1 L0_CLKIN_L1 L0_CLKOUT_L1 H_CLKON1 10
H_CLKIP0 J3 Y1 H_CLKOP0
10 H_CLKIP0 L0_CLKIN_H0 L0_CLKOUT_H0 H_CLKOP0 10
H_CLKIN0 J2 W1 H_CLKON0
10 H_CLKIN0 L0_CLKIN_L0 L0_CLKOUT_L0 H_CLKON0 10
+1.2V_HT
R236 1 2 51_0402_1% P3 T5
R235 1 L0_CTLIN_H1 L0_CTLOUT_H1
2 51_0402_1% P4 L0_CTLIN_L1 L0_CTLOUT_L1 R5
H_CTLIP0 N1 R2 H_CTLOP0
10 H_CTLIP0 L0_CTLIN_H0 L0_CTLOUT_H0 H_CTLOP0 10
H_CTLIN0 P1 R3 H_CTLON0
10 H_CTLIN0 L0_CTLIN_L0 L0_CTLOUT_L0 H_CTLON0 10 FAN1 Control and Tachometer +5VS
Athlon 64 S1
Processor Socket
1
2006-10-17 Change from 49.9 1% to 51 1% D3
1SS355_SOD323 @
B @ B
2
2 1
D14 1N4148_SOT23
C424
10U_0805_10V4Z~N
2 1
+5VS
+1.2V_HT C113
1000P_0402_50V7K~N 1 2
2 1 C410 10U_0805_10V4Z~N
U20
180P_0402_50V8J~N
180P_0402_50V8J~N
0.22U_0603_10V7K
0.22U_0603_10V7K
1 VEN GND 8
4.7U_0603_6.3V6M~D
4.7U_0603_6.3V6M~D
1 1 1 1 1 1 2 VIN GND 7
FAN1_POWER 3 6
C431 C428 C430 C426 C427 C429 EN_DFAN1 VO GND
25 EN_DFAN1 4 VSET GND 5
2 2 2 2 2 2 APL5605KI_SOP8
+3VS
40mil JFAN1
1
1
R38 2
10K_0402_5% 3
4 G
5 G
2
MOLEX_53398-0371~N
25 FAN_SPEED1
CONN@
LAYOUT: Place bypass cap near CPU socket
NEAR HT POWER PINS THAT ARE NOT CONNECTED DIRECTLY 2 FAN1
TO DOWNSTREAM HT DEVICE, BUT CONNECTED INTERNALLY
TO OTHER HT POWER PINS C114
A A
PLACE CLOSE TO VLDT0 POWER PINS 1
0.01U_0402_16V7K
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/1/3 Deciphered Date 2009/01/3 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TURION64 HT I/F & FAN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4191P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 14, 2008 Sheet 4 of 39
5 4 3 2 1
A B C D E
Processor DDR2 Memory Interface
VDD_VTT_SUS_CPU IS CONNECTED TO THE VDD_VTT_SUS POWER
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED 9 DDR_B_D[63..0]
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE CPU1C