Text preview for : Sony MBX-178- m620-pvt-mb-0608-1000.pdf part of Sony Sony MBX-178- m620-pvt-mb-0608-1000 Sony Notebook Sony MBX-178- m620-pvt-mb-0608-1000.pdf
Back to : Sony MBX-178- m620-pvt-mb | Home
5 4 3 2 1
Schematics Page Index (Title / Revision / Change Date)
Page Title of Schematics Page Rev. Date Page Title of Schematics Page Rev. Date
01 Schematics Page Index SC 20070316 36 Power Design Diagram
02 Block Diagram 37 Charger (MAX1909)
D
03 Merom(HOST BUS) 1/2 38 DCIN D
04 Merom(HOST BUS) 2/3 39 SYSPWR(+3VALW/+5VALW)
05 Merom(Power/Gnd) 3/3 40 SYSPWR(+1_5VRUN/+1_05VRUN)
06 CLOCK GEN 41 DDR2PWR(+1_8V_SUS/+0_9VRUN)
07 Crestline (HOST) 1/7 42 VHCORE(ISL6262A)
08 Crestline (DMI) 2/7 43 Others power plan
09 Crestline (GRAPHIC) 3/7 44 OVP protection
10 Crestline (DDRII) 4/7 45 GMCH POWER
11 Crestline (POWER,VCC) 5/7 46 HOLE/DB CONNS
12 Crestline (VCC CORE) 6/7 47 Audio Board /Audio Jack
13 Crestline (VSS) 7/7 48 CRT
14 DDRII(SO-DIMM_0) 1/3 49 History (EVT)
C
15 DDRII(SO-DIMM_1) 2/3 50 History (EVT2) C
16 DDRII(Termination) 3/3 51 History (DVT)
17 LVDS 52 History (PVT)
18 ICH8-M( PCI/USB ) 1/5
19 ICH8-M( LPC,IDE,SATA )2/5
20 ICH8-M( GPIO) 3/5
21 ICH8-M( POWER) 4/5
22 ICH8-M( GND) 5/5
23 SATA HDD/CD-ROM
24 EC+KBC(ENE3910C)
25 Flash ROM/XBUS Value M620GM M620GML
26 Mini-PCIE Card
B 27 FAN/HW THERMAL PROTECT B
28 EXPRESS/CAM/OIDE
29 PCI (PCI BUS) / TV-Tuner
30 PCI ( ILINK)
31 PCI (MS-DUO/MDC) NC_
32 PCI (PCMCIA)
33 USB2.0
34 LAN (1/2)
35 LAN (2/2) P. Leader Check by Design by
A 1P-0075503-6010 A
PCB P/N: 1P-0075103-6010 HON HAI PRECISION IND. CO., LTD.
FOXCONN
Title
CPBG - R&D Division
Index Page
Size Document Number Rev
Project Code & Schematics Subject: M620 Main Board Custom M620-L 1.0
Date: Friday, June 08, 2007 Sheet 1 of 52
5 4 3 2 1
5 4 3 2 1
MBX-178 M620 Block Diagram (15.4" Wide Screen)
Debug Only Clock Gen.
D Processor ICS9LPR358YGLFT D
CRT CRT (340MHz)
Merom/Celeron-M P.6 MAXIM CHARGER
P.48 MAX1909
P.3-5
INPUTS OUTPUTS
15.4" 1280x800 *GL960 only FSB DDRII SDRAM
WXGA Panel supports 533MHz 667/800MHz SO-DIMM 1 BT+
DC_IN
P.17 DCBATOUT
533/667 MHz P.14-16
Sub Woofer Audio Board North Bridge 533/667 MHz
10W Amplifier SO-DIMM 2
SYSTEM DC/DC
10 Watt x 1 P.47 P.39
965GM MAX8734A
*GL960 only supports 533MHz
Int. Speaker LVDS INPUTS OUTPUTS
3.0 Watt x 2 P.47 3W Amplifier x 2 EQ GL960
+5VALW
P.7-13 +5VALW_LDO
Int Mic In (Uni) P.47 Mini-Card DCBATOUT
Int Mic In (Omni) P.47 AEC WLAN P.26 +3VALW
+ECVCC
C-Link0 X4 DMI
S/PDIF Out
P.47 Marvell 10/100 NETSWAP SYSTEM DC/DC
NS682403P RJ45
C 88E8039 SC339/OZ811 P.40
C
Line In Jack P.34-35 P.35
P.47 INPUTS OUTPUTS
+1_8V_S3_SUS +1_5VRUN
CXD9872K
Mic In Jack
P.47
Audio Codec South Bridge
DCBATOUT +1_05VRUN
Head Phone Jack HP Amplifier ICH8M PCIE x 3
TPS2231PW SYSTEM DC/DC
P.41
P.47 USB2.0 Express Card 34 Power SW P.28
SC486
P.28
+1_8V_S3_SUS
DCBATOUT
*GL960 only supports ICH8M-B +0_9VSUS
MDC 1.5 HD Audio PATA
RJ11 Slot in ODD
Modem P.28 SATA
P.23
CPU DC/DC
PCI BUS USB2.0 x 8 2.5" SATA ISL6262A
P.18-22 HDD P.23 P.42
Digital INPUTS OUTPUTS
BCAS Mini-PCI Slot
DCBATOUT VHCORE
TV-Tuner
RF IN P.29
USB2.0 Port x 5 P.33,46 SYSTEM DC/DC
LPC
B GMT966 B
P.43
1.3M Camera P.28
TPS2220 PCMCIA Conn. INPUTS OUTPUTS
Power SWP.32 Type II P.32
TI PCI8412 CIR (USB1.1 )P.46
+1_8V_S3_SUS +1_25VRUN
MS_Duo_Pro ENE KB3910
Slot P.31 CardBus
CPU
CardReader Fan EC+KBC OIDE(USB1.1)
SD/MMC Slot i.LINK P.27 SYSTEM DC/DC
P.31 PS/2 x2 Keyboard SC472B
P.24 Controller GMCH core power
i-Link P.29-32
PS/2
P.30
Touch Pad P.45
P.28
XBUS INPUTS OUTPUTS
GPIO 12,13
SMB Channel 2 SMB Channel 1
DCBATOUT +VGFX_CORE
A
Thermal Sensor 1 Thermal Sensor 2 Clear Pure H/W Thermal Shotdown A
Flash BIOS G781-1 G781 Button Lid Switch
8Mbits Battery Conn G709 P.27
Local:Audio Local:NB/DDR Board
P.25 P.37 Remote:CPUP.27 Remote:TV P.27
HON HAI PRECISION IND. CO., LTD.
FOXCONN
Title
CPBG - R&D Division
Block Diagram (All)
Size Document Number Rev
Custom
M620-L 1.0
Date: Friday, June 08, 2007 Sheet 2 of 52
5 4 3 2 1
1 2 3 4 5 6 7 8
1 30MIL TP574
U1A +1_05VRUN
7 H_A#[3..35]
H_A#3 J4 H1
A[3]# ADS# H_ADS# 7
0
ADDR GROUP
H_A#4 L5 E2
A[4]# BNR# H_BNR# 7
A H_A#5 L4 G5 A
A[5]# BPRI# H_BPRI# 7
H_A#6 K5 A[6]#
1
H_A#7 M3 H5
A[7]# DEFER# H_DEFER# 7
H_A#8 N2 F21 R2030
A[8]# DRDY# H_DRDY# 7
H_A#9 J1 E1
A[9]# DBSY# H_DBSY# 7
H_A#10 N3 56_J +1_05VRUN
H_A#11 A[10]#
P5 A[11]# BR0# F1 H_BREQ#0 7 0402
H_A#12
2
P2 A[12]#
CONTROL
H_A#13 L2 D20 H_IERR#
H_A#14 A[13]# IERR#
P4 A[14]# INIT# B3 H_INIT# 19
H_A#15 P1 XDP_TDI R1751 1 150_J 2 0402
H_A#16 A[15]#
R1 A[16]# LOCK# H4 H_LOCK# 7
M1 R1752 39_D 0402
7 H_ADSTB#0 ADSTB[0]# H_CPURST# 7
C1 XDP_TMS 1 2
7 H_REQ#[4..0] RESET# H_RS#[2..0] 7
H_REQ#0 K3 F3 H_RS#0
H_REQ#1 REQ[0]# RS[0]# H_RS#1
H2 REQ[1]# RS[1]# F4
H_REQ#2 K2 G3 H_RS#2
H_REQ#3 REQ[2]# RS[2]#
J3 REQ[3]# TRDY# G2 H_TRDY# 7
H_REQ#4 L1 REQ[4]# XDP_TCK R1754 1 27_F
HIT# G6 H_HIT# 7 2 0402
H_A#17 Y2 E4
A[17]# HITM# H_HITM# 7
H_A#18 U5 R1755 649_F 0402
H_A#19 A[18]# XDP_TRST#
R3 A[19]# BPM[0]# AD4 PVT 1 2
1
ADDR GROUP
H_A#20 W6 AD3
H_A#21 A[20]# BPM[1]#
U4 A[21]# BPM[2]# AD1
H_A#22 Y5 AC4 Debug port not used .
XDP/ITP SIGNALS
H_A#23 A[22]# BPM[3]#
U1 A[23]# PRDY# AC2 resistors close to CPU.
H_A#24 R4 AC1
H_A#25 A[24]# PREQ# XDP_TCK
T5 A[25]# TCK AC5
B H_A#26 T3 AA6 XDP_TDI B
H_A#27 A[26]# TDI
Layout note: W2 A[27]# TDO AB3
H_A#28 W5 AB5 XDP_TMS
no stub on H_STPCLK TP. H_A#29 A[28]# TMS XDP_TRST#
Y4 A[29]# TRST# AB6
H_STPCLK# to be routed in daisy H_A#30 U2 C20 +1_05VRUN
H_A#31 A[30]# DBR#
V4 A[31]#
chain fashion from ICH to LPC slot H_A#32 W3 A[32]#
1
and then to CPU. H_A#33 AA4 THERMAL
H_A#34 A[33]# R1912
AB2 A[34]#
H_A#35 AA3 D21 PROCHOT# 56_J
A[35]# PROCHOT# H_THERMDA 0402
7 H_ADSTB#1 V1 ADSTB[1]# THERMDA A24 H_THERMDA 27
B25 H_THERMDC
THERMDC H_THERMDC 27
2
19 H_A20M# A6 A20M#
ICH
A5 C7 PM_THRMTRIP#
19 H_FERR# FERR# THERMTRIP# PM_THRMTRIP# 8,19
Layout note: 19 H_IGNNE# C4 IGNNE#
no stub on PM_THRMTRIP#
1 2 H_STPCLK#_R D5
19 H_STPCLK# STPCLK# should connect to
H_STPCLK# GP16 CLOSE_JUMP_40X50 C6 H CLK
19 H_INTR LINT0
19 H_NMI B4 LINT1 BCLK[0] A22 CLK_CPU_BCLK 6 ICH8-M and GMCH
19 H_SMI# A3 SMI# BCLK[1] A21 CLK_CPU_BCLK# 6 without T-ing (No stub)
M4 RSVD[01]
PVT N5
T2
RSVD[02]
RSVD[03]
V3 RSVD[04]
B2
RESERVED
RSVD[05]
C3 RSVD[06]
D2 H_THERMDA
RSVD[07]
D22 RSVD[08]
C C
D3 RSVD[09]
1
F6 C1696
RSVD[10] NC_2200P_50V_K_B
0402
2
CPU SOCKET_478P H_THERMDC close to cpu +ECVCC
FOX_PZ4782A-274M-01
1
R1757
+1_05VRUN
47K_J
+3VRUN 0402
1
2
R1758 If PROCHOT# is routed between
RESET#_KBC 24
CPU,IMVP and MCH, pull-up
3
75_J resistor has to be 75 ohm +-5%
1
D
0402
1
R1759 PROCHOT# C1418
2
1 Q44 0.1U_16V_M
8,18,20,23,24,25,26,28,34 PLT_RST#
3
G
2.2K_J Q46A S 2N7002EPT 0402
D
2
0402
2
2
A0205 5 G A0202
S +1_05VRUN
6
3
Q46B 2N7002DW-7-F Q47
D
4
C
1 2 1 B
D 20,24,27,42 OVT_EC# 2 G ICH8M's GPIO12: VIL---> -0.5V ~ 0.8V R1760 E DVT D
S 2.2K_J
2N7002DW-7-F
VIH---> 2.0V ~ 3.3+0.5V 0402 MMBT3904.215
MEROM's PROCHOT#: VIL---> -0.1V ~ 0.3*VCCP
1
2
null
VIH---> 0.7*VCCP ~ VCCP+0.1 PM_THRMTRIP#
HON HAI PRECISION IND. CO., LTD.
FOXCONN
Title
CPBG - R&D Division
Merom (HOST BUS) 1/3
Size Document Number Rev
A3 1.0
M620-L
Date: Friday, June 08, 2007 Sheet 3 of 52
1 2 3 4 5 6 7 8
5 4 3 2 1
D D
7 H_D#[63..0]