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A B C D E
1 1
Boston
LA-2721 Schematics Document
2 2
Intel Dothan / Alviso GM(PM) / DDR-1 / ICH6-M
(nVIDIA NV44MV / ATi M24C)
Rev:1.0
3 3
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title
Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 11:47:55 Sheet 1 of 53
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A B C D E
Compal confidential
File Name : LA-2721 Fan Conn Thermal Sensor Clock Generator
page 38 Intel Dothan CPU ADM1032ARM ICS954226
page 4,5
CRT/TV-OUT
page 4 page 14
page 15
1
H_A#(3..31) FSB H_D#(0..63)
1
400 / 533 Mhz
NV44MV/M24C
VGA Board Intel Alviso DDR-1 333 Mhz
DDR-SO-DIMM X2
page 16
GM( GML,PM) BANK 0, 1, 2, 3page 11,12,13
LCD CONN PCBGA 1257 page 6,7,8,9,10
page 16 Signal Channel DDR-1
Docking AMP & Audio Jack
DMI Audiopage 31 page 32
MARVELL LAN
RJ45 CONN 88E8036 PCI-E BUS USB 2.0 USB conn x 4
2
page 28 88E8053 page 39 2
page 27
IDSEL:PCI_AD18
Intel ICH6-M USB 2.0 BT Conn
page 36
GNT#1 PCI BUS mBGA-609
REQ#1 Audio CKT
IDSEL: PCI_AD20 AC-LINK
IRQG# ALC250-D
GNT#2
IRQH# page 17,18,19,20 page 30
REQ#2
Mini PCI IRQA#
TI Controller
MDC
socket IRQB# PCI7411/6411/4510/1510 page 35
page 29 IRQC# page 23,24 LPC BUS
IRQD# SATA
SATA to PATA
PATA HDD conn
88SA8040
3
1 394 Slot 0 5in1 CardReader page 21 page 21 3
Conn. Slot page 25
page 24 page 26 PATA
CDROM
Connector
page 22
Power On/Off CKT.
page 39
Docking CONN.
SMsC LPC47N217 ENE KB910 *RJ-11 / 45(LED*2)
LPC47N207 *COMPOSITE Video Out
page 35
DC/DC Interface CKT. RTC CKT. *LINE IN / OUT
page 33,34
page 42 page 41 *PS/2
*Print port
Int. KBD *1394
page 36 *USB
Power Circuit DC/DC Power OK CKT. FIR *DC JACK
Touch Pad
4 page 44~50 page 41
page 38 CONN. page 36 BIOS 4
page 37 page 39
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title
Block Diagrams
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 11:47:56 Sheet 2 of 53
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SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails
S0 (Full ON) HIGH HIGH HIGH HIGH ON ON ON ON
Power Plane Description S1 S3 S5 S1 (Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
1 B+ AC or battery power rail for power circuit. N/A N/A N/A 1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+CPU_CORE Core voltage for CPU ON OFF OFF
+1.05VS 1.05V switched power rail ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+DDRVTT 1.25V switched power rail for DDR terminator ON OFF OFF
+1.5VALW 1.5V always on power rail ON ON ON*
+1.5VS 1.5V switched power rail ON OFF OFF Board ID / SKU ID Table for AD channel
+1.8VS 1.8V switched power rail ON OFF OFF Vcc 3.3V +/- 5%
+DDRVCC 2.5V power rail for DDR ON ON OFF Ra/Rc/Re 100K +/- 1%
+2.5VS 2.5V switched power rail ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+3VALW 3.3V always on power rail ON ON ON* 0 0 0 V 0 V 0.100 V
+3V 3.3V power rail ON ON OFF 1 8.2K +/- 1% 0.216 V 0.250 V 0.289 V
+3VS 3.3V switched power rail ON OFF OFF 2 18K +/- 1% 0.436 V 0.503 V 0.538 V
+5VALW 5V always on power rail ON ON ON* 3 33K +/- 1% 0.712 V 0.819 V 0.875 V
+5VS 5V switched power rail ON OFF OFF 4 56K +/- 1% 1.036 V 1.185 V 1.264 V
+5VCD 5V switched power rail for CDROM ON OFF OFF 5 100K +/- 1% 1.453 V 1.650 V 1.759 V
2 2
+12VALW 12V always on power rail ON ON ON* 6 200K +/- 1% 1.935 V 2.200 V 2.341 V
+RTCVCC RTC power ON ON ON 7 NC 2.500 V 3.300 V 3.300 V
+5VAMP 5V switched power rail for amplifier ON OFF OFF
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
BOARD ID Table
Board ID PCB Revision
External PCI Devices 0 0.1
Device IDSEL# REQ#/GNT# Interrupts 1 0.2
C ardBus AD20 2 PIRQA/PIRQB/PIRQC/PIRQD 2 0.3
1394 AD20 2 PIRQA/PIRQB/PIRQC/PIRQD 3 1.0
Card reader AD20 2 PIRQA/PIRQB/PIRQC/PIRQD 4
Mini-PCI AD18 1 PIRQG/PIRQH 5
6
7
3 3
SKU ID Table
EC SM Bus1 address EC SM Bus2 address SKU_ID1 1 3 7
Button Button Button
Device Address Device Address
SKU_ID 0 1 2 3 4 5 6
0 10 1 8 0
Smart Battery 0001 011X b ADM1032 1001 110X b
1 10C 3 C 2
EEPROM(24C16/02) 1010 000X b 2'nd Battery 1001 011X b
(24C04) 2 10G 5 9 4
1011 000Xb Docking 1010 000X b
3 10GC 7 D 6
4
5
6
ICH6M SM Bus address 7
Device Address
4 4
Clock Generator 1101 001Xb
( ICS 952623)
DDR DIMM0 1001 000Xb
DDR DIMM1 1001 001Xb Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title
Notes
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 11:47:55 Sheet 3 of 53
A B C D E
5 4 3 2 1
JP23A
H_A#[3..31] H_A#3 P4 A19 H_D#0 H_D#[0..63]
<6> H_A#[3..31] H_A#4
H_A#5
U4
A3#
A4#
Dothan D0#
D1# A25 H_D#1
H_D#2
H_D#[0..63] <6>
+3VS
V3 A5# D2# A22
H_A#6 R3 B21 H_D#3
H_A#7 A6# D3# H_D#4
V2 A7# D4# A24
H_A#8 W1 B26 H_D#5
H_A#9 A8# D5# H_D#6
T4 A9# D6# A21
H_A#10 W2 B20 H_D#7 1
A10# D7#
1
H_A#11 Y4 C20 H_D#8
H_A#12 A11# D8# H_D#9 C552 R490
Y1 A12# D9# B24
D H_A#13 U1 D24 H_D#10 0.1U_0402_16V4Z @ 10K_0402_5% D
H_A#14 A13# D10# H_D#11 2
AA3 A14# D11# E24 1
H_A#15 Y3 C26 H_D#12 C553
2
H_A#16 A15# D12# H_D#13 U37
AA2 A16# D13# B23
H_A#17 AF4 E23 H_D#14 2200P_0402_50V7K THERMDA 2 1
H_A#18 A17# D14# H_D#15 2 D+ VDD1
AC4 A18# D15# C25
H_A#19 AC7 H23 H_D#16 THERMDC 3 6
H_A#20 A19# D16# H_D#17 D- ALERT#
AC3 A20# D17# G25
H_A#21 AD3 L23 H_D#18 <30,35,40> EC_SMB_CK2 8 4
H_A#22 A21# D18# H_D#19 SCLK THERM#
AE4 A22# D19# M26
H_A#23 AD2 H24 H_D#20 <30,35,40> EC_SMB_DA2 7 5
H_A#24 A23# D20# H_D#21 SDATA GND
AB4 A24# D21# F25
H_A#25 AC6 ADDR GROUP DATA GROUP G24 H_D#22
H_A#26 A25# D22# H_D#23
AD5 A26# D23# J23 ADM1032ARM_RM8
H_A#27 AE2 M23 H_D#24
H_A#28 A27# D24# H_D#25
AD6 A28# D25# J25
H_A#29 AF3 L26 H_D#26 +1.05VS
H_A#30 A29# D26# H_D#27
AE1 A30# D27# N24
H_A#31 AF1 M25 H_D#28
H_REQ#[0..4] A31# D28# H_D#29
<6> H_REQ#[0..4] D29# H26
H_REQ#0 R2 N25 H_D#30
H_REQ#1 REQ0# D30# H_D#31 ITP_TDI R73 150_0402_5%
P3 REQ1# D31# K25 2 1
H_REQ#2 T2 Y26 H_D#32
H_REQ#3 REQ2# D32# H_D#33 ITP_TDO R74
P1 REQ3# D33# AA24 2 1 @ 54.9_0402_1%
H_REQ#4 T1 T25 H_D#34
REQ4# D34# H_D#35 H_CPURST# R72
D35# U23 2 1 @ 54.9_0402_1%
U3 V23 H_D#36
<6> H_ADSTB#0 ADSTB0# D36# H_D#37 ITP_TMS R71 39.2_0603_1%
<6> H_ADSTB#1 AE5 ADSTB1# D37# R24 2 1
R26 H_D#38
C
D38# H_D#39 PRO_CHOT# R77 56_0402_5% C
D39# R23 2 1
A16 AA23 H_D#40
ITP_CLK0 D40# H_D#41 H_PWRGOOD R67 200_0402_5%
A15 ITP_CLK1 D41# U26 2 1
V24 H_D#42
D42# H_D#43 H_IERR# R69 56_0402_5%
<14> CLK_CPU_BCLK B15 BCLK0 D43# U25 2 1
B14 HOST CLK V26 H_D#44
<14> CLK_CPU_BCLK# BCLK1 D44#
Y23 H_D#45
D45# H_D#46
D46# AA26
Y25 H_D#47 +3VS
D47# H_D#48
<6> H_ADS# N2 ADS# D48# AB25
L1 AC23 H_D#49
<6> H_BNR# BNR# D49# H_D#50 ITP_DBRRESET# R70 150_0402_5%
<6> H_BPRI# J3 BPRI# D50# AB24 2 1
N4 AC20 H_D#51
<6> H_BR0# BR0# D51# H_D#52
<6> H_DEFER# L4 DEFER# D52# AC22
H2 AC25 H_D#53
<6> H_DRDY# DRDY# D53# H_D#54
<6> H_HIT# K3 HIT# D54# AD23
K4 CONTROL GROUP AE22 H_D#55 ITP_TRST# R75 2 1 680_0402_5%
<6> H_HITM# H_IERR# HITM# D55# H_D#56
A4 IERR# D56# AF23
J2 AD24 H_D#57 ITP_TCK R76 2 1 27.4_0402_1%
<6> H_LOCK# H_CPURST# LOCK# D57# H_D#58
<6> H_CPURST# B11 RESET# D58# AF20
AE21 H_D#59 TEST1 R68 2 1 @ 1K_0402_5%
D59# H_D#60
D60# AD21
H_RS#[0..2] H_RS#0 H1 AF25 H_D#61 TEST2 R65 2 1 @ 1K_0402_5%
<6> H_RS#[0..2] RS0# D61#
H_RS#1 K1 AF22 H_D#62
H_RS#2 RS1# D62# H_D#63
L2 RS2# D63# AF26
<6> H_TRDY# M3 TRDY#
DINV0# D25 H_DINV#0 <6>
DINV1# J26 H_DINV#1 <6>
B B
C8 BPM0# DINV2# T24 H_DINV#2 <6>
B8 BPM1# DINV3# AD20 H_DINV#3 <6>
A9 BPM2#
C9 H_FERR# 2 1
BPM3# Reserve for debug C677 220P_0402_50V8J
DSTBN0# C23 H_DSTBN#0 <6>
ITP_DBRRESET# A7 K24 C677 close to South Bridge (U13)
DBR# DSTBN1# H_DSTBN#1 <6>
<6> H_DBSY# M2 DBSY# DSTBN2# W25 H_DSTBN#2 <6>
<18> H_DPSLP# B7 DPSLP# DSTBN3# AE24 H_DSTBN#3 <6>
<18> H_DPRSTP# G1 DPRSTP# DSTBP0# C22 H_DSTBP#0 <6>
<6> H_DPWR# C19 DPWR# DSTBP1# L24 H_DSTBP#1 <6>
A10 MISC W24 H_SMI# 2 1
PRDY# DSTBP2# H_DSTBP#2 <6> C678 @ 180P_0402_50V8J
B10 PREQ# DSTBP3# AE25 H_DSTBP#3 <6>
PRO_CHOT# B17 H_INIT# 2 1
PROCHOT# C679 @ 180P_0402_50V8J
H_PWRGOOD E4 PWRGOOD NMI 2 1
<18> H_PWRGOOD
H_CPUSLP# A6 SLP# C675 680P_0402_50V8J
<6,18> H_CPUSLP#
ITP_TCK A13 TCK H_A20M# 2 1
ITP_TDI C12 TDI C2 H_A20M# C681 @ 180P_0402_50V8J
A20M# H_A20M# <18>
ITP_TDO A12 TDO D3 H_FERR# H_INTR 2 1
FERR# H_FERR# <18>
TEST1 C5 TYCO_1612365-1_Dothan A3 H_IGNNE# C682 @ 180P_0402_50V8J
TEST1 IGNNE# H_IGNNE# <18>
TEST2 F23 TEST2 B5 H_INIT# H_IGNNE# 2 1
INIT# H_INIT# <18>
ITP_TMS C11 TMS D1 H_INTR C683 @ 180P_0402_50V8J
LINT0 H_INTR <18>
ITP_TRST# B13 TRST# D4 NMI R614 2 1 0_0402_5% H_STPCLK# 2 1
LINT1 H_NMI <18>
LEGACY CPU C684 @ 180P_0402_50V8J
THERMAL H_PWRGOOD 2 1
THERMDA B18 C6 H_STPCLK# C685 @ 180P_0402_50V8J
THERMDC A18
THERMDA DIODE STPCLK#
B4 H_SMI#
H_STPCLK# <18> Reserve for debug H_CPUSLP# 2 1
THERMDC SMI# H_SMI# <18> C675, C678, C679, C681 ~ C686
C17 C686 @ 180P_0402_50V8J
<6,18> H_THERMTRIP# THERMTRIP# close to CPU (JP13)
A A
THERMDA & THERMDC Trace / Space = 10 / 10 mil
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title
Dothan Processor in mFCPGA479
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D