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A B C D E
1 1
2
Compal Confidential 2
ICW50 Schematics Document
AMD Turion/Sempron + Nvidia MCP67-MV
2007 / 04 / 20 Rev:1.0 FOR Pre-MP
3 3
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom ICW50 / ICY70 LA-3581P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 20, 2007 Sheet 1 of 42
A B C D E
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Compal confidential
Project Code: ICW50 DDRII 533/667/800 DDRII-SO-DIMM X2
Thermal Sensor AMD Turion/Sempron CPU
page 08,09
File Name : LA-3581P ADM1032ARM Socket S1 638P
page 4,5,6,7 Dual Channel
page 6
D HT LINK D
200-800MHz
DVI-D Conn. LCD Conn. CRT & TV-out
page 20 page 20 page 19
Nvidia USB conn x4 Bluetooth CMOS
LVDS Conn page Camera
MCP67-MV page 25,26 29 page 20
DVI LVDS 836 BGA USB 2.0 BUS
HD Audio 3.3V 24.576MHz/48Mhz
PCI-Express
IDE BUS 3.3V ATA-100
MXM II VGA/B SATA BUS
page 18 CDROM MDC 1.5 HDA Codec
Conn. 21 Conn 29 ALC268
C
page page page 31 C
PCI-Express port 1
PCI BUS S-ATA HDD
IDSEL:AD20
3.3V 33 MHz Conn. page 21
New Card MINI Card x2 PHY(GbE) (PIRQE#, Audio AMP
page 10,11,12,13,14,15,16,17
Socket WLAN, TV-Tuner RTL8211B GNT#0,
REQ#0) page 32
page 22
Card Reader
RICOH R5C833 Phone Jack x3
RJ45 page 23 LPC BUS page 32
page 22
1394 6 in 1
B Conn. socket B
page 23 page 24 ENE KB926
page 27,28
Power On/Off CKT / LID switch / Power OK CKT
page 30
Touch Pad Int.KBD
page 29 page 29
DC/DC Interface CKT. CIR/LED RTC CKT.
page 33 page 29 page 16
EC I/O Buffer BIOS
page 29 page 29
Power Circuit DC/DC
page 35~41
CIR
page 30
A A
Security Classification Compal Secret Data
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
BLOCK DIAGRAM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom ICW50 / ICY70 LA-3581P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 20, 2007 Sheet 2 of 42
5 4 3 2 1
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SIGNAL
STATE SLP_S1# SLP_S3# SLP_S5# +VALW +V +VS Clock
Voltage Rails
Full ON HIGH HIGH HIGH ON ON ON ON
S1(Power On Suspend) LOW HIGH HIGH ON ON ON LOW
Power Plane Description S1 S3 S5
VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH ON ON OFF OFF
D D
B+ AC or battery power rail for power circuit. N/A N/A N/A
S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF
+CPU_CORE Core voltage for CPU ON OFF OFF
+0.9V 0.9V switched power rail for DDR terminator ON ON OFF S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF
+1.2VALW 1.2V always on power rail ON ON ON*
+1.2VS 1.2V switched power rail ON OFF OFF Board ID / SKU ID Table for AD channel
+1.2V_HT 1.2V switched power rail ON OFF OFF Vcc 3.3V +/- 5%
+1.8V 1.8V power rail for DDR ON ON OFF Ra/Rc/Re 100K +/- 5%
+1.8VS 1.8V switched power rail ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+2.5VS 2.5V switched power rail ON OFF OFF 0 0 0 V 0 V 0 V
+3VALW/+3V/+3VAUX 3.3V always on power rail ON ON ON* 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+3VS 3.3V switched power rail ON OFF OFF 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+5VALW 5V always on power rail ON ON ON* 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+5VS 5V switched power rail ON OFF OFF 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+VSB VSB always on power rail ON ON ON* 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
C
+RTCVCC RTC power ON ON ON 6 200K +/- 5% 1.935 V 2.200 V 2.341 V C
7 NC 2.500 V 3.300 V 3.300 V
BOARD ID Table BTO Option Table
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
External PCI Devices Board ID PCB Revision BTO Item BOM Structure
Device IDSEL# REQ#/GNT# Interrupts
0 UMA (0V) DIP CAP & RTC 45@
1394 AD20 0 PIRQE
1 DISCRETE (3.3V) UMA UMA@
2 VGA VGA@
3 UMA & TV-OUT UMA&TV@
4 2 SATA HDD SATA2@
5 CAMERA CMOS@
6 BLUETOOTH BT@
7 MINI CARD 1(TV) MINI1@
B MINI CARD 2(WLAN) MINI2@ B
NEW CARD EXPRESS@
EC SM Bus1 address EC SM Bus2 address SKU ID Table TV-OUT TV@
DVI DVI@
Device Address Device Address SKU ID SKU
1394 1394@
Smart Battery 0001 011X b ADM1032 1001 100X b 0 B - PHASE
CARD READER 5IN1@
1 C - PHASE
HT Debug Port HT@
2
3
4
5
MCP67 SM Bus address 6
7
Device Address
DDR DIMM0 1001 000Xb
DDR DIMM2 1001 001Xb
A A
Security Classification Compal Secret Data
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
TABLE OF CONTENTS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom ICW50 / ICY70 LA-3581P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 20, 2007 Sheet 3 of 42
5 4 3 2 1
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PROCESSOR HYPERTRANSPORT INTERFACE
VLDT_Ax AND VLDT_Bx ARE CONNECTED TO THE LDT_RUN POWER
D D
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE
+1.2V_HT
FAN Conn
JP22A
D4 VLDT_A3 VLDT_B3 AE5 1 2 C533
D3 AE4 4.7U_0805_10V4Z
VLDT_A2 VLDT_B2
D2 VLDT_A1 VLDT_B1 AE3
D1 AE2 +5VS
VLDT_A0 VLDT_B0
1
H_CADIP15 N5 T4 H_CADOP15 D20
(10) H_CADIP15 L0_CADIN_H15 L0_CADOUT_H15 H_CADOP15 (10)
H_CADIN15 P5 T3 H_CADON15 1SS355_SOD323-2
(10) H_CADIN15 L0_CADIN_L15 L0_CADOUT_L15 H_CADON15 (10)
H_CADIP14 M3 V5 H_CADOP14 W=40mils
(10) H_CADIP14 L0_CADIN_H14 L0_CADOUT_H14 H_CADOP14 (10)
H_CADIN14 M4 U5 H_CADON14
(10) H_CADIN14 L0_CADIN_L14 L0_CADOUT_L14 H_CADON14 (10) +VCC_FAN1
H_CADIP13 L5 V4 H_CADOP13
(10) H_CADIP13 H_CADOP13 (10)
2
H_CADIN13 L0_CADIN_H13 L0_CADOUT_H13 H_CADON13
(10) H_CADIN13 M5 L0_CADIN_L13 L0_CADOUT_L13 V3 H_CADON13 (10)
H_CADIP12 K3 Y5 H_CADOP12 FAN1 1 2
(10) H_CADIP12 L0_CADIN_H12 L0_CADOUT_H12 H_CADOP12 (10) +3VS
H_CADIN12 K4 W5 H_CADON12 C510 10U_0805_10V4Z
(10) H_CADIN12 L0_CADIN_L12 L0_CADOUT_L12 H_CADON12 (10)
1
H_CADIP11 H3 AB5 H_CADOP11 D21
(10) H_CADIP11 L0_CADIN_H11 L0_CADOUT_H11 H_CADOP11 (10)
H_CADIN11 H4 AA5 H_CADON11 BAS16_SOT23-3
(10) H_CADIN11 L0_CADIN_L11 L0_CADOUT_L11 H_CADON11 (10)
1
H_CADIP10 G5 AB4 H_CADOP10 1 2
(10) H_CADIP10 L0_CADIN_H10 L0_CADOUT_H10 H_CADOP10 (10)
H_CADIN10 H5 AB3 H_CADON10 R88 C509 1000P_0402_50V7K
(10) H_CADIN10 L0_CADIN_L10 L0_CADOUT_L10 H_CADON10 (10)
H_CADIP9 F3 AD5 H_CADOP9 10K_0402_5% Update Footprint
(10) H_CADIP9 H_CADOP9 (10)
2
H_CADIN9 L0_CADIN_H9 L0_CADOUT_H9 H_CADON9 JP16
(10) H_CADIN9 F4 L0_CADIN_L9 L0_CADOUT_L9 AC5 H_CADON9 (10)
H_CADIP8 E5 AD4 H_CADOP8
(10) H_CADIP8 H_CADOP8 (10)
2
H_CADIN8 L0_CADIN_H8 L0_CADOUT_H8 H_CADON8 1
(10) H_CADIN8 F5 L0_CADIN_L8 L0_CADOUT_L8 AD3 H_CADON8 (10) (27,28) FAN_SPEED1 2
C H_CADIP7 N3 T1 H_CADOP7 C
(10) H_CADIP7 L0_CADIN_H7 L0_CADOUT_H7 H_CADOP7 (10) 3
H_CADIN7 N2 R1 H_CADON7
(10) H_CADIN7 L0_CADIN_L7 L0_CADOUT_L7 H_CADON7 (10)
H_CADIP6 L1 U2 H_CADOP6 1 ACES_85205-03001
HTT Interface
(10) H_CADIP6 L0_CADIN_H6 L0_CADOUT_H6 H_CADOP6 (10)
H_CADIN6 M1 U3 H_CADON6
(10) H_CADIN6 L0_CADIN_L6 L0_CADOUT_L6 H_CADON6 (10)
H_CADIP5 L3 V1 H_CADOP5 C52
(10) H_CADIP5 L0_CADIN_H5 L0_CADOUT_H5 H_CADOP5 (10)
H_CADIN5 L2 U1 H_CADON5 1000P_0402_50V7K
(10) H_CADIN5 L0_CADIN_L5 L0_CADOUT_L5 H_CADON5 (10) 2
H_CADIP4 J1 W2 H_CADOP4
(10) H_CADIP4 L0_CADIN_H4 L0_CADOUT_H4 H_CADOP4 (10)
H_CADIN4 K1 W3 H_CADON4
(10) H_CADIN4 L0_CADIN_L4 L0_CADOUT_L4 H_CADON4 (10)
H_CADIP3 G1 AA2 H_CADOP3
(10) H_CADIP3 L0_CADIN_H3 L0_CADOUT_H3 H_CADOP3 (10)
H_CADIN3 H1 AA3 H_CADON3
(10) H_CADIN3 L0_CADIN_L3 L0_CADOUT_L3 H_CADON3 (10)
H_CADIP2 G3 AB1 H_CADOP2
(10) H_CADIP2 L0_CADIN_H2 L0_CADOUT_H2 H_CADOP2 (10)
H_CADIN2 G2 AA1 H_CADON2
(10) H_CADIN2 L0_CADIN_L2 L0_CADOUT_L2 H_CADON2 (10)
H_CADIP1 E1 AC2 H_CADOP1
(10) H_CADIP1 L0_CADIN_H1 L0_CADOUT_H1 H_CADOP1 (10)
H_CADIN1 F1 AC3 H_CADON1 U11
(10) H_CADIN1 L0_CADIN_L1 L0_CADOUT_L1 H_CADON1 (10)
H_CADIP0 E3 AD1 H_CADOP0 1 8
(10) H_CADIP0 L0_CADIN_H0 L0_CADOUT_H0 H_CADOP0 (10) VEN GND
H_CADIN0 E2 AC1 H_CADON0 +5VS 2 7
(10) H_CADIN0 L0_CADIN_L0 L0_CADOUT_L0 H_CADON0 (10) VIN GND
+VCC_FAN1 3 VO GND 6
H_CLKIP1 J5 Y4 H_CLKOP1 EN_DFAN1 4 5
(10) H_CLKIP1 L0_CLKIN_H1 L0_CLKOUT_H1 H_CLKOP1 (10) (27,28) EN_DFAN1 VSET GND
H_CLKIN1 K5 Y3 H_CLKON1 1
(10) H_CLKIN1 L0_CLKIN_L1 L0_CLKOUT_L1 H_CLKON1 (10)
H_CLKIP0 J3 Y1 H_CLKOP0 G993P1UF_SOP8
(10) H_CLKIP0 L0_CLKIN_H0 L0_CLKOUT_H0 H_CLKOP0 (10)
+1.2V_HT H_CLKIN0 J2 W1 H_CLKON0 C310
(10) H_CLKIN0 L0_CLKIN_L0 L0_CLKOUT_L0 H_CLKON0 (10)
10U_0805_10V4Z
2
R143
1 2 51_0402_1% H_CTLIP1 P3 T5
R142 H_CTLIN1 L0_CTLIN_H1 L0_CTLOUT_H1
1 2 51_0402_1% P4 L0_CTLIN_L1 L0_CTLOUT_L1 R5
H_CTLIP0 N1 R2 H_CTLOP0
(10) H_CTLIP0
(10) H_CTLIN0
H_CTLIN0 P1
L0_CTLIN_H0
L0_CTLIN_L0
L0_CTLOUT_H0
L0_CTLOUT_L0 R3 H_CTLON0
H_CTLOP0 (10)
H_CTLON0 (10) FAN1 Conn
FOX_PZ63823-284S-41F
B Athlon 64 S1 B
Processor Socket
+1.2V_HT C541 C536 C539
4.7U_0805_10V4Z 0.22U_0402_10V4Z 180P_0402_50V8J
1 1 1 1 1 1
2 2 2 2 2 2
C542 C540 C538
4.7U_0805_10V4Z 0.22U_0402_10V4Z 180P_0402_50V8J
LAYOUT: Place bypass cap on topside of board
NEAR HT POWER PINS THAT ARE NOT CONNECTED DIRECTLY
TO DOWNSTREAM HT DEVICE, BUT CONNECTED INTERNALLY
TO OTHER HT POWER PINS
PLACE CLOSE TO VLDT0 POWER PINS
A A
Security Classification Compal Secret Data
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
AMD CPU HT I/F
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom ICW50 / ICY70 LA-3581P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 20, 2007 Sheet 4 of 42
5 4 3 2 1
A B C D E
Processor DDR2 Memory Interface
VDD_VTT_SUS_CPU IS CONNECTED TO THE VDD_VTT_SUS POWER
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED JP22C
(9) DDR_B_D[63..0]
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE DDR_A_D[63..0] (8)
DDR_B_D63 AD11 AA12 DDR_A_D63
DDR_B_D62 MB_DATA63 MA_DATA63 DDR_A_D62
AF11 MB_DATA62 MA_DATA62 AB12
DDR_B_D61 AF14 AA14 DDR_A_D61
DDR_B_D60 MB_DATA61 MA_DATA61 DDR_A_D60
AE14 MB_DATA60 MA_DATA60 AB14
DDR_B_D59 Y11 W11 DDR_A_D59
DDR_B_D58 MB_DATA59 MA_DATA59 DDR_A_D58
AB11 MB_DATA58 MA_DATA58 Y12
DDR_B_D57 AC12 AD13 DDR_A_D57
+1.8V DDR_B_D56 MB_DATA57 MA_DATA57 DDR_A_D56
AF13 MB_DATA56 MA_DATA56 AB13
+0.9VREF_CPU DDR_B_D55 AF15 AD15 DDR_A_D55
4 JP22B +0.9V DDR_B_D54 MB_DATA55 MA_DATA55 DDR_A_D54 4
AF16 MB_DATA54 MA_DATA54 AB15
DDR_B_D53 AC18 AB17 DDR_A_D53
MB_DATA53 MA_DATA53
1
W17 D10 DDR_B_D52 AF19 Y17 DDR_A_D52
R386 M_VREF VTT1 DDR_B_D51 MB_DATA52 MA_DATA52 DDR_A_D51
VTT2 C10 AD14 MB_DATA51 MA_DATA51 Y14
39.2_0402_1%~D PAD TP2 VTT_SENSE Y10 B10 DDR_B_D50 AC14 W14 DDR_A_D50
VTT_SENSE VTT3 DDR_B_D49 MB_DATA50 MA_DATA50 DDR_A_D49
VTT4 AD10