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EL5 Block Diagram :
VRM 11.1 Channel A DDR3 DIMM0 DDR3 DIMM1
D CPU Core Lynnfield/ 8GB per channel CN14 P.16 CN13 P.16
D
ISL6334 Clarkdale Dual channel DDR3
P.39 800/1066/1333MHz 1.5V
Processor Channel B DDR3 DIMM0 DDR3 DIMM1
8GB per channel CN18 CN17
MXM CNN (Graphics) 64-bit/45nm P.17 P.17
Mobile PCI-E Module PCIE 2.0 x16(PEG) LGA1156
TYPE-A(or B) (285 pin) (37.5x37.5mm)
TMDS
(Max 45W) P.18 VTT_CPU
(95W)
TMDS LEVEL SHIFT P.9~P.15 P.39
(Lynnfield
HDMI CN option) P.20
LVDS UMA PECI DMI
LCD Panel CNN P.20 FDI
LEVEL SHIFT (*1) x4
Samsung LTM230TT01 (Clarkdale
TMDS option) P.20
(23'' 16:10)
(34.5W) P.18 Inverter CONN
P.18
TMDS
LVDS (Clarkdale option)
C
Ibex Peak 25MHz C
14.318MHz LVDS Transmitter
SDVOB
Chrontel CH7308 (No MXM option) PCH GB LAN
LQFP64 PCI-E x1 PCIE 5 Intel 82578DC RJ45 CNN
ACIN P.19 P.33
FCBGA951 P.33
SATA HDD(3.5") SATA 0 SATA II
P.30 (27x27mm)
P3P3V_DUAL P.38
P5V_STBY SATA ODD SATA 1 USB 3 CARD READER CNN
(6.5W) CLOCK Generator
DDRIII Power P.40 P.30 (Realtek RTS5159-GR) 14.318MHz
CK505
VCC5 eSATA SATA 2
P.34
P1P05V_PCH P.41 P.30
P.08
VCC3 P1P8V(SFR) P.41 2nd SATA HDD SATA 3
PCIE 2 Mini PCIE1 RTC Battery P.25
(2.5" x SSD) P.30 USB 2.0 USB 10 WLAN CNN
P12V 802.11 b/g/n 3G/WiMax
P.35 Fan CNN
TOUCH Screen USB 8 USB 2.0 P.36
VCC_CORE/VTT_CPU P.34
B VREG_12V PCIE 3
Mini PCIE2 Reset Circuit B
P.39 CAREMA with USB 4 P.21~P.29 USB 12
Array MIC P.18
TV Tuner CARD CNN
BLUE TOOTH USB 2 P.35 Brightness Control
P.34 32.768KHz
LPC
SIDE USB x2 USB 1,5 B-CAS CNN LED Indicator
P.34 P.35
REAR USB x4 USB 0,9,11,13 EC/KBC MAIN SW CNN
32.768KHz
P.34 ITE8512
LQFP128 P.36
AUDIO AMP AUDIO CODEC Azailia
MAX9736BETJ+ ALC888S-VC2
QFN32 LQFP48
P.32 5.1 Channel P.31
FAN CTRL 1Mb SPI IR IR System Ambient
(CPU/MXM) FLASH RECEIVER Blaster Light Sensor
P.36 ROM P.29 P.37 P.37
INT SPK Head Phone & 5.1 Channel
Line Line Line Line
A CNN (3) MIC IN CONN In Out(1) Out(1) Out(1) A
P.32
P.31 P.31
Quanta Computer Inc(QCI).
211, Wen Hwa 2nd Rd., Kuei Shan,
Tao Yuan 33377, Taiwan
Tel : +886-3-327-2345
Confidential
FDI - Used only for the Clarkdale processor. Title
BLOCK DIAGRAM
Size Document Number Rev
C EL5 A02
Date: Thursday, March 04, 2010 Sheet 1 of 43
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Net name Description : Board Stack up Description 02
Voltage Rails PCB Layers
P5V_STBY 5.0V always on power rail by LATCH or ACIN Layer 1 Component Side, Microstrip signal Layer
D P3P3V_STBY 3.3V always on power rail by LATCH or ACIN Layer 2 Power Plane D
P1P5V 1.5V switched power rail by SUSB#/PM_SLP_S3# Layer 3 Normal Signal / Ground 1 Plane
P2P5V 2.5V switched power rail by SUSB#/PM_SLP_S3# Layer 4 Stripline Layer(High Speed)
VCC3 3.3V switched power rail by SUSB#/PM_SLP_S3#
VCC5 5.0V switched power rail by SUSB#/PM_SLP_S3# Layer 5 Ground Plane
P12V 12V switched power rail by SUSB#/PM_SLP_S3# Layer 6 Solder Side,Microstrip signal Layer
VREG_12V 12V switched power rail for CPU Vcore
VCCP Core Voltage for CPU
P1V1_CPU_VTT 1.1V power rail for AGTL+ termination & PCH DMI I/F Layers : 6 Depth 1.2mm Impence 55 ohms +/- 10%
by SUSB#/PM_SLP_S3# Single End Impedance Differential Impedance for Microstrip Differential Impedance for Stripline
Host Clock 55 ohm +/- 15% 95 ohm +/- 15% 100 ohm +/- 15%
P1P05V_PCH 1.05V power rail for PCH Core;PCH I/O;DMI;PCIE;SATA SRC Clock 55 ohm +/- 15% 95 ohm +/- 15% 100 ohm +/- 15%
by SUSB#/PM_SLP_S3# Host Bus 55 ohm +/- 15%
DDR3 CLK 42 ohm +/- 15% 70 ohm +/- 20% 70 ohm +/- 20%
DDR3 Strobe 55 ohm +/- 15% 85 ohm +/- 20%
P1P8_SFR 1.8V power rail for CPU PLL & PCH NAND I/F by DDR3 Bus 55 ohm +/- 15%
C
SUSC#/PM_SLP_S4# DMI Bus 55 ohm +/- 15% 95 ohm +/- 15% 100 ohm +/- 15% C
P1P5V_SUS 1.5V power rail for DDRIII by SUSC#/PM_SLP_S4# PCIE Bus 55 ohm +/- 15% 95 ohm +/- 15% 100 ohm +/- 15%
0.75VDDT_DDR3 0.75V DDRIII Termination Voltage by SUSB#/PM_SLP_S3# SATA 95 ohm +/- 15% 100 ohm +/- 15%
SDVO 55 ohm +/- 15% 95 ohm +/- 15% 100 ohm +/- 15%
LVDS 100 ohm +/- 15% 100 ohm +/- 15%
USB 90 ohm +/- 15% 90 ohm +/- 15%
Part Naming Conventions Lan 50 ohm +/- 15%
C = Capacitor
CN = Connector
D = Diode
F
L
=
=
Fuse
Inductor
For no M3 support with Intel LAN:
Q = Transistor
R = Resistor