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A B C D E
ZZZ
PCB
Part Number = DAZ0J200100
1 1
Compal Confidential
2 2
K73 Schematics Document
AMD APU Zacate-FT1 + FCH Hudson-M1 + GPU Seymour XT-M2
3
2010-02-22 3
REV:0.22
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/06/30 Deciphered Date 2012/06/30 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P01-Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.22
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA7323P
Date: Friday, March 04, 2011 Sheet 1 of 47
A B C D E
A B C D E
Compal confidential
LA-7323P
1 1
Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM X2
AMD Brazos APU Single Channel BANK 0, 1, 2, 3 page 8,9
1.5V DDRIII
FT1
LVDS Conn. HDMI Conn. CRT Conn. BGA 413-Ball
page 10 page 11 page 10
19mm x 19mm Port 0
SATA HDD Conn.
page 28
page 5,6,7
Port 1
LVDS(DIS) HDMI(DIS) CRT(DIS) UMI Gen.1 x4 SATA ODD Conn.
page 28
2.5GT/s per lane
SATA Port 2
SATA HDD Conn.
page 28
2
AMD Seymour-XT 2
PCI-E GPP x4 GEN2 2Channel Speaker
page 17 ~ 23 Hudson M1
page 25
BGA 605-Ball
23mm x 23mm AZALIA Audio Codec Audio Jacks X 2
ALC269 (Headphone,page 25
MIC)
VRAM 64*16/ page 25
VRAM 128*16 PCI-E 2.0 x1
USB2.0 DMIC
page 12 ~ 16 page 10
DDR3*4
page 22
Port 1 Port 0
Port 0
LPC BUS USB Conn.
page 31
Port 1
Mini Card-1 WLAN LAN(GbE) USB Conn.
page 31
3
(With Bluetooth) RTL8111E ENE KB930 3
Port 5
USB Conn.
page 27 page 24 page 29
(LS-7323P) page 25
Port 2
Camera
page 10
RJ45 Int.KBD
Port 3
page 24 page 30 Mini Card WLAN
RTC CKT (With Bluetooth)27
page
Touch Pad SPI ROM
page 12 Sub-Board page 30 page 29 Port 4
Card Reader
RTS5137 page 26
Power On/Off CKT LS-7324P Thermal Sensor
HDD/B
page 33 page 28 page 18 Port 6 USB Conn.
(LS-7323P) page 25
4
DC/DC CKT LS-7325P 4
PWR/B
page 23,34 page 33
LS-7323P Security Classification Compal Secret Data Compal Electronics, Inc.
Power Circuit Audio Jack & USB Issued Date 2010/06/30 Deciphered Date 2012/06/30 Title
page 35 ~ 44 page 25 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P02-Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.22
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA7323P
Date: Friday, March 04, 2011 Sheet 2 of 47
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A B C D E
Voltage Rails FCH Hudson-M1 Brazos FCH Hudson-M1
Power Plane Description S1 S3 S5 USB Port List PCIE Port List SATA Port List
VIN Adapter power supply (19V) N/A N/A N/A USB1.1 PCIE0 SATA0 HDD
B+ AC or battery power rail for power circuit. N/A N/A N/A
Port0 NC PCIE1 SATA1 ODD
APU
+APU_CORE Core voltage for CPU (0.7-1.2V) ON OFF OFF GPU
+APU_CORE_NB 1.0V switched power rail ON OFF OFF Port1 NC PCIE2 PCIE x4 SATA2 NC
1 1
+1.5V 1.5V power rail for CPU VDDIO and DDRIII ON ON OFF
+0.75VS 0.75VS switched power rail for DDR terminator ON OFF OFF
USB2.0 PCIE3 SATA3 NC
+1.0VS 1.0V switched power rail for NB VDDC & VGA ON OFF OFF Port0 JUSB1 PCIE0 LAN SATA4 NC
+1.1VS 1.1VS switched power rail ON OFF OFF
Port1 JUSB2 PCIE1 WLAN SATA5 NC
FCH
+1.8VS 1.8V switched power rail ON OFF OFF
+3VALW 3.3V always on power rail ON ON ON* Port2 Camera PCIE2 NC
+3V_LAN 3.3V power rail for LAN ON ON(WOL) OFF
Port3 JMINI(WLAN) PCIE3 NC
+3VS 3.3V switched power rail ON OFF OFF
+5VALW 5V always on power rail ON ON ON* Port4 Card Reader
+5VS 5V switched power rail ON OFF OFF
Port5 JUSB3
+VSB VSB always on power rail ON ON ON*
+RTCVCC RTC power ON ON ON Port6 NC
+1.1VALW 1.1V always on power rail ON ON ON*
Port7 NC
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Port8 NC
2 Port9 NC 2
SMBUS Control Table
Port10 NC
SOURCE MIINI1 BATT APU FCH SODIMM VRAM
Port11 NC
Port12 NC
EC_SMB_CK1
EC_SMB_DA1
KB930 X V X X X X Port13 NC
EC_SMB_CK2
EC_SMB_DA2
KB930 X X V V X V
FCH_SMCLK0
FCH_SMDAT0 PCH
V X X X V X SCL0,
SCL1,
SDA0
SDA1
(Primary SMBUS in the S0 domain)
(Secondary SMBUS supporting ASF)
SCL2, SDA2 (Primary SMBUS in the S5 domain)
SCL3, SDA3 (Primary low-voltage SBMBUS for Processor TSI)
FCH_SMCLK3
FCH_SMDAT3 PCH
X X V X X X SCL4, SDA4 (Primary SMBUS in the S5 domain)
3 3
Symbol Note :
BOM Structure : means Digital Ground
15@ : E240 1.5GHz
16@ :E350 1.6GHz
X76@ : VRAM second source : means Analog Ground
LS@ : Level Shift
4 NLS@ :non Level Shift 4
USB30@ :USB3.0
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/06/30 Deciphered Date 2012/06/30 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P03-Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.22
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA7323P
Date: Friday, March 04, 2011 Sheet 3 of 47
A B C D E
5 4 3 2 1
Without BACO option :
Power-Up/Down Sequence PE_GPIO0 : Low -> Reset dGPU ; High ->Normal operation
1. All the ASIC supplies must fully reach their respective nominal voltages within 20 ms of the start of the ramp-up PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON
sequence, though a shorter ramp-up duration is preferred.
BACO option :
2. VDDR3 should ramp-up before or simultaneously with VDDC. PE_GPIO0 : High ->Normal operation (dGPU is not reseton BACO mode)
PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON (always High)
3. For LVDS, DPx_VDD10 should ramp-up before DPx_VDD18 and the PCIe Reference clock should begin before
D DPx_VDD18. For power-down, DPx_VDD18 should ramp-down before DPx_VDD10. dGPU Power Pins Voltage PX 3.0 BACO Mode Max current
D
4. The external pull-ups on the DDC/AUX signals (if applicable) should ramp-up before or after both VDDC and PCIE_PVDD, PCIE_VDDR, TSVDD, VDDR4, VDD_CT, 1.8V OFF ON 1679mA
VDD_CT have ramped up. DPE_PVDD, DP[F:E]_VDD18, DP[D:A]_PVDD,
DP[D:A]_VDD18, AVDD, VDD1DI, A2VDDQ, VDD2DI,
5.VDDC and VDD_CT should not ramp-up simultaneously. (e.g., VDDC should reach 90% before VDD_CT starts to
DPLL_PVDD, MPV18, and SPV18
ramp-up (or vice versa).)
DP[F:E]_VDD10, DP[D:A]_VDD10, DPLL_VDDC, and 1.0V OFF ON 575mA
SPV10
PCIE_VDDC 1.0V OFF ON 2A
VDDR3(3.3VSG) Note: Do not drive any IOs before VDDR3 is ramped up.
VDDR3 , and A2VDD 3.3V OFF ON 190mA
BIF_VDDC (current consumption = [email protected], in Same as OFF ON 70mA
PCIE_VDDC(1.0V) BACO mode) VDDC Same as
PCIE_VDDC
VDDR1 1.5V OFF OFF 2.8A
C
VDDR1(1.5VSG) VDDC/VDDCI 1.12V OFF OFF 12.9A C
VDDC/VDDCI(1.12V)
VDD_CT(1.8V)
PE_GPIO0 PE_EN BACO Switch
iGPU dGPU
PERSTb BIF_VDDC
PE_GPIO1
REFCLK PX_mode
B +3.3VALW MOS
+3.3VSG B
Straps Reset 1
+1.5V SI4800
+1.5VSG
Straps Valid +1.0V +1.0VSG
Regulator
2 3
Global ASIC Reset
+B Regulator
+VGA_CORE
+1.8V +1.8VSG
T4+16clock
SI4800
5 4
PWRGOOD
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/08/20 Deciphered Date 2012/06/30 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P04-dGPU Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.22
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA7323P
Date: Friday, March 04, 2011 Sheet 4 of 47
5 4 3 2 1
5 4 3 2 1
U22
ZACATE ZM161032B2238 1.6G BGA 413P
+1.8VS U22B
Part Number = SA00004KG70
16@ A8 H3 R398 1 2 150_0402_1%
DISPLAYPORT 1
B8 TDP1_TXP0 DP_ZVSS
DP MISC
TDP1_TXN0 G2
R399 1 2 1K_0402_5% APU_SVC B9 DP_BLON H2
R400 1 2 1K_0402_5% APU_SVD U22 A9 TDP1_TXP1 DP_DIGON H1
D R142 2 1 300_0402_5% APU_RST# TDP1_TXN1 DP_VARY_BL D
R401 2 1 300_0402_5% APU_PWRGD D10
R402 1 2 510_0402_1% TEST_25_L C10 TDP1_TXP2 B2
R141 1 2 1K_0402_5% TEST36 TDP1_TXN2 TDP1_AUXP C2
A10 TDP1_AUXN
B10 TDP1_TXP3 C1
ONTARIO CMC50AFPB22GT 1G BGA TDP1_TXN3 TDP1_HPD
C237 0.01U_0402_25V7K Part Number = SA00004KD70 B5 A3
1 2 @ APU_RST# C50@ A5 LTDP0_TXP0 LTDP0_AUXP B3
DISPLAYPORT 0
C238 0.01U_0402_25V7K LTDP0_TXN0 LTDP0_AUXN
1 2 @ APU_PWRGD D6 D3 R406 1 2 100K_0402_5%
C6 LTDP0_TXP1 LTDP0_HPD
LTDP0_TXN1 C12
A6 DAC_RED D13
B6 LTDP0_TXP2 DAC_REDB A12
+3VS LTDP0_TXN2 DAC_GREEN B12
D8 DAC_GREENB A13
VGA DAC
R410 1 2 1K_0402_5% APU_PROCHOT# C8 LTDP0_TXP3 DAC_BLUE B13
LTDP0_TXN3 DAC_BLUEB
V2 E1
12 APU_CLKP V1 CLKIN_H DAC_HSYNC E2
12 APU_CLKN CLKIN_L DAC_VSYNC
D2 F2
CLK
12 APU_DISP_CLKP DISP_CLKIN_H DAC_SCL
R411 1 2 1K_0402_5% APU_ALERT#_R D1 D4
12 APU_DISP_CLKN DISP_CLKIN_L DAC_SDA
R143 1 2 1K_0402_5% APU_SIC J1 D12 R144 1 2 499_0402_1%
43 APU_SVC J2 SVC DAC_ZVSS
43 APU_SVD SVD
R414 1 2 1K_0402_5% R1
SER
APU_SID PAD T66
APU_SIC P3 TEST4 R2
SIC TEST5 PAD T67
APU_SID P4 R6
SID TEST6 T5
TEST14 PAD T68
T3 E4 TEST15 R415 1 @ 2 1K_0402_5%
C 12 APU_RST# T4 RESET_L TEST15 K4 C
12 APU_PWRGD
CTRL
PWROK TEST16 L1
R169 1 2 0_0402_5% APU_PROCHOT# U1 TEST17 L2 TEST18 R416 1 2 1K_0402_5%
29 EC_THERM# PROCHOT_L TEST18
R168 1 @ 2 0_0402_5% APU_THERMTRIP# U2 M2 TEST19 R417 1 2 1K_0402_5%
TEST
12 FCH_PROCHOT# T2 THERMTRIP_L TEST19 K1
APU_ALERT#_R TEST25_H R418 1 2 510_0402_1%
ALERT_L TEST25_H K2 TEST_25_L
APU_TDI N2 TEST25_L L5
APU_TDO N1 TDI TEST28_H M5
APU_TCK P1 TDO TEST28_L M21 TEST31
TCK TEST31 PAD T73
JTAG
APU_TMS P2 J18 TEST33_H C516 1 2 0.1U_0402_16V4Z R420 1 2 51_0402_1%
APU_TRST# M4 TMS TEST33_H J19 TEST33_L C517 1 2 0.1U_0402_16V4Z R421 1 2 51_0402_1%
T93PAD TRST_L TEST33_L
APU_DBRDY M3 U15 Delete Test point for layout limitation
T94PAD DBRDY TEST34_H
Close to APU APU_DBREQ# M1 T15 20100917
DBREQ_L TEST34_L H4 TEST35 R422 1 @ 2 1K_0402_5%
F4 TEST35 N5 TEST36
43 APU_VDDNB_RUN_FB_H G1 VDDCR_NB_SENSE TEST36 R5 TEST37 PAD T76 R958 1 2 1K_0402_5%