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ZZZ1 ZZZ2 ZZZ3 ZZZ4 ZZZ5 ZZZ6 ZZZ7 ZZZ8 PJP1
PCB LA-4772P LS-4773P LS-4774P LS-4775P LS-4777P LS-4778P LS-4779P 45@ DCIN
ATIDAZ@ ATIDA@ ATIDA@ ATIDA@ ATIDA@ ATIDA@ ATIDA@ ATIDA@
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Compal Confidential
KHLB2 Schematics Document
2 2
Intel Mobile Penryn uFCPGA with Cantiga_PM + DDRIII + ICH9M
2009-01-19
3 3
REV:1.0
4 4
Security Classification Compal Secret Data Compal Electronics,Ltd.
Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KHLB2 MB Schematic
Date: Monday, January 19, 2009 Sheet 1 of 56
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A B C D E
Compal Confidential
Model Name : KHLB2
Thermal Sensor Clock Gen.
File Name : LA-4772P(ATI) Mobile Penryn SLG8SP556VTR
EMC1402
page 5 ICS9LPRS387BKLFT
1
uFCPGA-478 CPU page23 1
page5,6,7
H_A#(3..35) FSB
H_D#(0..63) 667/800/1066MHz
LVDS
LCD Conn.
page 25
HDMI Intel Cantiga GMCH DDR3-SO-DIMM X2
Dual Channel BANK 0, 1, 2, 3
page 24 page 14,15
CRT PCBGA 1329
page 26 DDR3-800/1067(1.5V)
page 8,9,10,11,12,13
PCI-Express
2 2
VRAM 32M*32 USB conn x3 Bluetooth CMOS Camera Finger Print
GDDR3*4 TO I/O/Bpage Conn page Conn page 45
page 21 40 39 page 45
DMI C-Line
ATI M96 USB
3.3V 48MHz
page 16~20
Intel ICH9-M
PCI-Express
3.3V 24.576MHz/48Mhz HD Audio
mBGA-676
S-ATA
page27,28,29,30
port 0 port 1
GMCH HDA MDC 1.5 HDA Codec
New Card MINI Card x2 Conn 45 ALC268
LAN(GbE) LPC BUS page 8 page page 41
Socket WLAN,
RTL8111C/8102E Card Reader S-ATA HDD S-ATA ODD
TV-Tuner Conn.page 31 Conn. page 31
3
page 36 JMB385 3
page 35 page 33 page 32
Audio AMP
3 in 1 EC page 42
RJ45 socket ENE KB926D3
RTC CKT.
page 34 page 32 page37
page 28
Function/B
Power On/Off CKT. Power USB/B
page 38
page 40 Int.KBD
page38
Touch Pad
page39
USB I/O Conn.
DC/DC Interface CKT. CIR BIOS
page39
page 46
LID SW
4 4
Power Circuit DC/DC Debug port
page 40
page 46,47,48,50
51,52,53
TPM Security Classification Compal Secret Data Compal Electronics,Ltd.
Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
CHARGER LED MB Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
page 49 page 45 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KHLBX MB Schematic
Date: Monday, January 19, 2009 Sheet 2 of 56
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A B C D E
DDR3 Voltage Rails
1 1
+5VS
EC SM Bus1 address EC SM Bus2 address
+3VS
+1.5VS Device Address Device Address
power
+1.1VS Smart Battery 0001 011X b EMC 1402 100_1100X b
plane
+VCCP EEPROM(24C16/02) 1010 000X b ATI M96
+5VALW +1.5V +CPU_CORE
+B +1.8V +VGA_CORE
+3VALW +0.75V +1.8VS
State
2 2
S0
O O O O GPIO PIN Define
S1
O O O O
S3
O O O X ID3 ID2 ID1 ID0
JHT00(1100 ) X X R361 R357
S5 S4/AC
O O X X JHT01 (1101 ) X X R361 R355
JHL90 (1110 ) X X R360 R357
S5 S4/ Battery only
O X X X JHL91 (1111 ) X X R360 R355
KHLB0 (0000 ) R1052 R1150 R922 R928
S5 S4/AC & Battery
don't exist X X X X KHLB1( 0001 ) R1052 R1150 R922 R923
KHLB2( 0010 ) R1052 R1150 R927 R928
12 inch( 0011 ) X X X X
12 inch( 0100 ) X X X X
12 inch( 0101 ) X X X X
3 3
Reserve (0110 ) X X X X
Reserve (0111 ) X X X X
Reserve (1000 ) X X X X
Reserve (1001 ) X X X X
Reserve (1010 ) X X X X
Reserve (1011 ) X X X X
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
MB Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KHLBX MB Schematic
Date: Monday, January 19, 2009 Sheet 3 of 56
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A B C D E
VGA and DDR2 Voltage Rails (NB9M-GS) EDP at Tj = 97C*
Power Supply Rail NB9P-GS NB9P-GE2
VRAM POWER SQUENCE (V) GDDR3 DDR2 GDDR3 DDR2
power +3VS
plane GDDR3 FOR 4 UNIT = 5.4A NVVDD Variable 20.65A 16.96A 18.47A 16.06A
State +1.8VS +VGA_CORE
FB_DLLAVDD 1.1 10mA
+1.1VS
FB_PLLAVDD 1.1 10mA
S0
1
O O O O IFPC_IOVDD 1.1 80mA 1
S1
O O O O IFPD_IOVDD 1.1 80mA
S3
O O X X IFPE_IOVDD 1.1 160mA
S5 S4/AC
O O X X IFPF_IOVDD 1.1 160mA
S5 S4/ Battery only
O X X X PEX_IOVDD/Q 1.1 1550mA
S5 S4/AC & Battery
don't exist X X X X PEX_PLLVDD 1.1 90mA
PLLVDD 1.1 45mA
SP_PLLVDD 1.1 45mA
VID_PLLVDD 1.1 45mA
GPIO I/O ACTIVE Function Description
TOTAL 1.1 2.3A
GPIO0 N/A N/A Available
FBVDD/Q 1.8 3.37A 2.02A 3.21A 2.25A
GPIO1 IN - Hot plug detect for IFP link C IFPA_IOVDD 1.8 95mA
IFPB_IOVDD 1.8 95mA
GPIO2 OUT H Panel Back-Light brightness(PWM)
IFPAB_PLLVDD 1.8 70mA
GPIO3 OUT H Panel Power Enable IFPCD_PLLVDD 1.8 25mA
IFPEF_PLLVDD 1.8 85mA
2
GPIO4 OUT H Panel Back-Light On/Off (PWM) 2
TOTAL 1.8 5.76A 3.69A 5.47A 3.96A
GPIO5 OUT - GPU VID0
DACA_VDD 3.3 110mA
GPIO6 OUT - GPU VID1 DACB_VDD 3.3 120mA
DACC_VDD 3.3 110mA
GPIO7 OUT - GPU VID2 or MEM VID
MIOA_VDDQ 3.3 10mA
GPIO8 I/O L Thermal Catastrophic Overtemp MIOB_VDDQ 3.3 10mA
VDD33 3.3 150mA
GPIO9 OUT L FAN control and/or Thermal Alert (PWM)
TOTAL 3.3 0.51A
GPIO10 OUT Memory VREF switch
GPIO11 I/O L SLI raster sync
POWER UP/DOWN Sequence
GPIO12 IN - AC power detect pin
GPIO13 OUT - Power supply control
GPIO14 OUT - Power supply control
3 3
GPIO15 IN - Hot plug detect for IFP link E
BBP must ramp up before or at the same time as VDDC but not after(ensure that BBP>= VDDC at all times)
GPIO16 IN - Dongle DVI Mode control for Primary Displayport
GPIO17 IN - Dongle HDMI Mode control for Primary Displayport
GPIO18 IN - Dongle DVI Mode control for Secondary Displayport BBP/N
GPIO19 IN - Dongle HDMI Mode control for Secondary Displayport
(+VGA_CORE) VDDC
GPIO20 IN - Hot plug detect for IFP link D
(1.8VS) VDD_CT
GPIO21 IN - Hot plug detect for IFP link E
(1.1VS) DPX_PDD10
GPIO22 IN - SLI swap ready signal
GPIO23 N/A N/A Available
<20ms <20ms
(3.3VS) VDDR3
4 4
Lower Voltage leading higner voltage requirement VDDR3-VDD_CT<2V Lower Voltage trialing higner voltage requirement VDDR3-VDD_CT<2V
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/07/15 Deciphered Date 2009/07/15 Title
VGA Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KHLBX MB Schematic
Date: Monday, January 19, 2009 Sheet 4 of 56
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5 4 3 2 1
USE->56,NOT USE->50 XDP Reserve
+VCCP +3VS
H_IERR# R1 1 2 49.9_0402_1% XDP_DBRESET# R2 1 2 @ 1K_0402_5%
H_PROCHOT# R3 1 2 56_0402_5%
+VCCP
USE->68,NOT USE-->56 XDP_TDI R4 1 2 54.9_0402_1%
D XDP_TMS R5 1 2 54.9_0402_1% D
CONN@
JCPU1A XDP_TDO R6 1 2 @ 54.9_0402_1%
H_A#3 J4 H1 H_ADS#
<8> H_A#3 A[3]# ADS# H_ADS# <8>
ADDR GROUP_0
H_A#4 L5 E2 H_BNR# XDP_TRST# R7 1 2 54.9_0402_1%
<8> H_A#4 H_A#5 A[4]# BNR# H_BPRI# H_BNR# <8>
<8> H_A#5 L4 A[5]# BPRI# G5 H_BPRI# <8>
H_A#6 K5 XDP_TCK R8 1 2 54.9_0402_1%
<8> H_A#6 H_A#7 A[6]# H_DEFER#
<8> H_A#7 M3 A[7]# DEFER# H5 H_DEFER# <8>
H_A#8 N2 F21 H_DRDY#
<8> H_A#8 H_A#9 A[8]# DRDY# H_DBSY# H_DRDY# <8>
<8> H_A#9 J1 A[9]# DBSY# E1 H_DBSY# <8>
H_A#10 N3
<8> H_A#10 H_A#11 A[10]# H_BR0#
<8> H_A#11 P5 A[11]# BR0# F1 H_BR0# <8>
H_A#12 P2
<8> H_A#12 A[12]#
CONTROL
H_A#13 L2 D20 H_IERR#
<8> H_A#13 H_A#14 A[13]# IERR# H_INIT#
<8> H_A#14 P4 A[14]# INIT# B3 H_INIT# <28>
H_A#15 P1
<8> H_A#15 H_A#16 A[15]# H_LOCK#
R1 H4
<8> H_A#16 H_ADSTB#0 M1
A[16]# LOCK# H_LOCK# <8> 1/29 change to EMC1402 pn U1
<8> H_ADSTB#0
H_REQ#0 K3
ADSTB[0]#
RESET# C1
F3
H_RESET#
H_RS#0
H_RESET# <8> EMC1402 +3VS
<8> H_REQ#0 REQ[0]# RS[0]# H_RS#0 <8>
H_REQ#1 H2 F4 H_RS#1 C1
<8> H_REQ#1 REQ[1]# RS[1]# H_RS#1 <8>
H_REQ#2 K2 G3 H_RS#2 0.1U_0402_16V4Z
<8> H_REQ#2 REQ[2]# RS[2]# H_RS#2 <8>
H_REQ#3 J3 G2 H_TRDY# 1 2
<8> H_REQ#3 REQ[3]# TRDY# H_TRDY# <8>
H_REQ#4 L1 LM95245CIMMX NOPB MSOP 8P
<8> H_REQ#4 REQ[4]# H_HIT# NS@
HIT# G6 H_HIT# <8>
H_A#17 Y2 E4 H_HITM#
<8> H_A#17 H_A#18 A[17]# HITM# H_HITM# <8>
<8> H_A#18 U5 A[18]#
H_A#19 R3 AD4 1 U1
<8> H_A#19 A[19]# BPM[0]#
ADDR GROUP_1
H_A#20 W6 AD3 1 8
<8> H_A#20 A[20]# BPM[1]# VDD SCLK EC_SMB_CK2 <17,37>
C H_A#21 U4 AD1 C2 C
<8> H_A#21 H_A#22 A[21]# BPM[2]# 2200P_0402_50V7K H_THERMDA
<8> H_A#22 Y5 A[22]# BPM[3]# AC4 2 D+ SDATA 7 EC_SMB_DA2 <17,37>
H_A#23 2
XDP/ITP SIGNALS
<8> H_A#23 U1 A[23]# PRDY# AC2
H_A#24 R4 AC1 H_THERMDC 3 6 2 1 +3VS
<8> H_A#24 H_A#25 A[24]# PREQ# XDP_TCK D- ALERT/THERM2 R9 10K_0402_5%
<8> H_A#25 T5 A[25]# TCK AC5
H_A#26 T3 AA6 XDP_TDI +3VS 1 2 4 5
<8> H_A#26 H_A#27 A[26]# TDI XDP_TDO R10 10K_0402_5% THERM GND
<8> H_A#27 W2 A[27]# TDO AB3
H_A#28 W5 AB5 XDP_TMS
<8> H_A#28 H_A#29 A[28]# TMS XDP_TRST# EMC1402-1-ACZL-TR MSOP
<8> H_A#29 Y4 A[29]# TRST# AB6
H_A#30 U2 C20 XDP_DBRESET# Address:100_1100 SMSC@
<8> H_A#30 A[30]# DBR# XDP_DBRESET# <29>
H_A#31 V4
<8> H_A#31 H_A#32 A[31]#
<8> H_A#32 W3 A[32]#
H_A#33 AA4 THERMAL
<8> H_A#33 H_A#34 A[33]# H_PROCHOT#
<8> H_A#34 AB2 A[34]#
H_A#35 AA3 D21
<8> H_A#35 H_ADSTB#1 A[35]# PROCHOT# H_THERMDA
<8> H_ADSTB#1 V1 ADSTB[1]# THERMDA A24
B25 H_THERMDC
H_A20M# THERMDC
A6
<28> H_A20M# A20M#
FAN1 Conn
ICH
ICH
H_FERR# A5 C7 H_THERMTRIP# 10/30 add
<28> H_FERR# FERR# THERMTRIP# H_THERMTRIP# <8,28>
H_IGNNE# C4 @
<28> H_IGNNE# IGNNE# EN_FAN1 C1651 2 1 100P_0402_50V8J
H_STPCLK# D5
<28> H_STPCLK# STPCLK#
H_INTR C6 H CLK
<28> H_INTR LINT0
H_NMI B4 A22 CLK_CPU_BCLK
<28> H_NMI LINT1 BCLK[0] CLK_CPU_BCLK <23>
H_SMI# A3 A21 CLK_CPU_BCLK#
<28> H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# <23> +5VS
M4 C3 +5VS
RSVD[01] 10U_0805_10V4Z 1
N5 RSVD[02] H_THERMDA, H_THERMDC routing together, 2
T2 RSVD[03]
1
B
V3 Trace width / Spacing = 10 / 10 mil B
RSVD[04] U2 D1
B2
RESERVED
RSVD[05]
RSVD pins on the CPU D2 RSVD[06] VEN1 GND 8 BAS16_SOT23-3
should be left as NO D22 RSVD[07] VIN2 GND 7
D3 +VCC_FAN1 3 6
2
CONNECT F6
RSVD[08]