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Contents
Ethernet Expansion Board 1
Ethernet Interface 3
Interface I/O Description 3
Status and Command Circuitry 4
CPU Read/Write Access 4
LANCE Interrupt Status 4
Read/Write Control Register 4
State Machine Control Circuitry 4
LANCE Interface 6
Ethernet Interface 6
Software Interface 6
Expansion Slot 7
On-Board Addressing 7
Contents
Interface Registers and Command
Descriptions 7
ID Register (Base Address
03FFFF - 03FFCO) 8
Software Reset 8
LANCE Data Latch 9
Status Ring Address 9
Control Register 9
LANCE Register Address and Data
Ports 10
Software Operation 10
Troubleshooting 11
I/O Cycle 11
Register Read/Write Cycle 13
Board ID Read-Only Cycle 14
CPU LANCE Read/Write Cycle 14
DMA Cycle 14
DMA Read/Write (Single) 15
DMA Read/Write (Burst) 17
Interrupt Cycle 17
Contents
Figures
1 Expansion Board Block Diagram 2
2 Ethernet State Diagram 12
3 Expansion Board Cycle Diagram 16
4 CPU non-LANCE Read-Timing
Diagram 18
5 CPU non - L ..~.NCE lA]y-;+-=-'T';TTl;-nrr
""'.&. ........................... ':;:11
...L ' - " " "
Diagram 19
6 CPU LANCE Read-Timing Diagram 20
7 CPU LANCE Write-Timing
Diagram 21
8 LANCE DMA Read Cycle 22
9 LANCE DMA Write Cycle 23
Tables
1 Ethernet IS-Pin D Connector 6
2 Expansion Slot Offset
Addresses 7
3 State Assignments 13
Ethernet Expansion Board Theory of Operation
This overview summarizes the major functions performed by the
UNIXTM PC Ethernet Expansion Board hardware. The topics covered
here include:
o Interface I/O description
o Status and command circuitry
o State machine control circuitry
o LANCE interface
o Ethernet interface
o Software interface
Ethernet ExPansion Board
The Ethernet Expansion Board (EEB), when plugged into an AT&T
UNIXTM PC, provides an interface to an Ethernet communications
network operating at a transfer rate of 10MB/sec. The EEB is
based on the AMD 7990 and 7992 chip set, which performs the
following functions:
o AM7990 Local Area Network Controller for Ethernet (LANCE)
performs memory management, packet handling, error reporting,
and interface functions.
o AM7992 Serial Interface Adapter (SIA) performs Manchester
encoding and decoding of the serial bit stream with phase
lock loop, clock recovery.
The Expansion Board, as shown in the Figure 1 block diagram, is a
circuit board containing the I/O and DMA interface to the Lm~CE
chip, a state machine with a read/write control register, a
separate DMA controller for LANCE status, and a board ID/Ethernet
address ROM.
1
XR/w*, XIOEN *
BUFFER
XRST*
EXPRQ EXPBG * XR/W* OS * INT*
SYSTEM
STATUS CONTROLLER
RING
ADDRESS
BUFFER BUFFER AND
DATA
o
INT*, HOLD*, RDY*, DAS* LAS* I"'tI
HLDA*,RDy*,DAS*, LAG*
BUFFER RECEIVE
AMD7992 ~COLL.,
AMD7990
LANCE
SERIAL
INTERFACE t.- XMIT,
ADAPTOR REC.
BUFFER TRANSMIT
~
~ ~
DC-DC 12V.
CONVERTER GND
Figure 1 Expansion Board Block Diagram
Ethernet Expansion Board Theory of Operation
Once the LANCE chip is initialized, all data transfers including
buffer chaining are handled by the chip. Timing and control are
maintained by the on-board state machine. LANCE status is
transferred to memory by a separate state machine DMA controller
on each LANCE interrupt. This status is placed in a 256-word
ring in memory allowing the software a 256-packet interrupt
latency. Because of maximum throughput, the CPU is able to find
all data and status in memory and never needs to talk directly to
the board. The board is also not re~~ired to wait for CPU
response or to share board resources with the CPU accesses.
LANCE operation consists of two distinct modes, transmit and
receive. In the transmit mode, the LANCE chip directly accesses
data in memory. Data is conditioned by adding a preamble, sync
pattern, and appending a 32-bit cycle redundancy check (eRe)
This packet is sent from the LANCE to the AM7992A Serial
Interface Adapter (SIA). The SIA then transmits this packet to
the Ethernet system AM7995 transceiver. In the receive mode,
packets are sent by the SIA to the LANCE.
Ethernet Interface
The Ethernet system, to which the EEB is connected, consists of
an external AM7995 transceiver with power supply and the Ethernet
coax transmission line. The EEB is connected to this system by
cable. For a detailed description of the Ethernet system
interface, refer to the Ethernet/IEEE 802.3 specification and
the technical manual for Local Area Network Controller AM 7990
(LANCE) by Advanced Micro Devices.
Interface I/O Descrtption
The expansion-board interface consists of drivers and receivers
for all required signals to and from the UNIX PC's expansion bus.
The expansion data bus goes through buffers that are controlled
by the state machine section to create the internal data bus.
The address bus and the bus cycle control signals are received
with buffers that are always enabled to create the internal
address and control bus. The internal address and control bus,
with the comparator for board ID, allows constant monitoring for
board I/O requests, which are then passed on to the state
machine.
For board-initiated DMA cycles, the state machine-generated
request, read/write, and data strobe signals are also driven onto
the expansion bus by this section.
3
Ethernet Expansion Board Theory of Operation
Status and Command Circuitry
The amount of on-board status and command information is limited.
The board ID function has been expanded to allow the CPU to
interrogate the board for the 6-byte Ethernet address, as well as
for the required 4-byte board ID. This information is contained
in a 32-byte prom accessed at odd byte addresses in the upper 32
bytes of the board address block. A write to any of these
addresses produces a board reset.
CPU Read/Write Access
The status and command section provides CPU read/write access to
the LANCE chip address and data ports. However, due to the long
access time of the chip, LANCE reads do not provide data to the
CPU in a single cycle. Data is latched on board during the LANCE
read; it is then read by the CPU in a separate latch read cycle.
LANCE Interrupt Status
This section contains a 16-bit register and an 8-bit counter.
The LANCE interrupt status is written automatically to memory at
the location of the combined 24-bit address by the on-board DMA.
Read/Write Control Register
A 4-bit read/write control register is also contained in this
section. This register allows the CPU to disable DMA for
diagnostic purposes, select Ethernet, and make selections between
INT 01 and INT 05. The register contains one unused bit.
State Machine Control Circuitry
The state machine control section consists of five PALs providing
control and timing signals for all other sections. A 20R8 PAL
determines when a board cycle needs to be initiated and what type
of cycle it should be. The 20R8 arbitrates between LANCE DMA
requests (HOLD), LANCE interrupts, and CPU I/O requests and
generates the LANCE HLDA and expansion bus requests as well as on-
board I/O cycles.
4
Ethernet Expansion Board Theory of qperation
Each of 11 non-idle cycles has its own timing and control
requirements (see timing diagrams for more detail). These cycles
consist of five CPU-initiated operations which are:
o CPU non-LANCE Read
o CPU non-LANCE Write
o CPU LANCE Read
o CPU LANCE Write
o CPU Data Latch Read
These are all individual cycles that can occur only when the
state machine is in its idle state. The state machine is always
returned to the idle state.
Three additional cycles are initiated by LANCE DMA requests.
These are:
o request cycle
o LANCE DMA read cycle
o LANCE DMA write cycle
The request cycle precedes a single LANCE DMA cycle or burst of
cycles. This cycle insures UNIX PC LANCE synchronization. The
LAl~CE D~~ read or write cycles follow the request cycle. Lne
state machine goes directly from the request cycle to the read or
write without going through idle. As long as the LANCE DMA
request stays active, each DMA cycle leads directly to the next,
again without idle. LANCE DMA requests are either single cycle
for buffer management fetches or bursts of eight cycles for data
transfers.
The three final cycle types are also linked together with no
intervening idle states. When the LANCE asserts its interrupt
the state machine executes a status LANCE read cycle reading the
LANCE interrupt status into the on-board data latch. A status
DMA cycle is executed to place the status in the status ring in
memory. Finally, a status LANCE write is executed to clear the
LANCE interrupt, and a CPU interrupt is generated at the same
time.
5
Ethernet Expansion Board Theory of Operation
The 20R8 PAL encodes the cycle type in 4 bits. These 4 bits are
fed to three additional registered PALS. These signals combine
with a 3-bit counter for timing within each cycle and, with
several handshake signals from the LANCE, allowing these three
PALS to generate all LANCE-related timing and control signals.
In addition, an I/O cycle signal is generated for on-board non-
LANCE cycles. This signal goes to the fifth PAL. This PAL is a
nonregistered PAL that generates timing and control for on-board
I/O that is based on I/O cycle and address decodes.
LANCE Interface
The LANCE interface consists of a 16-bit, multiplexed address and
data bus with associated handshake signals. The hardware
provides three sets of 16-bit latches for address, read data, and
write data. This section also includes a buffer for the upper 5
bits of address and a 4-bit data buffer. These buffers provide
for the status write to clear the LANCE interrupt.
Ethernet Interface
The Ethernet interface is handled by the AMD chip set. The LANCE
chip sends transmit data to the 7992 and gets receive data and
collision detection from the 7992. The 7992 provides the
interface to the off-board transceiver through a standard IS-pin
D-connector interface. Table 1 lists the pin-out assignments for
this connector.
Table 1 Ethernet 15-Pin D Connector
Pin Signal Pin Signal Pin Signal
1 GND 6 GND 11 Not Used
2 COL+ 7 Not Used 12 RCVR-
3 I TRANS + 8 Not Used 13 PLUS12
4 Not Used 9 COL- 14 Not Used
5 RCVR+ 10 TRANS- 15 Not Used
Software Interface
The EEB occupies the standard 2S6Kbyte (or 128K word) block
assigned to each expansion slot.
6
Ethernet Expansion Board Theory of Operation
Expansion Slot
The expansion cards in the u~IX PC are each assigned 256K bytes
of address space. Since all addressing is done on word
boundaries, 128K words of address space is available. Expansion
bus address bits XAI - XA17 define this space. Each expansion
slot contains hardwired identification bits XIDO - XID2 to define
seven unique slot addresses. Bits XA18 - XA20 are compared
against the slot identification bits to validate the address.
Also, address bit XA21 is always zero; similarly, expansion
addresses XA22 and XA23 are always ones.
Therefore, once the EEB is plugged into its slot, the
predetermined XA18 - XA23 bits generate the offset address, while
devices.
The offset addresses used in the UNIX PC are listed below.
Table 2 Expansion Slot Offset Addresses
Slot Number Offset Address (h)
0 OCOOOOO
1 OC40000
2 OC80000
3 OCCOOOO
4 ODOOOOO
5 OD40000
6 OD80000
7 ODCOOOO
On-Board Addressing
Only a small number of addresses are decoded for on-board
functions. These addresses are not fully decoded in hardware.
Undefined addresses should not be used; they may affect on-board
functions. Reads and writes are always full words, even if only
8-bit values are significant.
Interface Registers and Command Descriptions
The following paragraphs list the registers used in Ethernet
interface operations and the command descriptions that select the
I/O functions.
7
Ethernet Expansion Board Theory of Operation
ID Register (Base Address 03FFFF - 03FFCO)
When the UNIX PC is first powered up, the UNIX kernel reads the
ID register into memory. The ID register is a set of 8-bit
registers located at odd byte addresses in the upper 32 words of
the board address block. The upper four words contain the
required board identification numbers. The lowest six words
contain the board-specific Ethernet station address. The
appropriate driver must determine where the hardware is located.
The getslot system call (see UNIX System V User's Manual,
drivers(7