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Service Manual
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MDCT-1000
SERVICE MANUAL
Ver 1.1 2001. 07
US Model
US and foreign patents licensed from Dolby Laboratories Licensing Corporation
Model Name Using Similar Mechanism MD Mechanism Type Optical Pick-up Mechanism Type
MDCC-2000 CCMD-2000 KMS-250A
SPECIFICATIONS
Laser diode properties Material: GaAlAs Wavelength: 780 nm Emission duration: Continuous Laser output: Less than 44.6 µW (This output is the value measured at a distance of about 200 mm from the lens surface on the optical pick-up block with 7 mm aperture.) Revolutions 400 rpm to 1,800 rpm (CLV) Error correction Advanced Cross Interleave Reed Solomon Code (ACIRC) Sampling frequency 44.1 kHz Coding ATRAC 3 (Adaptive TRansform Acoustic Coding 3) Modulation system EFM (Eight to Fourteen Modulation) Number of channels 2 or 4 monaural channels Frequency response 5010,000 Hz Speaker Approx. 5.0 cm (2 inches) dia.
Power output 600 mW (at 10% distortion) Output EAR (minijack) for 8300 earphones Other connector CONTROL UNIT connector Power requirements 12 V DC DC IN 12V jack accepts the supplied AC power adaptor for use on 120 V AC, 60 Hz Dimensions Approx. 320 x 280 x 118 mm (w/h/d) (125/8 x 111/8 x 43/4 inches) including projecting parts and controls Mass Approx. 3.7 kg (8 lb 3 oz) Accessories supplied AC power adaptor (1) AC power cord (1) Design and specifications are subject to change without notice.
MD CONFER-TRANSCRIBER
9-873-186-02
2001G1600-1 © 2001.7
Sony Corporation
Personal Audio Company Shinagawa Tec Service Manual Production Group
MDCT-1000
TABLE OF CONTENTS 1. GENERAL ·········································································· 4 2. DISASSEMBLY
2-1. 2-2. 2-3. 2-4. 2-5. 2-6. 2-7. 2-8. 2-9. 2-10. 2-11. 2-12. 2-13. 2-14. Cabinet(Upper) Section ················································ 6 Switch Section ······························································ 7 LCD Section ································································· 7 MD Section ·································································· 8 Volume Section ···························································· 8 Main Board ·································································· 9 Door ··········································································· 10 MD Board ·································································· 10 Base Unit Section ······················································· 11 BUM-F1 Board ·························································· 11 REC/PB Head Assy (HR901) Section ······················ 12 Holder Assy, Cartridge Section ·································· 12 Holder Assy, Cartridge Installation ···························· 13 Optical Pick-Up (KMS-250A) Section ······················ 13 5-10. 5-11. 5-12. 5-13. 5-14. 5-15. 5-16. 5-17. 5-18. 5-19. 5-20. 5-21. Schematic Diagram Main Section (1/11) ················· 40 Schematic Diagram Main Section (2/11) ················· 41 Schematic Diagram Main Section (3/11) ················· 42 Schematic Diagram Main Section (4/11) ················· 43 Schematic Diagram Main Section (5/11) ················· 44 Schematic Diagram Main Section (6/11) ················· 45 Schematic Diagram Main Section (7/11) ················· 46 Schematic Diagram Main Section (8/11) ················· 47 Schematic Diagram Main Section (9/11) ················· 48 Schematic Diagram Main Section (10/11) ··············· 49 Schematic Diagram Main Section (11/11) ··············· 50 Printed Wiring Board Main Section ························· 51 Main Section (1/4) ····················································· 52 Main Section (2/4) ····················································· 53 Main Section (3/4) ····················································· 54 Main Section (4/4) ····················································· 55 Schematic Diagram Audio Section ·························· 56 Printed Wiring Board Audio Section ························ 57 Schematic Diagram Level Meter Section ················· 58 Printed Wiring Board Level Meter Section ·············· 59 Schematic Diagram LCD Section ···························· 60 Printed Wiring Board LCD Section ························· 61 Schematic Diagram Switch Section ························· 62 Printed Wiring Board Switch Section ······················ 63 Schematic Diagram Foot Switch Section ················· 64 Printed Wiring Board Foot Switch Section ·············· 65 IC Pin Function Description ······································ 66 IC Block Diagrams ····················································· 69
3. TEST MODE ···································································· 14 4. ELECTRICAL ADJUSTMENTS ······························· 26 5. DIAGRAMS
5-1. Circuit Boards Location ············································· 27 5-2. Block Diagrams ·························································· 28 MD Section ································································ 28 I/O Section ································································· 29 FIFO Section ······························································ 30 CPU Section ······························································· 31 LCD Section ······························································· 32 5-3. Printed Wiring Board MD Section ··························· 33 5-4. Schematic Diagram MD Section (1/4) ····················· 34 5-5. Schematic Diagram MD Section (2/4) ····················· 35 5-6. Schematic Diagram MD Section (3/4) ····················· 36 5-7. Schematic Diagram MD Section (4/4) ····················· 37 5-8. Schematic Diagram BUM Section ··························· 38 5-9. Printed Wiring Board BUM Section ························ 39
5-22. 5-23. 5-24. 5-25. 5-26. 5-27. 5-28. 5-29. 5-30. 5-31. 5-32. 5-37.
6. EXPLODED VIEWS
6-1. 6-2. 6-3. 6-4. Cabinet Section ·························································· 76 Key Section ································································ 77 LCD Section ······························································· 78 MD Mechanism Section (CCMD-2000) ···················· 79
7. ELECTRICAL PARTS LIST ······································· 80
NOTES ON HANDLING THE OPTICAL PICK-UP BLOCK OR BASE UNIT The laser diode in the optical pick-up block may suffer electrostatic break-down because of the potential difference generated by the charged electrostatic load, etc. on clothing and the human body. During repair, pay attention to electrostatic break-down and also use the procedure in the printed matter which is included in the repair parts. The flexible board is easily damaged and should be handled with care. NOTES ON LASER DIODE EMISSION CHECK Never look into the laser diode emission from right above when checking it for adjustment. It is feared that you will lose your sight.
Flexible Circuit Board Repairing · Keep the temperature of the soldering iron around 270°C during repairing. · Do not touch the soldering iron on the same conductor of the circuit board (within 3 times). · Be careful not to apply force on the conductor when soldering or unsoldering. Notes on chip component replacement · Never reuse a disconnected chip component. · Notice that the minus side of a tantalum capacitor may be damaged by heat.
SAFETY-RELATED COMPONENT WARNING!! COMPONENTS IDENTIFIED BY MARK ! OR DOTTED LINE WITH MARK !ON THE SCHEMATIC DIAGRAMS AND IN THE PARTS LIST ARE CRITICAL TO SAFE OPERATION. REPLACE THESE COMPONENTS WITH SONY PARTS WHOSE PART NUMBERS APPEAR AS SHOWN IN THIS MANUAL OR IN SUPPLEMENTS PUBLISHED BY SONY.
CAUTION Use of controls or adjustments or performance of procedures other than those specified herein may result in hazardous radiation exposure.
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MDCT-1000
Unleaded solder Boards requiring use of unleaded solder are printed with the leadfree mark (LF) indicating the solder contains no lead. (Caution: Some printed circuit boards may not come printed with the lead free mark due to their particular size.)
: LEAD FREE MARK Unleaded solder has the following characteristics. · Unleaded solder melts at a temperature about 40°C higher than ordinary solder. Ordinary soldering irons can be used but the iron tip has to be applied to the solder joint for a slightly longer time. Soldering irons using a temperature regulator should be set to about 350°C. Caution: The printed pattern (copper foil) may peel away if the heated tip is applied for too long, so be careful! · Strong viscosity Unleaded solder is more viscous (sticky, less prone to flow) than ordinary solder so use caution not to let solder bridges occur such as on IC pins, etc. · Usable with ordinary solder It is best to use only unleaded solder but unleaded solder may also be added to ordinary solder.
3
MDCT-1000 SECTION 1 GENERAL
This section is extracted from instruction manual.
Location and Function of Controls
For details, refer to the pages indicated in ( ).
1 2 3 4 5 6 7 8
LCD display Built-in speaker MONITOR VOL control LCD CONTRAST control Adjusts the contrast of the display. MONITOR select buttons (ALL/1/2/3/4) (8) STANDBY switch MD insertion slot Z EJECT button
9 FUNCTION button q; DISP MODE button (10) qa Arrow buttons qs ENTER button qd Jog dial qf x STOP button qg m REW/BS button qh u PLAY/PAUSE button qj M FF/FS button
Left side
qk CONTROL UNIT connector (11) ql EAR jack (8)
Rear w; DC IN 12V jack (7)
4
MDCT-1000
Display Window (Information screen)
1
2 3 4 5 6 7 8
1 Status display (17) Indicates the disc inserted in or the status of deck as follows: BLANK: a blank disc NO DISC: no disc PB ONLY: a commercially available recorded disc (for playback only) PROTECTED: a protected disc RECORDED: a recorded disc 2 TIME display Indicates the recorded time at the current location for each index item. 3 (copied) display Indicates that a disc digitally copied on MDCC2000 is inserted.
4 INDEX counter Lights up when a disc is inserted. Blinks during an index search. (9) 5 END display This shows the end of the disc. 6 Disc status display Indicates the status of the disc with pictures. 7 Message display Indicates various data by characters and various error messages. (17) 8 Disc position display Indicates the current playback location on the disc by a white box. Already recorded parts are indicated in black. The further it is to the right, the closer the disc is to the end. Depending on the condition of the disc, the black part might not reach the far right even if the disc is full.
5
MDCT-1000 SECTION 2 DISASSEMBLY
· The equipment can be removed using the following procedure.
Set Cabinet (upper) section Switch section LCD section
· Disassemble the unit in the order as shown below.
MD section Main board Volume section Door MD board
Base unit section
BUM-F1 board
REC/PB head assy (HR901) section
Holder assy, cartridge section
Holder assy, cartridge installation
Optical pick-up (KMS-250A) section
Note : Follow the disassembly procedure in the numerical order given.
2-1. CABINET(UPPER) SECTION
Cabinet (upper) assy
3 Four claws 4 Connector (CN9102)
2 Three screws (+PSW4 × 16)
1 Two screws (+PSW4 × 16)
6
MDCT-1000
2-2. SWITCH SECTION
2 Seven screws (+PS 3 × 6) 3 Key switch block assy
7 SWITCH board 5 Seven screws (STEP M2)
6 Five screws (+PSW 3 × 6)
1 Cable, flexible flat (90mm)
4 Eight screws (STEP M2)
2-3. LCD SECTION
2 Plate (LCD), transparent 1 Four screws (+PS 2 × 8)
qd Connector (CN4002) 5 Holder (LCD)
9 Three screws (+PS 3 × 6)
4 Claws 3 Cable, flexible flat (70mm) 0 Four screws (+PSW 3 × 6) 7 6 LCD qa LCD bracket qf LCD board
qs Connector (CN4001)
8 Light unit, back
7
MDCT-1000
2-4. MD SECTION
5 Connector(CN9101) 3 Three screws (+PS 3 × 6) 1 Cable, flexible flat (295mm) 2 Screw (+PS 3 × 6)
6 Two screws (+PSW 3 × 8) 7 AUDIO I/O board
4 MD mechanism
2-5. VOLUME SECTION
5 Knob(VOL) 6 Two nuts 7 Spacer 9 Two screws (+PS 3 × 6) 4 Level meter bracket 2 Connector (CN9202) 8 VOLUME board qg Screws (+PSW 3 × 8) qd Connector (CN9001) qs Connector (CN8001) qf Two screws (+PSW 3 × 6) qa LEVEL METER board 0 Screw (+PSW 3 × 6) 1 Connector(CN6002) 3 Three screws (+PS 3 × 6)
qh FOOT SWITCH board
8
MDCT-1000
2-6. MAIN BOARD
6 MAIN board
5 Four screws (+PSW 3 × 6) 2 3 Connector(CN111) 4 Cable, flexible flat (295mm)
1
Cabinet (lower)
9
MDCT-1000
2-7. DOOR
spring, door return
3 Door
1 Release the hook.
2 Release the boss.
2-8. MD BOARD
6 MD board 5 Two screws (M 2 × 3) 4 Two screws (M 2 × 3)
1 Flexible wire (18 core, CN5)
3 Flexible board (CN1)
2 Flexible board (CN3)
10
MDCT-1000
2-9. BASE UNIT SECTION
3 Two screws (step)
5 Base unit 4 Two screws (step)
1 Screw (toothed lock M 2 × 3.5) 2 Lug, 2
2-10. BUM-F1 BOARD
4 Two screws (precision +M 1.7 × 2.2) 7 BUM-F1 board 6 Claw 5 Claw
3 Flexible board (CN302) 2 Flexible board (CN304)
1 Plam flexible board (CN303)
11
MDCT-1000
2-11. REC/PB HEAD ASSY (HR901) SECTION
4 Screw (toothed lock M 1.4) 5 Guide, screw 6 Two screws (M 1.7 × 2.8) 2 Lug, 2
1 Screw (toothed lock M 2 × 3.5)
3 Motor, DC geared (M903) 8 REC/PB head assy (HR901)
7 Removed hook
2-12. HOLDER ASSY, CARTRIDGE SECTION
2 While releasing the four bosses, remove the cartridge holder assembly in the direction of the arrow C.
1 Push it in the direction of the arrows A and B with fingers.
Boss
A
B
Boss
Boss
C
Boss
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MDCT-1000
2-13. HOLDER ASSY, CARTRIDGE INSTALLATION
When installing the cartridge holder, coat the portion A shown in the illustration with grease (EM-30L).
A Position
A Position
A Position
2-14. OPTICAL PICK-UP (KMS-250A) SECTION
3 Two screws (Precision, +P 1.7 × 2.2)
5 Two screws (M 1.7 × 4.5)
6 Two washers
4 Spring, guide shaft retainer
2 Motor, stepping (M902) 7 Optical pick-up (KMS-250A)
1 Two screws (Precision, +P 1.7 × 2.2)
13
MDCT-1000 SECTION 3 TEST MODE
NOTE
This machine does not have either DECK B nor the recording function. 3-1-5. Test Display
01 - 00 00 - 00 01 - 00 02 - 00 03 - 00 04 - 00 05 - 00 06 - 00 07 - 00 08 - 00 09 - 00 EXIT THIS MENU AUDIO MECH DISPLAY KEY COMMUNICATION AUDIO HW DIGITAL HW NVRAM (Top menu) (Exit) (Top menu) (Audio firmware test) (Mechanism test) (Display system test) (Key test) (Communication test) (Audio hardware test) (Digital hardware test) (NVRAM test)
3-1. Description
3-1-1. How to Enter the Test Mode Pressing the G G ENTER g g g g g ENTER G G ENTER F buttons. 3-1-2. How to Exit the Test Mode While pressing the G button, rotate the JOG dial and set "k_test_h" to "0". 3-1-3. How to Cancel the ENTER key The numeric keys that have been input up to the moment can be canceled at the following so that the machine does not enter the test mode unless otherwise needed. 1. When the interval of pressing the previous numeric key and the next key exceeds one second or more. 2. When the deck select key is pressed. 3. When the k_mode changes. 4. When the selected deck has changed. 5. When the test mode is set. 3-1-4. How to Select the Test Item The test item can be selected by "k_test_h" and "k_test_l". 1. Displaying the selected item The selected item is displayed on LCD as follows.
Value of "k_test_h" (Displayed in hexadecimal number) Value of "k_test_l" (Displayed in hexadecimal number) 05 - 01 /* KEY INCREMENT TEST */
3-1-6. Communication with Mechanism Deck Communication with the mechanism deck is performed using programs such as "Hyper terminal" or the like that have been started up on a PC. Refer to 3-3-3. "Selecting the Terminal". (Communication control with the log system or trace monitor is not possible.) 3-1-7. Circuit Block
General purpose port
KEY
NVRAM
CLOCK
CPU CPU bus
ROM
SRAM
DRAM
1809
8655
FIFO
LCD
DECK A
CODEC
AD/DA
2. How to select the test item using the JOG dial 1. While pressing G button, rotate the JOG dial. "k_test_h" changes. When "k_test_h" changes, "k_test_l" is set to "0". Select the desired test category using "k_test_h". 2. While pressing g button, rotate the JOG dial. "k_test_l" changes. Select the desired test item using "k_test_l". 3. Sets the selected test item either by pressing g button after selecting "k_test_l" or by pressing the ENTER button. 3. How to select the test item with the use of the PC remote command The desired test item can be selected by sending the remote command of rewriting "k_test_h" and "k_test_l" from the PC to the machine. When the "k_test_h/l" change command is sent from a PC to the machine while the "k_test_h/l" change inhit bit is being set, the machine returns NAK and the machine does not chanage "k_test_h/l".
3-2. Audio Firmware Test: [AUDIO]
SF data storage method in the DRAM. · Test program is stored as shown below. (Operations start in the order starting from channel 1, channel 2, channel 3, and up to channel 4 under the ordinary operation conditions but the test mode starts from channel 1, channel 3, channel 2, and channel 4 in this order.)
0 SF 1ch 1 3ch 2 2ch 3 4ch
FIF012 FIF034
CXD1858 1.2ch CXD1858 3.4ch
LCD: Types, conditions and others of the test are displayed on the LCD during each test. Channel selector and channel selector LED: Select the channel selector by manual operation. Voice mirror: Change the input level by manual operation. · Perform the following tests after the machine is set in the "STOP" mode.
02-00 /* AUDIO-F TEST MENU */ 02-00 AUDIO-F MENU
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MDCT-1000
3-2-1. Audio Recording and Playback Test without Disc · The audio signal (up to the full memory capacity of the DRAM at a maximum) is recorded in the ATRAC data recording area in the DRAM and is played back. · Note: If the audio sources of channel 1 to channel 4 are all the same, · Playback is slower than normal if the 4 channels are recorded and 2 channels are played back. (The pitch of the playback remains unchanged and the playback speed of it is half of normal.) · Playback is faster than normal if the 2 channels are recorded and 4 channels are played back. (The pitch of the playback remains unchanged and the speed of it is double of normal.)
02-01 4ch-REC 02-02 4ch-PLAY 02-03 2ch-REC 02-04 2ch-PLAY 02-05 reserve 02-06 reserve on DRAM on DRAM on DRAM on DRAM
3-2-5. Audio Muting Test · ROM_PB (990Hz, -0.2dB, 1 to 4ch)
02-19 02-1A 02-1B 02-1C 02-1D 02-1E 02-1F 02-20 XMUTE=on, MODE=00, (During ROM_PB, circuit playback + mute) XMUTE=on, MODE=01, (During ROM_PB, circuit recording + mute) XMUTE=on, MODE=10, (During ROM_PB, circuit STOP + mute) XMUTE=on, MODE=11, (During ROM_PB, circuit STANDBY + mute) XMUTE=off, MODE=00, (During ROM_PB, circuit is in playback.) XMUTE=off, MODE=01, (During ROM_PB, circuit is in record.) XMUTE=off, MODE=10, (During ROM_PB, circuit is STOP.) XMUTE=off, MODE=11, (During ROM_PB, circuit is STANDBY.)
3-3. Mechanism Deck: [MECH]
03-00 /* MD TEST MENU */ 01-0E 10-1F 20-2F 30-3F 40-4F 50-57 .....etc DECK-A Only DECK-B Only DECK-A Only DECK-B Only Laser Check (Check & Setting) (Check & Setting) (Display Log) (Display Log)
3-2-2. Microphone Sound Monitoring from Speaker during Stop · Application: For testing "ripping" sound of speaker (Sweep sound is input from external source.) · Application: For testing the voice mirror LED (sound is input from external source.)
02-07 REC_MONI, SP, 1-4ch
3-3-1. Displaying the Number of Times of Using the Lasers The number of times of using the lasers of the deck-A and deckB is displayed. The number of times of using the lasers is stored in the NVRAM, and the number of times that the laser power has entered the MO write (number of clusters), is displayed.
03-01 DECK-A Laser Cnt = xxxxxxxx DECK-B Laser Cnt = xxxxxxxx
3-2-3. ROM Playback 1 · The pseudo ATRAC data on the EPROM is copied to the 1SG area on the DRAM and is played back repeatedly. · Application: Level/Frequency response test
02-08 02-09 02-0A 02-0B 02-0C 990Hz, -0.2db, 43Hz, 990Hz, Infinity, -0.2db, -12db, 0, 10KHz, -0.2db, 1-4ch (For playback of the reference level) 1-4ch 1-4ch 1-4ch 1-4ch (For S/N test)
3-3-2. Displaying Temperature of Mechanism The temperatures of the mechanism of deck-A and deck-B are displayed. The temperature of mechanism indicates the temperature inside the RF amplifier mounted on this machine. However, use this temperature as a reference value because it is not highly accurate.
03-02 Thermo DECK-A 35°C [Result] = [55] [0B] [58] [62] [07] [09] [09] DECK-B 31°C
3-2-4. ROM Playback 2 · The pseudo ATRAC data on the EPROM is copied to the 1SG area on the DRAM and is played back repeatedly. · Application: Separation/Frequency response test · Other channels : No sound
02-0D 02-0E 02-0F 02-10 02-11 02-12 02-13 02-14 02-15 02-16 02-17 02-18 990Hz, -0.2db, 990Hz, -0.2db, 990Hz, -0.2db, 990Hz, -0.2db, 43Hz, 43Hz, 43Hz, 43Hz, 10Hz, 10Hz, 10Hz, -0.2db, -0.2db, -0.2db, -0.2db, -0.2db, -0.2db, -0.2db, 1ch 2ch 3ch 4ch 1ch 2ch 3ch 4ch 1ch 2ch 3ch 4ch
[Result] = [55] [0B] [58] [5F] [06] [06] [06]
3rd byte of the above [Result] data string : Initial value of the temperature sensor at 25°C 4th byte of the above [Result] data string : Present temperature sensor value 3-3-3. Selecting the Terminal Select the PC terminals (RS-232C) on the rear of this machine. Either one of the two patterns "Other" and "Mech", can be selected. Other : For checking contents, etc of the system memory Mech : For checking status of the mechanism operation
03-0A Terminal Mode = Mech
10KHz, -0.2db,
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MDCT-1000
The PC should use the terminal software (such as Hyper-Terminal or Tera-Term). Sets the communication as follows. Baud rate : 9600 bps Data length : 8 bits Parity : None Stop bit :1 Flow control : None 3-3-4. Dump List Displays the Dump-List of the specified address. Sets the address value (Adrr) and number (Num) of display bytes by rotating the JOG dial and pressing ENTER button.
03-0D Adrr = 00000000 Num = 00
When the "Mech" position of the terminal is selected, the test status can be checked as follows. Description of the contents displaying the test status Example of display
$$ TEST-drv [CNT] (W/R/D/S) (TW/TR) (Result)
3-3-5. Deleting (Deck-A/Deck-B) Performs deletion of the disc data.
03-14 03-24 (DECK-A) (DECK-B)
3-3-6. OA (Inner track, Middle track and Outer track) (Deck-A/ Deck-B) Performs the OA (overall) test against the inner track (UTOC area)/Middle track/Outermost track. Performs "Write", "Read", and "Verify" for every 1 cluster as many as 10 clusters in each area.
03-15 03-25 (DECK-A) (DECK-B)
drv : Drive No. CNT : Number of times of test W : Number of times of "Write" error Number of times of the write failure for the single write command ("Seek" error is not included.) R : Number of times of "Read" error Number of times of the read failure for the single read command ("Seek" error is not included.) D : Number of times of alternation Number of times of giving-up to write into the specified cluster S : Number of times of "Seek" error Number of times that "Seek" error has occurred TW : Number of times of TOC "Write" error Number of times of the TOC write failure for the single TOC "Write" command ("Seek" error is no included.) TR : Number of times of TOC "Read" error Number of times of the TOC read failure for the single TOC "Read" command ("Seek" error is no included.) Result : Test result up to present (1 : OK, 0 : NG) Result display When the OA test has ended with success, the following message appears on the LCD.
***Total OK***
Result display When the OA test of each area has ended with success, the following message appears on the LCD.
***Total OK***
3-3-8. Checking Operations of Mechanism (Deck-A/Deck-B) Operations of the mechanism are checked using the terminal.
03-17 03-27 (DECK-A) (DECK-B)
· After the above message appears with normal end, the disc is ejected automatically. 3-3-7. OA (Overall Test for Normal Recording ) (Deck-A/Deck-B) The OA test in the same operation as the normal recording is performed. The process of "Write", "Read" and "Verify" is performed for every 1 cluster starting from the innermost track of the recording area to the outermost track. Then the "UTOC Write" is performed for every 10 clusters.
03-16 03-26 (DECK-A) (DECK-B)
Mechanism test
Prompt
Dedicated for mechanism
:MON> y Waiting for mdmon n Waiting for exit y >> Waiting for command n y Waiting for ' . '
n
Operation step Step 1 : Enters the test mode of the mechanism. Step 2 : Type in "mdmon" against "MON>" and set it. Step 3 : Press the ENTER button several times until the machine enters the test mode dedicated for mechanism. Step 4 : Performs the operation check in accordance with the display output. Step 5 : Type in "." to return to "Prompt". Step 6 : Type in "exit" to set the operation and exit the test mode of the mechanism.
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MDCT-1000
3-3-9. Eject (Deck-A/Deck-B) Ejects the disc.
03-18 03-28 (DECK-A) (DECK-B)
3-3-12. Rescue (2-channel Mode) (Deck-A/Deck-B) When the UTOC information shows error, the disc can be recovered as follows.
03-1E 03-2E (DECK-A) (DECK-B) DECK-A Rescue 2Ch Mode Disc-Input!!
3-3-10. Clearing the Number of Times of Using the Laser (Deck-A/Deck-B) The number of times of using the laser is stored, and is cleared as follows. It is necessary to clear the number of times data of using the laser whenever the laser is replaced.
03-19 03-29 (DECK-A) (DECK-B) DECK-B Laser Count Clear NV-RAM Save OK
Result display Index structure
: Only 1 index is used over the entire area of a disc. Recording mode : 2-channel mode Original : Original Name information : Invalid Time information : Invalid
3-3-11. OA (Overall Test for Random Recording ) (Deck-A/Deck-B) The (OA) overall test is performed using the same operation as that of the normal recording. The "write", "read", and "verify" are performed at every cluster at random within the recording area. The "UTOC write" is performed at every ten clusters. The test ends after the specified time has passed. When the "Mech" position of the terminal is selected, the test status can be checked as follows. Description of the contents displaying the test status Example of display
$$ TEST-drv [CNT] (W/R/D/S) (TW/TR) (Result)
3-3-13. Rescue (4-channel Mode) (Deck-A/Deck-B) When the UTOC information shows error, the disc can be recovered as follows.
03-1F 03-2F (DECK-A) (DECK-B) DECK-A Rescue 4Ch Mode Disc-Input!!
Contents of recovery Index structure : Only 1 index is used over the entire area of a disc. Recording mode : 4-channel mode Original : Original Name information : Invalid Time information : Invalid 3-3-14. Laser Power OFF (Deck-A/Deck-B) Turns off the laser power.
03-50 (DECK-A) [Result] = [01] [1D] [00] [00] [00] [00] [00] 03-54 (DECK-B) [Result] = [01] [1D] [00] [00] [00] [00] [00]
drv : Drive No. CNT : Number of times of test W : Number of times of "Write" error Number of times of the write failure for the single write command ("Seek" error is not included.) R : Number of times of "Read" error Number of times of the read failure for the single read command ("Seek" error is not included.) D : Number of times of alternation Number of times of giving-up to write into the specified cluster S : Number of times of "Seek" error Number of times that "Seek" error has occurred TW : Number of times of TOC "Write" error Number of times of the TOC write failure for the single TOC "Write" command ("Seek" error is no included.) TR : Number of times of TOC "Read" error Number of times of the TOC read failure for the single TOC "Read" command ("Seek" error is no included.) Result : Test result up to present (1 : OK, 0 : NG) Result display When the OA test has ended with success, the following message appears on the LCD.
***Total OK***
Laser Power (DECK-A) = OFF
Laser Power (DECK-B) = OFF
3-3-15. Laser Power MO-WRITE (Deck-A/Deck-B) Sets the laser power to the "MO-WRITE".
03-51 (DECK-A) [Result] = [01] [1D] [00] [18] [00] [01] [00] 03-55 (DECK-B) [Result] = [01] [1D] [00] [18] [00] [01] [00]
Laser Power (DECK-A) = MO-WRITE
Laser Power (DECK-B) = MO-WRITE
3-3-16. Laser Power CD-READ (Deck-A/Deck-B) Sets the laser power to the "CD-READ".
03-52 (DECK-A) [Result] = [01] [1D] [00] [08] [00] [02] [00] 03-56 (DECK-B) [Result] = [01] [1D] [00] [08] [00] [02] [00]
Laser Power (DECK-A) = CD READ
Laser Power (DECK-B) = CD READ
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MDCT-1000
3-3-17. Laser Power MO-READ (Deck-A/Deck-B) Sets the laser power to the "MO-READ".
03-53 (DECK-A) [Result] = [01] [1D] [00] [08] [00] [03] [00] 03-57 (DECK-B)
· Connecting the LCD Controller with SRAM
LCD controller VA15 VA14 VA13 Buff AND 2 AND 1 3
Laser Power (DECK-A) = MO READ
Laser Power (DECK-B) = MO READ [Result] = [01] [1D] [00] [08] [00] [03] [00]
VA12
3-4. Display System Test: [DISPLAY]
AND OR [SRAM] VWR VRD
VCE
04-00 04-01
/* DISPLAY TEST MENU */ [LCD_cntr] - [u_com] : connection check [LCD_cntr] - [h_sram] : connection check [LCD_cntr] - [LCD] : connection check
04-02 04-03 04-04 04-05 04-06 04-07
LCD DOT all set LCD DOT all clear character check on h_sram (SAG1) [1] character check on h_sram (SAG1) [2] [u_com - [LCD_cntr] : test signal transmission of character data
VA14 VA13 VA12 VA11 VA10 VA9 VA8 VA7 VA6 VA5 VA4 VA3 VA2 VA1 VA0
· 1st layer (Character screen) 0 (0000h) to 9999 (270Fh) · 2nd layer (Graphic screen) 10000 (2710h) to 19999 (4E1Fh) · SAG1 (Character storage) 61440 (F000h) to (FFFFh)
04-08... content of global_area_address
· Connecting the Microprocessor with LCD Controller
Microprocessor AO XRD XHWR XCS4 16MHz D15 D14 D13 D12 D11 D10 D9 D8 XRES XRES Divide-by-2 LCD controller AO XRD XWR XCS 8MHz
D7 D6 D5 D4 D3 D2 D1 D0
ADDRESS 0000 to 6FFF 7000 to EFFF F000 to FFFF
1 2 3 H H L L L H H H L
Reset IC
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MDCT-1000
· Connecting the LCD Controller with LCD
LCD controller WF LP XSCL YDIS CP YD AND FRAME LP DELAY LCD DF
3-4-2. LCD Dot Check (Lighting All Dots) Lighting all dots of LCD (Graphic data: By 0xff transfer)
04-02
LOAD
3-4-3. Checking the LCD Dot (Turning off all dots) All dots of LCD are turned off. (Graphic data : By 0x00 transfer)
04-03
D0 D1 D2 D3
3-4-4. Test Signal Output from Microprocessor to LCD Controller Test signal output is under preparation.
04-06 NOW test signal loading...
XRES OR
DISP
Test signal is under preparation. 0xff and 0x00 are output repeatedly to the microprocessor ports D15 to D8 as follows.
Reset IC PA4 (Microprocessor)
3-4-1. Connection Check between Microprocessor and LCD Controller, and between LCD Controller and SRAM · Check the checksum of the font and the graphic data that are transferred to SAG1 (F000h to FFFFh) of the SRAM for display when releasing the STANDBY mode.
[Calculation is under way.] 04-01 (data read from LCD cntr) = ????????
About 0.25 S 0.25
0.25
0.25 About 30 seconds
The test signal output ends.
04-06 finished test signal output
3-5. Key Test: [KEY]
05-00 /* KEY TEST MANU */ 05-01 05-02 05-03 KEY INCREMENT TEST ANY KEY TEST K_mode LOG
· When [OK] appears: Connection between the microprocessor and LCD controller and the connection between LCD controller and SRAM are correct.
04-01 (data read from LCD cntr) = xxxxxxxx [OK]
3-5-1. Key Test by Pressing Keys in Order
05-01 /* KEY INCREMENT TEST */ Turn ON DISPLAY(A)
· When [NG] appears: 1. If the following *NG display is recognized, "XRD" is suspected. 2. If the following *NG display is not recognized (upon confirmation through trace monitor), either one of the connections between microprocessor and LCD controller or the connection between LCD controller and SRAM or the connection between LCD controller and LCD is defective. (At this time, if the test signal is output from the microprocessor to LCD controller in step 04-06, whether the connection is OK or NG can be confirmed, and also which of the connections between LCD controller and SRAM or the connection between LCD controller and LCD is NG.)
04-01 (data read from LCD cntr) = KKKKKKKK [NG] Mabye read pattern NG. or. [LCD_cntr]-[u_com],[h_sram]: connect NG
When the specified "DISPLAY (A)" key is pressed correctly, the following messages appear.
05-10 /* KEY INCREMENT TEST */ DISPLAY(A) OK Turn OFF
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MDCT-1000
When releasing your finger from the key, the next key to be pressed is specified. When an incorrect key that is different from the specified one is pressed, following messages appear.
05-10 /* KEY INCREMENT TEST */ DISPLAY(A) NG Turn OFF
Allocation of key groups and keys
Application Type Group 0 1 2 3 4 5 6 7 8 9 10 Foot switch operation ANALOG 0 FS_PLAY FS_FS FS_BS
The test cannot be advanced unless the correct key is pressed. The "Key Test by Pressing Keys in Order" is complete. (Normally end)
When all of the key pressings are correct, "COMPLETE" appears on the LCD screen and type in 05-42.
Allocation of Kn
Application Type Group 0 1 2 3 4 5 6 7 8 9 10
Operation of the Operation of the Operation of the mechanism mechanism mechanism ANALOG 1 STOP(A) STOP(B) PLAY/PAUSE(A) REW/REV(A) FF/CUE(A) MARK(A) MARK_OFF(A) ANALOG 2 REC(A) REC(B) PLAY/PAUSE(B) REW/REV(B) FF/CUE(B) MARK(B) MARK_OFF(B) ANALOG 3 INDEX EJECT(A) EJECT(B) DECK_A DECK_B SEARCH 0 1 2 3 4 5 6 7 8 9 10
Search ANALOG 4
(Abnormally end)
When the incorrect key is pressed more than once, "xxxxx at FAULT" appears on the LCD screen. An incorrect key that was detected at first in the order of pressing keys, is displayed in "xxxxx".
3-5-2. Key Test by Pressing Arbitrary Key
05-02 /* KEY TEST */ PUSH KEY AD CODE TRANSCRIBE SEARCH MODE : : : : OFF (FF/F5-FF) FF FF FF FF FF FF FF A POW : ON INDEX JOG : 00
Allocation of Kn
Application Type
Function ANALOG 5 FUNCTION f F DEL <(LEFT) >(RIGHT)
Function ANALOG 6
Function ANALOG 7
Power supply, etc. DIGITAL 8 Use is prohibited Use is prohibited A/B(FS) INDEX/TIME STANDBY/ON
Displays the name of the pressed key. Example : When the STOP button of the deck-A is pressed,
05-05 PUSH KEY : STOP (A) (00/00-09)
Group 0 1 2 3 4 5 6 7 8 9 10
appears. The first 2-digit "00" of (00/00-09) indicate the value that the pressed key after it is converted by AD converter. The digits "0009" indicate the range when the key is judged as "STOP (A)". AD CODE Displays values when the key inputs are converted by AD converter, in the order starting from 0 up to 7 from the left of the LCD screen.
05-05
Group 0 AD CODE : FF FF FF FF FF FF FF Group 7
20
Allocation of Kn
REC_PAUSE ENTER DISP_MODE(A) DISP_MODE(B)
MDCT-1000
3-6. Communication Test: [COMMUNICATION]
· RS232-C connector When the pin-2 and pin-3 of the RS232-C connectors are connected, two values are displayed in the 2-digit hexadecimal values respectively on the LCD screen, one is the send data and the other is data that have been received by the loop-back. Display example
Tx DATA Rx DATA 57 57 Send data. Received data.
3-8. Digital Hardware System Test: [DIGITLAL HW]
· Performs the menu display of the digital system test items. · SRAM test Write/read test of the SRAM area is performed at the startup when the main power is turned on. 0x5555, 0xAAAA and 0x0000 are used as the write data. After completion of the writing the respective data, the data are read-out and are collated. The test area is 0x200000 to 0x207FFF in the area 1. When an error occurs during reading and collating, the REC LED on the deck-A will blink permanently. (The REC LED on the deck-A is connected to the pin-11 (PC0) of the IC1077 HD64003TF16. · DRAM test Write/read test of the DRAM area is performed at the startup when the main power is turned on. 0x5555, 0xAAAA and 0x0000 are used as the write data. After completion of the writing the respective data, the data are read-out and are collated. The test area is 0x600000 to 0x7FFFFF in the area 3. The test is performed at every 257 bytes. When an error occurs during reading and collating, the REC LED on the deck-B will blink permanently. (The REC LED on the deck-B is connected to the pin-12 (PC1) of the IC1077 HD64003TF16.) 3-8-1. The Menu Display
08-01 /* DIGITAL HW TEST */ 08-01 08-02 08-03 08-04 08-05 08-06 08-07 08-08 08-09 08-0A 08-0B 08-0C THIS MENU ROM VERSION & DATE ROM CHECK SUM JOG INPUT PULSE 10 mSEC CXD-8655 WRITE/READ CLOCK IC CLOCK IC (power on) LED ON/OFF NMI MODEL LOCAL
The value of the received data follows a little bit delayed after the send data. The send data increments at every about 0.5 seconds. · Modular jack When pin-2 and pin-3 of the modular jack are connected to pin3 of the RS232-C connector, the same test can be done. · Communication packet The status packet is used. Packet size = 38 bytes
06-00 /* PC_I/F LOOP BACK */ Tx DATA = xx Rx DATA = xx
3-7. Audio Hardware Test: [AUDIO HW]
· The following test should be performed while the machine is set in the "STOP" mode.
07-00 /* AUDIO-H TEST MENU */ 07-00 AUDIO-H MENU
07-01 RESERVE
3-7-1. Testing the Alarm Sound
07-02 07-03 07-04 07-05 07-06 07-07 07-08 07-09 XMUTE=on, MODE=00 XMUTE=on, MODE=01 XMUTE=on, MODE=10 XMUTE=on, MODE=11 XMUTE=off, MODE=00 XMUTE=off, MODE=01 XMUTE=off, MODE=10 XMUTE=off, MODE=11 (During alarm, circuit playback + mute) (During alarm, circuit recording + mute) (During alarm, circuit STOP + mute) (During alarm, circuit STANDBY + mute) (During alarm, circuit is in playback.) (During alarm, circuit is in record.) (During alarm, circuit is STOP) (During alarm, circuit is STANDBY)
3-8-2. ROM Version Displays the release version of the programmed ROM.
08-02 /* ROM VERSION & DATE */ ROM: Ver No.0017 DECK A ROM : V 2.33 DECK B ROM : V 2.33 DATE: 2001.02.21
3-7-2. Testing LED
07-0A LED=4ch, LED=on 07-0B LED=2ch, LED=off
3-7-3. Stopping FINT Information
07-0C FINT INFORMATION
3-8-3. Check Sum of the ROM Checksum of the programmed ROM is calculated. The checksum area is 0x00000 to 0x07FFFF in the area 0. Displays the address under calculation in hexadecimal number.
08-03 /* ROM CHECK SUM */ CHECK SUM = xxxx
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MDCT-1000
Displays the calculation result in the 2 bytes hexadecimal number. The result indicates the value which is the same as checksum calculated by the ROM writer.
08-FF /* ROM CHECK SUM */ CHECK SUM = 9375 COMPLETED
3-8-7. Watch IC Test I Displays the inside data of the watch IC and performs the error correction of the oscillation clock.
08-07 /* CLOCK DATA */ SECOND = 54 MINUTE = 37 OCLOCK = 14 WEEK DAY YEAR = 00 = 02 = 00 SET CORRECT (JOG & ENTER) 32769.500 - 32769.599 (10) CORRECT CRTL_1 CTRL_2 = 10 = 20 = 00
3-8-4. Entry by JOG Operation The input data of the JOG operation is sampled by 1 msec. cycle. When the input data agree twice continuously, the data are confirmed as the input data. The confirmed input data pass through the chattering processing. Then the resultant input data is displayed.
08-04 /* JOG INPUT */ JOG-1 = 1 JOG-2 = 0 or 1
MONTH = 91
"MONTH = 91" means a status that the 100-yaer bit is on. It becomes November by masking MSB. 1. Contents of displays
Items SECOND MINUTE OCLOCK WEEK Contents of display Displays the value of the "second" count register in 2-digit BCD. Displays the value of the "minute" count register in 2-digit BCD. Displays the value of the "hour" count register in 2-digit BCD using 24-hour display. Displays the value of the "week" count register in 2-digit hexadecimal number. No. 0 to No. 7 corresponds to Sunday through Saturday respectively. But, because this machine does not use the day of No. 7, the data is different from the actual day of the week. DAY MONTH Displays the value of the "date" count register in 2-digit hexadecimal number. Displays the value of the "month" count register in 2-digit hexadecimal number. The bit 7 is set to "1" when the "year" count register is capable up to 100 years. YEAR Displays the value of the "year" count register in 2-digit BCD.
Displays the input status of the pin-2 of the CPU in the JOG-1. Displays the input status of the pin-3 of the CPU in the JOG-2. The JOG-1 is the input at pin-2 (PB0) connector of the IC1077 HD64003TF16. The JOG-2 is the input at pin-3 (PB1) connector of the IC1077 HD64003TF16. 3-8-5. PULSE Output · Connection between the CXD-1809 and the CPU bus can be checked by this test.
08-05 /* PULSE 10mSEC */
The pulse for confirming the clock oscillation of the microprocessor is output. This pulse is output to pin-73 (RA03) terminal TP1058 of the IC1033 CXD-1809. The pulse width is 10 msec and the tolerance is less than 1/100.
10 mSEC 10 mSEC
Displays the value of the "CORRECT" error correction register in 2-digit hexadecimal number.
CRTL_1 Displays the value of the control register 1 in 2-digit hexadecimal number. Bit name 7 : WALE 6 : DALE 5 : 12 24 3 : TEST Used for Alarm control Alarm control 12-hours/24-hours clock IC test Setup value 0 = Alarm is invalid 0 = Alarm is invalid 1 = 24-hours clock 0 = Valid 0 = Normal operation mode 2 : CT2 1 : CT1 0 : CT0 Selecting the periodic interrupt 0 = OFF 0 = OFF 0 = OFF
4 : CLEN2 32 kHz output
3-8-6. Write/Read Test of CXD-8655 After writing 0x55 in the "Interrupt Timing Register" of the CXD8655 (IC1021), the value in the same register is read out and is checked whether the data is 0x55 or not.
08-06 /* CXD- 8 6 5 5 WR/RD */ WRITE/READ COMPLETE.
If value is the same, "WRITE/READ COMPLETE" appears. If value differs, "WRITE/READ ERROR!" appears.
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MDCT-1000
CRTL_2
Displays the value of the control register 2 in 2-digit hexadecimal number. Bit name 7 : VDSL 6 : VDET Used for voltage Result of power supply monitoring 5 : SCRATCH Scribble bit 4 : XSTP 3 : CLEN1 2 : CTFG 1 : WAFG 0 : DAFG Stops sending data 32 kHz output Fixed cycle interrupt output Alarm matches. Alarm matches. 0 = Does not match. 0 = Does not match. 0 = Normal send status 0 = Valid 0 = OFF 0 = More than monitoring voltage Setup value
Power supply monitoring 0 = 2.1V
3-8-8. Watch IC Test II (When power is turned on) The inside data of the watch IC before executing the backup battery run-out check is displayed at the moment of immediately after the power-on of the machine. Accordingly, the data before resetting the watch IC at the event of backup battery run-out check, etc can be confirmed.
08-08 /* CLOCK IC (Data just before power on) */ SECOND = 54 MINUTE = 37 OCLOCK = 14 WEEK DAY YEAR = 00 = 02 = 00 [OSCILLATOR [SECOND-YEAR DATA [BACKUP BATTERY : OK (CONTINUED) : LEGAL ] ] CORRECT CRTL_1 CTRL_2 = 10 = 20 = 00
MONTH = 91
: OK (MORE THAN 2.1V) ]
SET CORRECT 32768.500 to 32768.599 ( )
Indicates the method to set the correction value. Indicates the clock oscillation frequency range. Indicates the correction value in parenthesis ( ).
"MONTH = 91 becomes November by masking MSB in the status in which the 100-yaer bit is set to on. 1. Contents of displays The contents are the same as those of Section 3-8-7. "Watch IC Test I" except for the following.
Items Contents of displays : OK (CONTINUED) : NG (STOPED) ] When the oscillation stop is not detected. [OSCILLATOR ] When the oscillation stop is detected. ] When the data of second, minute, hour, date, month, and year are of the [SECOND-YEAR DATA : ILLEGAL possible values. ] When the data of second, minute, hour, date, month, and year are of the [BACKUP BATTERY [BACKUP BATTERY impossible values. : OK (MORE THAN 2.1V) ] When the backup battery is normal. : LESS THAN 2.1V ] When the backup battery has run out.
2. Error Correction Corrects an error of the clock oscillation frequency of the watch IC. 1. Pull up the clock output (TP1001) of the watch IC to the Vcc with a resistor (about 10 k). 2. Measure the clock oscillation frequency. The frequency counter which has the measurement accuracy of eight digits or more should be used. 3. Select the range of the oscillation frequency using the JOG dial. 4. Press the ENTER button. When the writing data into the watch IC and the storing data into the NVRAM are complete, "COMPLETE" appears. 5. When the ENTER button pressed once and then the hand removed from the ENTER button, the value that are set in "CORRECT=" is reflected and stored. (Note) In order to return the machine to the customer with the status in which the clock error correction value is being saved, select "SHIPPING" in the test mode of the NVRAM and press the ENTER button, or alternately exit the test mode and enter the STANDBY mode. In the latter method, be careful that the stamp information, password, reverse time, etc are not initialized. (If the NVRAM is initialized or the pattern write test is performed, the clock error correction value that is saved in the NVRAM, will also be initialized.)
[OSCILLATOR
[SECOND-YEAR DATA : LEGAL
3-8-9. LED ON/OFF The LEDs of the channel 3 and channel 4 of the monitor and those of LINE OUT, the deck-A and deck-B, and the REC button simultaneously blink.
08-09 /* LED ON/OFF */ 1. 3ch/4ch 2. DECK A/B 3. REC A/B
The period of blinking is 0.5 seconds for "on" and 0.5 seconds for "off".
0.5 SEC 0.5 SEC
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MDCT-1000
3-8-10. NMI Test When the NMI starts, "NMI ON" appears.
08-0A /* NMI */ NMI ON
3-9-1. Setup for Shipment of the Machine The data except the watch correction value and the number of times of use of the laser are initialized.
09-01 /* NVRAM INITIALIZE / CHECK */
"NMI OFF" appears about one second later.
08-0A /* NMI */ NMI OFF
Setting-up is under way. Setup for shipment of the machine is under way.
09-10 /* NVRAM SHIPPING */
Outputs the pulse to pin-73 (RA03) terminal TP1058 of the IC1033 CXD-1809. Pulse width is about 1 sec.
IC1002-8 PIN
Result (Normal completion) Display of completion of setup for shipment of the machine
09-FF /* NVRAM SHIPPING */ COMPLETE.
IC1007-72 PIN
CUT OFF POWER!
IC1033-72 PIN 1 SEC LCD display "NMI OFF" "NMI ON" "NMI OFF"
Shut off the power supply after this. (After completion of the test mode by setting k_test_h to 0x00, you may set the [STANDBY] mode.) (Abnormal completion) Display of the abnormal completion of the setup for shipment of the machine
09-10 /* NVRAM SHIP INITIALIZE */ ERROR. REPAIR HARDWARE!
3-9. NVRAM Test: [NVRAM]
After writing the word data (2 bytes) with 128 words to the evennumbered address from the address 0x00, write 128 words to the odd- numbered address from the address 0x01. After reading and checking at every even-numbered address from the address 0x00, read and check at odd-numbered address from the address 0x01.
09-01 /* NVRAM INIIALIZE / CHECK */ 09-01 09-02 09-03 SHIPPING INITIALIZE PATTERN CHECK
Data of the NVRAM are undefined. Investigation to perform repair, etc is required. Initialized data of the NVRAM
Marks A B C D E F G H I J K L M N O P Items disp_cnt_A/B deck status mark_clust_a mark_clust_b mark_sect_a mark_sect_b pb_stop (A/B) laser (A/B) rec_mode rev_time pass_word correct reserve crc_int stamp crc_stamp Values 0x11 0x00 0x00 0x00 0x00 0x00 0x00 ? 0x01 0x00 0x00 ? 1 ? 0x00 ? Remarks A=Lower 4-bit, B=Higher 4-bit use, mark_a/b Cluster address of the mark A Cluster address of the mark B Sector address of the mark A Sector address of the mark B Playback stop position address Count of use of the laser Record ATARC mode Reverse time Password Error correction value of the watch Reserved CRC of the above Stamp character string CRC in stamp character string
SELECT and ENTER
While pressing the g button, rotate the [JOG] dial, then the setup or test starts by pressing the ENTER button after changed k_test_l. · Remote selection By sending the remote command for the setup of k_test_h and k_test_l, the test can start to perform directly without operating buttons of g , [JOG], ENTER , etc.
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MDCT-1000
3-9-2. Initialization of the NVRAM
09-02 /* NVRAM INITIALIZE/CHECK */
3-9-3. 4-Pattern Check
09-03 /* NVRAM INITIALIZE / CHECK */
During execution of the initialization, "k_test_l" shows the following values.
Value of k_test_l 0x21 0x22 0xFF Status During write. During read. Completion of the check
During execution of the check, "k_test_l" shows the following values.
Value of k_test_l 0x31 0x32 0x33 0x34 are 0x0000. Data read and data check are in progress. Data write is in progress. Even number is 0x5555 and odd number is 0xAAAA. Data read and data check are in progress. Data write is in progress. Even number is 0xAAAA and odd number is 0x55555. 0x36 Data read and data check are in progress. Data write is in progress. Both even number and odd number are 0xFFFF. 0x38 0xFF Data read and data check are in progress. Check is complete. 0x37 0x35 Status Data write is in progress. Both even number and odd number
Display during initialization
09-20 /* NVRAM INITIALIZE */ NOW NVRAM INITIALIZE.
Result (Normal completion of the initialization) If nv_error=0, the initialization has normally ended.
09-FF /* NVRAM INITIALIZE */ COMPLETE. CUT OFF POWER.
Display during check
09-31 /* NVRAM PATTERN CHECK */ 1. NOW 00-00 PATTERN CHECK
All data of the NVRAM are set up to 0xFFFF (the initial value of the device). After this, shut off the power supply. (Note) The correction information of the watch is set up to "No correction (0)". (Abnormal completion of the initialization) If nv_error=0x10, the initialization has ended with failure.
09-FF /* NVRAM INITIALIZE */ ERROR. REPAIR HEARDWARE!
Result of the check (In the normal case) If nv_error=0, the result is normal.
09-FF /* NVRAM CHECK */ 1. 2. 3. 4. 00-00 55-AA AA-55 FF-FF PATTERN CHECK OK. PATTERN CHECK OK. PATTERN CHECK OK. PATTERN CHECK OK.
CHECK END. CUT OFF POWER.
The data of the NVRAM are undefined. Investigation to perform repair, etc is required. (Note) The correction information of the watch is set up to "No correction (0)".
All data of the NVRAM are set up to 0xFFFF (the initial value of the device). After this, shut off the power supply. (Note) The correction information of the watch is set up to "No correction (0)". (In the abnormal case) If nv_error>0, the result is abnormal.
09-FF /* NVRAM CHECK */ 1. 2. 3. 4. 00-00 55-AA AA-55 FF-FF PATTERN CHECK OK. PATTERN CHECK OK. PATTERN CHECK ERROR. PATTERN CHECK OK.
REPAER THE HEARDWARE!
Example : An error in write and read of the AA-55 pattern Investigation to perform repair, etc is required. (Note) The correction information of the watch is set up to "No correction (0)".
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MDCT-1000 SECTION 4 ELECTRICAL ADJUSTMENTS
4-1. LASER POWER ADJUSTMENT
1. Enter the test mode of Checking Operations of Mechanism, and start up the adjustment program. (Refer to section 3-3-13. Checking Operations of Mechanism.)
:MON>mdmon MD DRIVE TEST MODE MONITOR Wait..... Hit '.' to exit
4-2. SERVO ADJUSTMENT 1. 2. Set the MD data disk (recordable disk). Select 3) EFBL/SERVO/FBIAS.
1)TEMP 2)LASER 3)EFBL/SERVO/FBIAS 5)EFBL 6)SERVO 7)FBIAS E)Eject >>3 ---MO PIT (FBIAS)---------FBIAS [10] ---MO GROOVE (EFBL)---------EFBL [0F] ---MO WRITE (EFBL)---------EFBL [0F] ---MO GROOVE (FOCUS)---------K13 [4D] ---MO GROOVE (TRACKING)---------K23 [43] K07 [43] ---MO GROOVE (FBIAS)---------FBIAS [2F] T=6774(msec)
>>>PDMD-7 TEST MODE V2.14 [Feb. 16 1998] >>
2.
When the return key is pressed, the menu is displayed.
>>>PDMD-7 TEST MODE V2.14 P)Play A)Access N)Info E)Eject R)Rec K)Erase V)Volum !)Reset X)Cmd L)Laser F)Focus W)Switch S)Spindl J)Jump G)FGSV D)Sled M)EEPROM U)Adjust C)Spec T)Still Y)Sync >> 1)Mon 2)Aging
3.
Press the [ESC] key to terminate the adjustment menu.
1)TEMP 2)LASER 3)EFBL/SERVO/FBIAS 5)EFBL 6)SERVO 7)FBIAS E)Eject >> >>
3.
Select U)Adjust.
>>u 1)TEMP 2)LASER 3)EFBL/SERVO/FBIAS 5)EFBL 6)SERVO 7)FBIAS E)Eject >>
4.
Eject the MD data disk (recordable disk).
>>e
4.
Select 2) LASER.
1)TEMP 2)LASER 3)EFBL/SERVO/FBIAS 5)EFBL 6)SERVO 7)FBIAS E)Eject >>2 --- READJUST?
5.
Select U)Adjust.
>>u 1)TEMP 2)LASER 3)EFBL/SERVO/FBIAS 5)EFBL 6)SERVO 7)FBIAS E)Eject >>
5.
Set the laser power meter (J-2501-046-A) and press the return key.
>>WRITE POWER : 6.85 mW 1)- 2)+ [DA] FD [00ED]
6. 7.
Set the MD data disk (read only disk). Select 3) EFBL/SERVO/FBIAS.
1)TEMP 2)LASER 3)EFBL/SERVO/FBIAS 5)EFBL 6)SERVO 7)FBIAS E)Eject >> ---CD DISC (EFBL)---------EFBL[10] ---CD DISC (FOCUS)---------K13[38] ---CD DISC (TRACKING)---------K23[30] K07[30] ---CD (FBIAS)---------FBIAS[00] T=3143(msec)
6.
Adjust the laser power by pressing [1] key (decreasing the laser power), [2] key (increasing the laser power) until the laser power measurement value is as close as possible to 6.85 mW. Press the return key to set the adjustment value. (Do not take to long time for adjustment. If it takes too long time, the laser power will fluctuate due to temperature increase.)
1)- 2)+ [DA] FD [00ED] 1)TEMP 2)LASER 3)EFBL/SERVO/FBIAS 5)EFBL 6)SERVO 7)FBIAS E)Eject >>
8.
Press the [ESC] key to terminate the adjustment menu.
1)TEMP 2)LASER 3)EFBL/SERVO/FBIAS 5)EFBL 6)SERVO 7)FBIAS E)Eject >> >>
7.
Eject the probe of the laser power meter.
1)TEMP 2)LASER 3)EFBL/SERVO/FBIAS 5)EFBL 6)SERVO 7)FBIAS E)Eject >>e
9.
Eject the MD data disk (read only disk).
>>e
10. Press the period [.] key to exit the adjustment program.
>>. :MON>
11. Turn off the main power of this machine.
:MON>pwof
Note : If discs are replaced while the machine is left in the U/Adjust mode in the machines up to Ver 2.14, the disk types may be incorrectly recognized and adjustment may not be possible. In such a case, press the [ESC] key to terminate the U)Adjust mode once and then select U)Adjust again.
26
SECTION 5 DIAGRAMS
Note on Printed Wiring Boards: MAIN SECTION · X : parts extracted from the component side. · : Pattern from the side which enables seeing. (The other layers' patterns are not indicated.) : Pattern of the rear side. · Note on Schematic Diagram: MAIN SECTION · All capacitors are in µF unless otherwise noted. pF: µµF 50 WV or less are not indicated except for electrolytics and tantalums. · All resistors are in and 1/4 W or less unless otherwise specified. f · : internal component. Note: The components identified by mark 0 or dotted line with mark 0 are critical for safety. Replace only with part number specified. · : B+ Line. · Power voltage is dc 12 V and fed with regulated dc power supply from battery terminal. · Voltages and waveforms are dc with respect to ground under nosignal conditions. no mark : PLAY · Voltages are taken with a VOM (Input impedance 10 M). Voltage variations may be noted due to normal production tolerances. · Waveforms are taken with a oscilloscope. Voltage variations may be noted due to normal production tolerances. · Circled numbers refer to waveforms. · Signal path. E : PB
MDCT-1000
5-1. CIRCUIT BOARDS LOCATION
· Waveforms
2 IC1009 pin4 (TP1006)
62.5 ns (16MHz)
5.4 Vp-p
VOLUME board LEVEL METER board LCD board SWITCH board
3 IC1018 pin4
7.4 Vp-p 22.1 ns (45.1584MHz)
4 IC38 eh (CL25)
4.6 Vp-p 39.4 ns (25.4MHz)
5 IC2 pinya (CL18)
100 ns (10MHz)
4.6 Vp-p
AUDIO I/O board
FOOT SWITCH board
BUM-F1 board MD board MAIN board
27
27
MDCT-1000
5-2. BLOCK DIAGRAMS MD SECTION MD BOARD
HR901 OVER WRITE HEAD I-V AMP IC22 Q11-14 OVER WRITE HEAD DRIVER IC24 SUM 4 3 IC23 1 3 2 3 1 6 7 CHUT IC26 LPF,PHASE SHIFT 18 17 12 11
IC29 DRIVER Y1 Y2 Y7 Y8 I1 I2 I7 I8 2 3 8 9 6 3
IC28 5 4 1 2 VCC
· Signal Path : PB
3
1
5
7 1
G2 19
XMGON
5 OPTICAL PICK-UP KMS-250A (J2N) I J VC A B C D
7 IC38 DSP, EFM/ACIRC ENCODER/DECODER VREF 21 RF 38 PEAK 37 BOTM 36 ABCD 35 AUX 33 ADFG 32 SE 28 IC12 APCREF 12 6 C 7 D FE 34 2 IC9 6 1 7 5 6 7 IC36 1 77 TE 4 2 84 LDDR 69 58 64 65 66 68 82 76 VC RFI PEAK BOTM ABCD AUX1 ADFG SE EFMO 45 79 AD1 Q9 TEMP SENSOR 80 AD2 81 AD3 CSV PB3 5 TXD0 12 RXD0 14 RECS TXD RXD IC40 1 4 2 XRST2 UNREG (6.4V) DTI 4 IC11 1 2 IC2 MD MECHANISM CONTROLLER PB6 8 C2PO LRCK BCK DTO DTI RECS TXD RXD XRST D6.4V
IC21 RF MATRIX AMP
1 I 2 J 3 VC 4 A 5 B
DTI DTO C2PO BCK LRCK
29 30 31 32 33
DTI DTO C2PO BCK LRCK
60 PS2
P
MAIN BOARD (3/3)
IC1 FLASH MEMORY 67 FE REC FOK SENS WRPWR SQSY COUT SRDT 24 2 12 6 14 99 11 D0-D7 27-34 REC FOK SENS WRPWR SQSY TCNT SRDT 58 82 83 87 88 96 15 PS0 P74 P75 IRQ0 IRQ1 PA3 RXD1 21-23 D0-D7 25-29 20-13 3,2,31 A0-A15 1,12,4 5,11 32 XOE 7 XWE 30 XCE
E F
8 E 9 F TE 26 2
IC10 6 1 7 IC35 LPF 4
A0-A15 36-43 45-52 XRD 70 XWR 71 CSO 91
PD Q3,4 AUTOMATIC POWER CONTROL
10 PD SWDT 16 SCLK 17 XLAT 18 1
ILCC
11 APC
IC34 SHOCK DETECT 4 2
XTAI 35 XTAO 34
X1 25.4MHz
66 EXTL X2 10MHz 67 XTL P42 20 P41 19 DSCPRO RFLCT
BUM-F1 BOARD
S301 IC302 SPINDLE MOTOR DRIVER S302 16 6 22 1 2 VS VS BK FG STBY COM U V W 20 15 13 10 Q301-302 MOTOR DRIVER V U W
IC13 4
IC14 1 2 4
IC15 1 2 4 2
7
1 1 IC33 4 1 2 DIR 1 5 IC20 4 SPRD 93 SPDL IC18 7 6 FGDR SPSW FGSV P40 18 PS1 59 VS DIR DISCIN EJECT
M901 (SPINDLE)
9
14 2
S303
10 IC37 FOCUS/TRACKING COIL DRIVER SPINDLE MOTOR DRIVER VS 24 RO4 RI4 19 FFDR XSHOCK LMOD
13
24 P45 23 P44 4 TCA4
FCS+
8 FO1
FI1 6
FCS-
11 RO1
RI1 5 FI3 31
FRDR IC17 TFDR TRDR FS4 SPSW 1 5 7 6 SPFD FGSV
SPFD FFDR FRDR TFDR TRDR FS4
94 87 89 86 85 90
SPFD FFDR FRDR TFDR TRDR FS4
SWDT 8 SCLK 99 XLAT 10
P43 IRQ2 TCA0 PA0 TCKB PA1 TCA3
21 89 95 93 3 94 2 PVCC
LIMIT MOB CK OEB CW STOP FG STBY
S304
IC301 SLED MOTOR DRIVER 27 28 4 3 1 MOB CK OEB CW STOP A1 13 B1 17
M
M903 (EJECT)
M
B2 19 A2 15
M902 (SLED)
XRST 16 13 TXD1 17 CLK1 16 P94
IC3 EEPROM PA7 100 PA6 99 PA4 97 3 DAT 4 SCK 1 CS PVCC 5V
TRK+
29 FO3
Q5 SWITCH IC19 4 3 +5V REG 2
UNREG
TRK-
26 RO3
RI3 32 PS CLK 3 34
LMOD XSHOCK LDON MLON Q6-8 B+ SWITCH IC39 2 +2.8V REG 3 Q15,16 RF MOD SWITCH
6 PB4 90 IRQ3 9 PB7 7 PB5 RES 63 XRST MVCC 3.5V
LDON
Q10 SWITCH IC30 4 3 +3.5V REG 2
MOD XRST
UNREG XRST 4 IC5 1 2 XRST2 IC6 1 RESET 3 UNREG VCC 3.5V
Q1 SWITCH IC4 4 3 +3.5V REG 2
28
28
MDCT-1000
I/O SECTION
LEVEL METER BOARD
D9201-9203 IC9201 LED LEVEL METER DRIVER 9 VC5 4 VC3 1 VC1 IC9202 LED LEVEL METER DRIVER 9 VC5 4 VC3 1 VC1 IN 12 MON LEV 2 IN 12 MON LEV 1 D9207-9209 IC9203 LED LEVEL METER DRIVER 9 VC5 4 VC3 1 VC1 IC9204 LED LEVEL METER DRIVER 9 VC5 4 VC3 1 VC1 IN 12 MON LEV 4 S9201,D9215-9219 MONITOR MONITOR SELECTOR IN 12 MON LEV 3 D9207 -9212 Q9201-9203 B+ SWITCH MON LEV 2 MON LEV 3 D9204-9206 D9210-9212 MON LEV 4 MON SEL 1 MON SEL 2 MON SEL 3 MON SEL 4 4 7 6 1 2 IC307 AMP 7 6 MODE0 MODE1 BEEP ON IC705(1/2) 11 12 9 8 IC105 AD/DA CONVERTER ADDT12 SDTO 13 MCLK XPD DADT12 LRCK SCLK 17 20 12 10 11 MCKI XPD STDI LRCK SCLK IC106 BUFFER 5 7 BEEP 3 1 IC501 MONITOR SWITCH 2 MON SEL 1 MON SEL 2 MAIN BOARD (2/3) 13 4 5 10 MON SEL 3 MON SEL 4 XDEM MAIN BOARD (2/3) 12 8 6 9 11 3 RV6002 MONITOR VOL Q509,510 MUTING 1 2 IC505 AMP 1 IC506(1/2) AMP 6 7 IC507 POWER AMP 6 B+IN OUTA 1 7 A+IN OUTB 3 5 B-IN 8 A-IN Q506,507 MUTING Q701 SWITCH IC706(1/2) BEEP OSC 2 IC706(2/2) BUFFER 1 5 7 Q508,510 MUTING IC506(2/2) BUFFER 3 1 IC509 EARPHONE AMP 3 IN+1 OUT1 1 5 IN+2 OUT2 7 2 IN-1 6 IN-2 Q514,515 MUTING 10 A5V MON LEV 1
2CH X4CH
2CH X4CH
· Signal Path
1 2 IC107 AMP
: PB
6 5
IC704 4 2 3 1 MUTE SP1 XMUTE SP0
FOOT SWITCH BOARD (2/2)
J9001 EAR
MAIN BOARD (1/3)
AOUTL 22
AOUTR 23
AUDIO I/O BOARD
(SPEAKER)
DEM0 15
B
ADDT12 ,ADDT34
VOLUME BOARD(2/2)
A
IC703 3.3V (IC105) (IC305) 3 +3.3V 2 REG A5V XMUTE IC705(2/2) 9 IC305 AD/DA CONVERTER SDTO 13 MCLK XPD DADT34 LRCK SCLK MCKI XPD STDI LRCK SCLK 8 Q502 SWITCH
ADDT34
IC306 BUFFER 5 7
MAIN BOARD (3/3)
C
XDEM MODE0 MODE1 XMUTE BEEP ON 2CH X4CH
XDEM MODE0 MODE1 XMUTE BEEP ON 2CH X4CH
17 20 12 10 11
AOUTL 22
AOUTR 23
3
1 IC1002 D1007 4 NMI B12V D5VCPU D5V D6.4V Q1005 SWITCH Q1006 SWITCH D1006 IC1064 SWITCHING REG 10 OUT1 VCC 9 J1001 DC IN 12V
DEM0 15
B12V
2 2 RESET 8
IC1006
14
SWITCH BOARD (2/2)
S9401 ON
MAIN BOARD (3/3)
D
IC701 A9V REG ON 4 +9V REG 1 IC702 A5V XPDOWN 4 +5V REG 1 2 2
STANDBY
Q1002 SWITCH Q1003,1004 SWITCH
1 2
IC1063 4 XSTANDBY
29
29
CTL
7 OUT1
MDCT-1000
FIFO SECTION
· Signal Path
MAIN BOARD(2/3)
DATA BUS D[0]-D[15]
H I J
IC1017 DRAM 14 XRAS 29 XOE 13 XWE 30 XUCAS 31 XLCAS I/O0 2-5,7-10 33-36 38-41 A0 17-20 A8 23-27 A9 28,16 15 D[0]-D[15] MAIN BOARD (3/3)
: PB
ADDRESS BUS A[0]-A[20]
IC1042 ATRAC ENCODER/DECODER DADT12r
A[0]-A[4]
D[8]-D[15]
CONTROL SIGNAL BUS
XCS3 41,38-35 A0-A4 63 ADT04 58 ADTI2 XIRQ0 IC1043 XREC 9 10 13 IC1048 2 4 12 3 1 XPB 2 6 4 XREC 5 59 XLAT2 XWRFA 79 62 XLAT0 IC1021 FIFO CONTROLLER 11 64 XRQ0 8 57 XRQ2 23-30 I/O0-I/O7 CS 34 XRD 43 XWR 44 CPUSCK 46 XRST 45 FIA0 81 FIA7 88 XRDF0 80 2 IC1022 6 XRD XCS7 XRD XHWR 16MHz XRES XHWR XLWR
I/O15
33 DODT12
ACDI12 28 ACDO12 31 XIRQ0 10 SCLK 20 SCLK SWDT SWDT 23 XLAT1A XLAT 24
A[1]-A[9]
A11
A[18]-A[20]
IC1025 FIFO FIA[0]-FIA[7] 10,11,13 Q0 14,19-22 Q7 18 XR 2 XW PB 1/2ch D0 7-4 D7 31-28 XRS 25 D[8]-D[15]
ADDT12
1 2
IC1046 4 34 AIDT12
XARQ12N 32
XRES1 IC1069 3.3V MAIN BOARD (1/3) MAIN BOARD (1/3) 3 +3.3V REG 2 IC1027 BUFFER DADT12 DADT34 MCLK SCLK LRCK 18 1Y 17 2Y 15 4Y 13 6Y 11 8Y 1A 2 2A 3 4A 5 6A 7 8A 9 256Fs 64Fs LRCKA DADT34r D5V 512fs 128fs X64fs LRCKA
19 XRST 15 25 36 38 EXTAL ACLK BCK LRCK12 XABS12 29 4 IC1047 2 1
A
55 DO12 69 DO34 IC1051 ATRAC ENCODER/DECODER IC1026 FIFO 48 FIB0 70 FIB7 76 XRDF1 49 FIB[0]-FIB[7] 10,11,13 Q0 14,19-22 Q7 18 XR 2 XW PB 3/4ch D0 7-4 D7 31-28 XRS 25 RST01 D[8]-D[15]
B
33 DODT34
ACDI34 28 ACDO34 31 XIRQ0 10 SCLK 20 SWDT 23 XLAT 24 XIRQ0 SCLK SWDT IC1052 XREC 9 10 13 IC1057 2 4 12 3 1 XPB 2 6 4 XREC 5 11 8
53 ADTO1 94 ADTI3
XPD
IC1032 4 2
MAIN BOARD (3/3) PD
XWRFB 47
E
1 2 IC1055 4 34 AIDT34
K
MAIN BOARD (3/3)
95 XRQ3
ADDT34
XARQ34N 32
96 XRQ1
XRES1 512fs 128fs X64fs LRCKA
19 XRST 15 25 36 38 EXTAL ACLK BCK LRCK34 XABS34 29 4
IC1056 2 1
52 XLAT1 ACLK 5 93 XLAT3 FS64 3 BCK 97 BFIN 8 BFOUT 9
128fs
64fs COUNTER LRCKA IC1059 7 Ep XARQ12N XARQ24N 2 CK 1 XCLR RCo 15 IC1061(1/2) 12 D2 11 CLK2 13 CLR2 XQ2 8
XRES1
XLAT1A 1 XLAT2A 2 MAIN BOARD (3/3)
IC1050 XLAT2G
F
IC1018 OSCILLATOR 4 2 D5V CPU IC1019 DIVIDER 3 CLK1 Q1 5 11 CLK2 Q2 9
65
256FS
4
FS01 4 LRCK 98
FINT12
Q1011,1013-1015 +5V B+ SWITCH
IC1060 IC1020 X64fs 4 2 64fs X64fs 7 Ep 2 CK 1 XCLR RCo 15
IC1061(2/2) 2 D1 3 CLK1 1 CLR1 XQ1 6 FINT34
512fs
Q1012,1016-1018 +5V B+ SWITCH 4 IC1070 XRES 2 XRES 1
X1003 45.1584MHz
256fs
L
MAIN BOARD (3/3)
IC1062
G
MAIN BOARD (3/3)
2
4
30
30
MDCT-1000
CPU SECTION
MAIN BOARD (3/3)
DATA BUS D[0]-D[15]
H I
XRESL XRES 1 2 IC1014 4 IC1011 BUS TRANSCEIVER 2 1A 9 8A 1 DIR A[1]-A[18] 1 IC1012 4 2 IC1015 D-FF 2 1D 1Q 5 3 1CK 4 1XS SDDT-1809 IC1013 BUFFER A[0] D[8]-D[15] XRD XHWR XCS4 16MHz A0 10-3,25 24,21 A14 23,2,1 XRES A[1]-A[15] 2 3 4 5 6 9 1A 2A 3A 4A 5A 8A 1Y 2Y 3Y 4Y 5Y 8Y 18 17 16 15 14 11 LCD A[0] LCD XRD LCD XHWR LCD XCS4 LCD 16MHz LCD XRES DECKSEL 2 DTOT-1809 1 2 1 IC1071 4 2 IC1040 4 DTI A DIRECTION CONTROL IC1038 1 4 IC1037 2 4 2 1IC1039 4 RXD A RECS A C2PO A TXD A RXD A LRCK A BCK A DTO A DTI A XRST A D6.4V 1B 18 8B 11 DISP_CTL MAIN BOARD (2/3)
ADDRESS BUS A[0]-A[20] CONTROL SIGNAL BUS
· Signal Path : PB
J
45-52 54-65,95 A0-A20
27-34 36-43 D0-D15 XRD 78 XHWR 79 XLWR 80 XCS0 XCS1 XCS3 XCS4 XCS6 XCS7 104 103 101 13 15 16
IC1010 EPROM XRD XHWR XLWR XCS0 XCS1 XCS3 XCS4 XCS6 XCS7 XRESL 1809RST IRQ0 XDREQ0 XDREQ1 INT1809 IC1009 1 IC1016 SRAM XCS1 XRD 4 16MHz XHWR 20 XCE 22 XOE 27 XWE D0 11-13 D7 15-19 D8-D15 10-3 D0-D7 19-12 XCS0 2 XCE 21-29 A0-A17 31-39 20 XRD D[0]-D[15] D[8]-D[15]
LCD-D08-D15
8
SW_AN-IN1 SW_AN-IN3 SWITCH BOARD
AN-IN[1] AN-IN[3] AN-IN[5] AN-IN[6] SLA SLB
87 AN-IN1 89 AN-IN3 91 92 2 3 AN-IN5 AN-IN6 PB0 PB1
XRD
M
SW_AN-IN5 SW_AN-IN6 SW_SLA SW_SLB
XRD XCS4 16MHz XRES
O
LCD BOARD
PA4(XREST) 109 PA7(1809RST) 111 IRQ0 XDREQ0 XDREQ1 KEY-INT 100 8 9 17
TRC_ON TRC_ON FS_PLAY FSFS FOOT SWITCH BOARD (1/2) Q1007 SWITCH Q1008 SWITCH Q1009 SWITCH Q1010 SWITCH B12V B12V AN-IN[7] 93 AN-IN7 AN-IN[0] 86 KEY-IN IC1007 CPU 4 PB2
P
MD BOARD
PHA1 69 2 XTAL 75 EXTAL 74
N
FS-BS
X1002 16MHz XCS1 XRD
IC1067 SRAM 20 XCE 22 XOE 27 XWE A0 10-3,25 24,21 A14 23,2,1 A[1]-A[15] D0 11-13 D7 15-19
D[0]-D[7] 16MHz
IC1072 D-FF 2 1D 1Q 5 3 1CK 12 2D 2Q 9 11 2CK C2PO-1809 TIMING CONTROL SDIN-1809 9 LRCK-1809 12 7 RCTR-1809 4
IC1034 2 3 5 6 11 10 14 13 1 IC1035 BTCK-1809 DTIN-1809 7 IC1036 XMDRES 2 1 4 11 10 14 13 6 DECKSEL RD02 64 RA04 RA07 RA06 RD00 RD01 RD04 RD05 74 69 68 61 62 66 67 RST01 XIRQ0 XREC XPB SCLK SWDT XLAT1A XLAT2A (L=A ,H=B) MAIN BOARD (2/3) +3.3V 3 IC1065 +3.3V 2 REG D5VCPU 4 2 3 5 6 9 12 XRST A BCK A DTO A RECS A C2PO A TXD A LRCK A
IC1005 XLWR RX232C TX232C 8 R1IN R1OUT 9 13 T1OUT T1IN 11 22 RXD0 20 TXD0
IC1008 XRES 71 1 RESET 2 D5VCPU D[0]-D[15] A[1]-A[5] NMI 72 PB4 6 PBF5 7 107 PA2(NV_SCLK) 108 PA3(NV_DIO) XRES_AD 68 110 PA5(NV_CS) XRES1 67 FINT12 18 FINT34 102 XRES1 FINT12 FINT34 PD NMI XSTANDBY XPDOWN
IC1033 MD CONTROLLER 32-37 HD00 39-48 HD15 15 HAD1 19 HAD5 4 5 7 8 9 10 12 14 30 31 60 59 58 57 56 55 HSCK XRST HXCS HXWL HXWH HXRD HXD0 HXD1 HXI1 HXI2 IO07 IO06 IO05 IO04 IO03 IO02 RA07 RA08 DTOT DTIN C2PO LRCK BTCK RCTR SDIN SDOT 79 80 90 91 92 93 94 95 49 50 DECKSEL XMDRES DTOT-1809 DTIN-1809 C2PO-1809 LRCK-1809 BTCK-1809 RCTR-1809 SDIN-1809 SDOT-1809
DECKSEL
IC1003 NVRAM SCLK 2 DO 4 DI 3 CS 1
D
MAIN BOARD (1/3)
E L
MAIN BOARD (2/3)
16MHz 1809RST XCS6 XLWR XHWR XRD XDREQ0 XDREQ1 INT1809 IRQ0
MAIN BOARD (2/3)
K F
MAIN BOARD (1/3)
C
XDEM 2CH X4CH MODE1 MODE0 XMUTE BEEP ON
MAIN BOARD (2/3)
XRES
G
MAIN BOARD (2/3)
31
31
MDCT-1000
LCD SECTION
LCD BOARD
DISP_CTL IC4004 LCD CONTROLLER XD0 33 XD3 30 8 LCD-D08-D15 22 D0 29 D7 YD WE LP XSCL 40 36 37 35 DIN FR LP XSCL VD0-7 IC4006 VRAM XSCL 11-13 D0-7 15-19 10-3,25 24,21,23 A0-15 2,26,1 27 XWE 22 XOE IC4002 VA15 IC4001(1/2) 8MHz VA14 12 17 XG VA13 10 VA10 9 8 11 12 13 9 10 7 2 8MHz 8 9 10 3 2 5 6 3 1CK IC4007 D-FF 4 20 XCE XSCL 2 1D 1Q 5 LP IC4008 8 LP 9 TIMING GENERATOR YDIS IC4016 BUFFER 8 7A 5 4A FR XSCL YDIS LOAD 2 1A 4 3A 9 8A 3 2A 7Y 12 4Y 15 1Y 18 3Y 16 8Y 11 2Y 17 DF CP DISP LOAD0 FRAME D0-D3 4
XD0-X