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5 4 3 2 1
MODEL: REV: CHANGE LIST: MODEL : ZL5 MB
1A FIRST RELEASE
PAGE FROM TO
2A 01. Page2 : Unstaff R202 for correct clock setting
1 3A 3B
02. Page3 : Delete JP2, Unstaff C561 and C559 ~ C562, C567 change P/N to CH6101M9A07 due to the height limitaion
2 3A 3B
03. Page5 : Change DDR MD terminator resistor array to 56ohm 4P2R type
ZL5 3 3A 3B
D MotherBoard 04. Page9 : Change R20 to 6.2K, Unstaff C13 D
4 3A 3B
05. Page10 : Modify the CRT circuit due to the bad signal quality of CM2009 (Delete U1, Add D25, D28 ~ D32, Q35, Q36, R405, R404, R406, U31, U32)
5 3A 3B
06. Page11 : RN5, RN7, RN8, RN11, RN20, RN21 change P/N to CJ282084N01
6 3A 3B
07. Page12 : Modify the power good circuit (Delete D15, Add R402, R403)
7 3A 3B
08. Page16 : Modify the lan led circuit to fit to the right led color definition (R350, R353 change to pull high, Add D26, D27, CN3 change footprint)
8 3A 3B
09. Page17 : CN7, CN8 change footprint
9 3A 3B
10. Page19 : HOLE25 change to TOP layer
10 3A 3B
11. Page20 : Cancel the HOLD# ciruit (Unstaff R95, R111, D5, D7, Q17, Staff Q15, R99)
11 3A 3B
12. Page21 : SW2, SW3 change P/N to DHPPS11BD0
12 3A 3B
13. Page22 : Add PR123, PD16, PC149; PD13 change P/N to BC05FA20Z01; PU12 change P/N to AL001999W16
13 3A 3B
14. Page23 : PR63 change to 11K/F; PD15 change P/N to BC10QS04C01; Staff PC77 1000P
14 3A 3B
15. Page25 : PL8, PL9 change size to RC0805; PD8, PD9 change P/N to BC10QS04C01
15 3A 3B
C 16. Page26 : Unstaff PQ4; PR101, PR105 change P/N to CS31003B919; PU9 change P/N to AJ017720W06 C
16 3A 3B
17. Delete JP1, JP2 ~ JP6
17 3A 3B
18. U20 change P/N to AJ007600T25
18 3A 3B
19. L7, L8, L9, L10, L11, L12, L13, L14, L15, L16, L18, L24, L26, L27, L40, L43, L47, L48, L49, L50 change P/N to CX0QNT03004
19 3A 3B
20. PQ3, PQ4, PQ5, PQ6, PQ8, PQ9, PQ10, PQ12, PQ13, PQ14, PQ15, PQ16, PQ18, PQ24, PQ32, PQ33, PQ35, Q2, Q3, Q4, Q5, Q6, Q8, Q9, Q11, Q26, Q27, Q34 change P/N to BAM70020074
20 3A 3B
3A 01. Page2 : Staff R176 33ohm for 302ELV clock
21 3A 3B
02. Page4 : Staff C131, C175, C188, C189
22 3A 3B
03. Page9 : Staff R295(0ohm), R294 change P/N to CS00002JB03, Unstaff Y4, C31, C554 for 302ELV clock; Add C710 ~ C713, R407 ~ R410 for EMI reserved.
23 3A 3B
04. Page10 : D17 change p/n to BC05FA20Z01 to enlarge the current limit; L1 ~ L3 change p/n to CX808600101 for EMI
24 3A 3B
05. Page12 : C633, C634 change P/N to CH01806JB07 to adjust RTC accuracy; Add JP1 for RTC reset
25 3A 3B
06. Page15 : Add C709
26 3A 3B
07. Page17 : Unstaff CN8, CN10; Add C700 ~ C708 for EMI
B 08. Page19 : Delete HOLE18; Staff PAD4 for modem cable B
3B 01. Page17 : L36, R274, R279 change p/n to CX8HS121001; Staff R270, R273 100pF
02. Page18 : L54, L55 change p/n to CX8HS121001; Unstaff R260, R261, R265, R271, R278
03. Page19 : Staff PAD9(FDMK1004010) for EMI
04. Page22 : Unstaff PR112 for thermal shutdown working properly
05. Q2, Q3, Q4, Q5, Q6, Q8, Q9, Q11, Q18, Q26, Q27, Q34, Q35, Q36, PQ3, PQ4, PQ5, PQ6, PQ8, PQ9, PQ10, PQ12, PQ13, PQ14, PQ15, PQ16,
PQ18, PQ24, PQ32, PQ33, PQ35 change p/n to BAN70020Z13
A A
PROJECT : ZL5 APPROVE BY: SAINT LIN DRAWING BY:DILBERT YU REV 3B
COVER SHEET 1 OF 1
Quanta Computer Inc. MB ASSY'S P/N : 31ZL5MB0009 PROJECT LEADER: SAINT LIN DOCUMENT NO: DATE :2005/3/9
5 4 3 2 1
8 7 6 5 4 3 2 1
HOST 200MHz
CPU
CLK-GEN
ZCLK 133MHz
AGP 66MHz
DDR 333
AMD Athlon64 ZL5
ICS 952801
PCI 33MHz
DDR SO-DIMM SMT uPGA754 Thermal Block Diagram
D D
Page 5 Page 3,4 Thermal sensor & Fan
USB 48MHz
HyperTransport
REF 14.318MHz
Page 2
16x16
1600MT/s
CRT
RGB 1x D-SUB 15-Pin
NB INTA#
Page 10
LCD
3V_ALWAYS SIS M760GX DVO LVDS LVDS 15" XGA/WXGA
Page 10
5VPCU (698 PIN BGA) Transmitter
SIS302ELV
3V_S5
Page 6,7,8 Page 9
1.8V_S5
3V/5V MuTIOL(1GB/s)
C
3VSUS REQ0#, GNT0# C
INTB#, INTC# IDSEL : AD22
5VSUS
HDD ATA 66/100 PCI 2.2 133MB/s (33MHZ) Mini PCI
+3V Primary Master Antenna
+5V
Page 19 SB REQ1#, GNT1#
WLAN 802.11A/G
Page 15
ODD INTD# IDSEL : AD17
15V ATA 66/100
Page 22
Secondary Master
Page 19
SIS 963L CardBus
TI PCI1410
PC Card
1x type-I/II
(371 PIN BGA) Page 14
USB USB 2.0
2.5VSUS 3x connector
Page 15
1.25VREF MII LAN PHY Transformer RJ-45
2.5V/1.25V RTL8201CP Page 16
+2.5V MINI USB Page 16 Page 16
(BLUETOOTH)
DDR_VTT Page 15
B AC'97 2.1 MDC1.5 RJ-11 B
Page 23 56K MODEM Page 16
Page 17
+1.2V_HT MIC-In Jack
1.2V/1.5V +1.5V
Page 11,12,13
AC97 Codec Line-In Jack
1.8V +1.8V ALC203
Page 24 LPC
Page 17 AMP HP-Out Jack
Int. Keyboard MAX9755
87-Key EC Int. Speaker
CPU CORE VCC_CORE Page 21 Page 18
NS PC97551
Page 25
Touch Pad BIOS
A
6-Button Page 20 Page 20 A
Page 21
BATTERY PROJECT : ZL5
CHARGER Quanta Computer Inc.
Page 26 Size Document Number Rev
BLOCK DIAGRAM 3B
Date: Thursday, March 10, 2005 Sheet 1 of 26
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
+3V U12 By-Pass Capacitors
L23 VCC3_CLKGN 1 Place Close to Clock Generator
FBM2125 VDDREF
11 VDDZ Damping Resistors
15 VDDPCI
C281 C288 C314 C257 24 Place Close to Clk Generator CPUCLK1_H C313 *10P_4
VDDPCI
31 VDD48
D .1U_4 .1U_4 .1U_4 .1U_4 33 CPUCLK1_L C300 *10P_4 D
C291 VDDAGP MGN_CPU1T R182 15_4
43 VDDCPU CPU_1T 42 CPUCLK1_H [6]
C356 44 41 MGN_CPU1C R174 15_4
VDDCPU CPU_1C CPUCLK1_L [6]
.1U_4 C280 C277 C350 C301 AGPCLK0 C279 *10P_4
10U/10V_8 46 MGN_CPU0T R198 15_4
CPU_0T CPUCLK+ [3]
.1U_4 .1U_4 .1U_4 .1U_4 5 45 MGN_CPU0C R189 15_4
GNDREF CPU_0C CPUCLK- [3]
8 ZCLK0 C302 *10P_4
GNDZ
16 GNDPCI
23 ZCLK1 C297 *10P_4
GNDPCI
28 GND48
36 35 MGN_AGPCLK0 R147 22_4
GNDF AGPCLK0 AGPCLK0 [6]
34 96XPCLK C278 *10P_4
AGPCLK1
40 9 MGN_ZCLK0 R175 22_4
+3V GNDCPU ZCLK0 ZCLK0 [7]
47 10 MGN_ZCLK1 R171 22_4 PCLK_MP C275 *10P_4
GNDCPU ZCLK1 ZCLK1 [11]
R203 33_4 PCLK_PCM C270 *10P_4
14M_CODEC [17]
2 FS0 R204 33_4
FS0/REF0** VOSCI [7]
3 FS1 R192 33_4 PCLK_591 C261 *10P_4
FS1/REF0** REFCLK1 [12]
R205 4 FS2 R185 33_4
FS2/REF0** VOSCIE [7]
4.7K_4 R176 33_4 VBRCLK C303 *10P_4
VBRCLK [9]
13 FS3
R197 *0_4 FS3/PCICLK_F0** FS4
[12] CPUSTP# 48 CPUSTOP#* FS4/PCICLK_F1** 14
17 MGN_PCICLK1 R143 33_4 REFCLK1 C324 *10P_4
PCICLK0 96XPCLK [11]
18 MGN_PCICLK2 R135 33_4
MGN_PD# PCICLK1 PCLK_MP [15]
R156 10K_4 37 19 MGN_PCICLK3 R133 33_4 VOSCI C337 *10P_4
+3V PD#* PCICLK2 PCLK_PCM [14]
20 MGN_PCICLK4 R130 33_4
PCICLK3 PCLK_591 [20]
C 21 VOSCIE C317 *10P_4 C
PCICLK4
PCICLK5 22
PCICLK6 25
26 UCLK48M C276 *10P_4
R158 4.7K_4 PCICLK7
+3V
STP_PCI# R153 *0_4 12
[12] STP_PCI# PCI_STOP#*
30 CLK48M R140 22_4
+3V 48MHz UCLK48M [13]
24_48MHz 29
L22 VCC3_CLKGN_VDDA 38
FBM2125 VDDA
32 +3V
SCLK SMBCLK [5,12]
C289 C284 C292 27
.1U_4 .1U_4 10P_4
SDATA SMBDAT [5,12]
Frequency Selection
R202 *2.7K_4 FS0 R201 *2.7K_4
39 R191 2.7K_4 FS1 R190 *2.7K_4
GNDA * INTERNAL PULL-HIGH 150K R184 *2.7K_4 FS2 R183 *2.7K_4
** INTERNAL PULL-lOW 150K R155 *2.7K_4 FS3 R154 *2.7K_4
R150 *2.7K_4 FS4 R149 *2.7K_4
X1
X2
ICS952801
+3V
6
7
Y2
B 14.318MHz B
C355 C353 C354
C298 C271
10U/10V_8 .1U_4 10P_4
10P_4 10P_4
CLK Table for SiS M760 ( Not For ICS ICS-952801)
SiS 755/M760 CLOCK SiS 755/M760 CLOCK
(FS4) (FS3) (FS2) (FS1) (FS0) CPU ZCLK AGPCLK PCI VCO (FS4) (FS3) (FS2) (FS1) (FS0) CPU ZCLK AGPCLK PCI
(MHz) (MHz) (MHz) (MHz) (MHz) (MHz) (MHz) (MHz) (MHz)
0 0 0 0 0 200 66.66 66.66 33.33 400 1 0 0 0 0 180 135 67.5 33.75
0 0 0 0 1 200 100 66.66 33.33 400 1 0 0 0 1 185 132.14 66.07 33.04
0 0 0 1 0 200 133.33 66.66 33.33 400 1 0 0 1 0 190 135.71 67.08 33.93
0 0 0 1 1 200 166.66 66.66 33.33 1000 1 0 0 1 1 195 130 65 32.5
0 0 1 0 0 233 66.66 66.66 33.33 466 1 0 1 0 0 205 136.66 68.33 34.17
A 0 0 1 0 1 233 93.2 66.66 33.33 466 1 0 1 0 1 210 140 70 35 A
0 0 1 1 0 233 133.28 66.66 33.33 933 1 0 1 1 0 215 129 64.5 32.25
0 0 1 1 1 233 139.8 69.9 33.33 699 1 0 1 1 1 220 132 66 33
0 1 0 0 0 266 66.66 66.66 33.33 266 1 1 0 0 0 66.66 66.66 66.66 33.33
0 1 0 0 1 266 106.4 66.5 33.33 532 1 1 0 0 1 66.66 100 66.66 33.33 PROJECT : ZL5
0 1 0 1 0 266 133 66.5 33.33 532 1 1 0 1 0 100 100 66.66 33.33
0 1 0 1 1 266 159.6 66.5 33.33 798 1 1 0 1 1 100 133.33 66.66 33.33
0 1 1 0 0 200 133 50 33.33 400 1 1 1 0 0 133 100 66.66 33.33 Quanta Computer Inc.
0 1 1 0 1 200 114 66.66 33.33 800 1 1 1 0 1 133 133.33 66.66 33.33
0 1 1 1 0 200 142 66.66 33.33 1000 1 1 1 1 0 166 100 66.66 33.33
0 1 1 1 1 200 160 66.66 33.33 800 1 1 1 1 1 166 133.33 66.66 33.33 Size Document Number Rev
CLOCK GENERATOR 3B
Date: Thursday, March 10, 2005 Sheet 2 of 26
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
+1.2V_HT U21A +1.2V_HT U21C VCC_CORE
AMD K8 AMD K8
LDT CTL & DBG R304 *51.1/F_6 CORE_SENSE
B27 V_HT0_A0 V_HT0_B0 AF25
B29 AE28 AF20 A20 THERMTRIP#
V_HT0_A1 V_HT0_B1 [6] LDTREST# RESET# THERMTRIP# THERMTRIP# [12]
C26 AF29 CPU_PWROK AE18
V_HT0_A2 V_HT0_B2 PWROK THERMDA
C28 V_HT0_A3 V_HT0_B3 AG26 [6] LDTSTOP# AJ27 HT_STOP# THERMDA A26 Length < 1"
D25 AG28 A27 THERMDC
V_HT0_A4 V_HT0_B4 L0_REF1 THERMDC Width : 10mil
D27 V_HT0_A5 V_HT0_B5 AH27 Length < 1" AF27 L0_REF1 Near Socket754
D29 AH29 L0_REF0 AE26 AJ28
[6] CADIP[15..0] V_HT0_A6 V_HT0_B6 CADOP[15..0] [6] L0_REF0 KEY0 T47
D KEY1 A28 T50 D
CADIP15 T25 N26 CADOP15 COREFB A23 CPU_CLK C570 3900P_6
HT_RXD15 HT_TXD15 COREFB CPUCLK+ [2]
CADIP14 U27 L25 CADOP14 COREFB# A24 R305
CADIP13 HT_RXD14 HT_TXD14 CADOP13 CORE_SENSE COREFB# 169/F_6 CPU_CLK- C569 3900P_6
V25 HT_RXD13 HT_TXD13 L26 B23 CORE_SENSE CPUCLK- [2]
CADIP12 W27 J25 CADOP12 AG18
CADIP11 HT_RXD12 HT_TXD12 CADOP11 NC_BP3 FBCLKOUT- R308 80.6/F_6 FBCLKOUT
AA27 HT_RXD11 HT_TXD11 G25 T17 AE12 VDDIOFB NC_BP2 AH18
CADIP10 AB25 G26 CADOP10 AF12 AG17 BP1
HT_RXD10 HT_TXD10 T18 VDDIOFB# NC_BP1
CADIP9 AC27 E25 CADOP9 VDDIO_SENSE AE11 AJ18 BP0
CADIP8 HT_RXD9 HT_TXD9 CADOP8 VDDIO_SENSE NC_BP0 VCC_CORE
AD25 HT_RXD8 HT_TXD8 E26
CADIP7 T27 N29 CADOP7 CPU_CLK AJ21 AJ23 BPSCLK
CADIP6 HT_RXD7 HT_TXD7 CADOP6 CPU_CLK- CLKIN NC_BPSCLK BPSCLK- R302 51.1/F_6 COREFB
V29 HT_RXD6 HT_TXD6 M28 AH21 CLKIN# NC_BPSCLK# AH23 COREFB [25]
CADIP5 V27 L29 CADOP5
CADIP4 HT_RXD5 HT_TXD5 CADOP4 FBCLKOUT R297 51.1/F_6 COREFB#
Y29 HT_RXD4 HT_TXD4 K28 Diff. Pair AH19 FBCLKOUT NC_PLLCHZ AE24 T49 COREFB# [25]
CADIP3 CADOP3
CADIP2
AB29 HT_RXD3 HT_TXD3 H28
CADOP2 Zdiff=80ohm FBCLKOUT- AJ19 FBCLKOUT# NC_PLLCHZ# AF24 T48
AB27 HT_RXD2 HT_TXD2 G29 Trace route
CADIP1 AD29 F28 CADOP1 AH25 D20 SCANCLK1
CADIP0 HT_RXD1 HT_TXD1 CADOP0
CPU_VCCA VDDA1 NC_SCANCLK1 SCANCLK2 +1.2V_HT as 10/10/10
[6] CADIN[15..0] AD27 HT_RXD0 HT_TXD0 E29 CADON[15..0] [6] AJ25 VDDA2 NC_SCANCLK2 C21
D18 SCANEN
CADIN15 CADON15 NC_SCANEN SCANSHENB R46 44.2/F_6 L0_REF1
R25 HT_RXD#15 HT_TXD#15 N27