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A B C D E
MODEL AME : KIU20
PCB O : LA-5091P (DA60000BR10)
1
BOM P/ : 43169831L02 1
Compal Confidential
2
Bear Schematics Document 2
Intel Diamondville Processor with Calistoga(945GSE) + DDRII + ICH7M
2009-3-31
REV: 1.0
3 3
@ : Nopop Component
1@ : For N280 only
2@ : For N270 only
4 4
om
l.c
ai
tm
Security Classification
Classification Compal Secret Data Compal Electronics, Inc.
ho
Issued Date 2008/11/10 Deciphered Date 2009/11/10 Title
f@
Cover Page
in
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
xa
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-5091P
he
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 22, 2009 Sheet 1 of 39
A B C D E
A B C D E
Compal Confidential
Model ame : KIU20 Diamondville SC Thermal Sensor
File ame : LA-5091P EMC1402
FCBGA8 page 4
1
437Pins 1
22x22mm Clock Generator
page 4,5
CK505 page 12
FSB
H_A#(3..31) 400/533MHz H_D#(0..63)
CRT Conn RGB Port 4 WWA
page 19
page 14 Calistoga GSE Memory BUS(DDRII) DDRII-SO-DIMM
page 11
FCBGA998
1.8V DDRII 400/533 Port 6
LVDS 27x27mm WLA
LCD Conn. page 19
page 13 page 6,7,8,9,10
DMI
2 X2 mode Port 0 USB Port X1 2
USB PWR page 27
PCI-Express ICH7M
BGA652 SATA USB daughter board
Port 3 USB Port X1
31x31mm HDA
page 27
page 15,16,17,18
2.5" HDD
MI I Card 10/100 Ethernet page 22
Port 7 USB Port X1
RTL8103EL
WLA page 27
page 19 page 24
LPC BUS Audio Codec AMP & Speaker Through BT cable
3 ALC272-VB-GR 3
page 20
RJ45 page 21 Port 5
page 24 BlueTooth
HeadPhone & page 19
E E KBC SPI MIC Jack
page 21
Power O /OFF DC/DC Interface KB926
page 25
Through LVDS cable
page 26 page 30
Port 1
DC I CMOS CAM
3VALW/5VALW
page 30 page 32 page 13
BATT CO /OTP 1.5VS/0.9VS/ Int.KBD Touch Pad SPI ROM
page 36 page 25 page 26 page 26
2.5VS Card Reader
Port 2
CHARGER page 34 RTS5159
4
page 31 SD/MMC/MS 4
page 23
1.8V/VCCP
page 33
LED CO
page 22
CPU CORE Security Classification Compal Secret Data Compal Electronics, Inc.
page 35 Issued Date 2008/11/10 Deciphered Date 2009/11/10 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5091P
Date: Wednesday, April 22, 2009 Sheet 2 of 39
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A B C D E
ZZZ
PCB
DA60000BR10
1 1
Voltage Rails
External PCI Devices
Power Plane Description S1 S3 S5
VIN Adapter power supply (19V) N/A N/A N/A
DEVICE IDSEL # REQ/GNT # PIRQ
B+ AC or battery power rail for power circuit. N/A N/A N/A
No PCI Device
+CPU_CORE Core voltage for CPU ON OFF OFF
+0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF
+VCCP VCCP switched power rail ON OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF
+1.8V 1.8V power rail for DDR ON ON OFF
+2.5VS 2.5V switched power rail ON OFF OFF
+3VALW 3.3V always on power rail ON ON ON*
+3VS 3.3V switched power rail ON OFF OFF
+5VALW 5V always on power rail ON ON ON*
+5VS 5V switched power rail ON OFF OFF
2 2
+VS VS always on power rail ON ON ON*
+RTCBATT RTC power ON ON ON
EC SM Bus1 address EC SM Bus2 address
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Device Address Device Address
Smart Battery 0001 011X b EMC1402 1001 100X b
EEPROM(24C16/02) 1010 000X b
SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Full ON HIGH HIGH HIGH ON ON ON ON
S1(Power On Suspend) HIGH HIGH HIGH ON ON ON LOW
S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF
S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF
S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF
3 3
ICH7M SM Bus address
BOARD ID Table(Page 25)
Device Address
ID BRD ID Ra Rb Vab
Clock Generator 1101 001Xb
0 R01 (SSI) NC 0 0V (SLG8SP556VTR)
1 R02 (ST) 100K 8.2K 0.25V DDR DIMMA 1010 000Xb
* 2 R10 (X build) 100K 18K 0.50V
3 R10A (MP) 100K NC 3.3V
4 4
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Security Classification Compal Secret Data Compal Electronics, Inc.
ho
Issued Date 2008/11/10 Deciphered Date 2009/11/10 Title
f@
Notes List
in
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
xa
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-5091P
he
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 22, 2009 Sheet 3 of 39
A B C D E
5 4 3 2 1
<6> H_A#[3..16]
<6> H_D#[0..15] H_D#[32..47] <6>
U5A U5B
H_A#3 P21 V19 H_ADS# +VCCP +VCCP H_D#0 Y11 R3 H_D#32
A[3]# ADS# H_ADS# <6> D[0]# D[32]#
H_A#4 H20 Y19 H_BNR# H_BNR# <6> H_D#1 W10 R2 H_D#33
H_A#5 A[4]# BNR# H_BPRI# H_D#2 D[1]# D[33]# H_D#34
N20 U21 H_BPRI# <6> Y12 P1
A[5]# BPRI# D[2]# D[34]#
1
1
H_A#6 R20 H_D#3 AA14 N1 H_D#35
A[6]# D[3]# D[35]#
0
GROUP
GROUP
ADDR
DATA GRP 0
H_A#7 J19 T21 H_DEFER# R201 R27 H_D#4 AA11 M2 H_D#36
A[7]# DEFER# H_DEFER# <6> D[4]# D[36]#
H_A#8 N19 T19 H_DRDY# H_DRDY# <6> 56_0402_5% 330_0402_5% H_D#5 W12 P2 H_D#37
H_A#9 A[8]# DRDY# H_DBSY# H_D#6 D[5]# D[37]# H_D#38
G20 Y18 H_DBSY# <6> AA16 J3
H_A#10 A[9]# DBSY# H_D#7 D[6]# D[38]# H_D#39
M19 Y10 N3
2
2
DATA GRP 2
H_A#11 A[10]# H_BR0# H_D#8 D[7]# D[39]# H_D#40
H21 T20 H_BR0# <6> Y9 G3
H_A#12 A[11]# BR0# H_D#9 D[8]# D[40]# H_D#41
L20 Y13 H2
A[12]# D[9]# D[41]#
CONTROL
H_A#13 M20 F16 H_IERR# H_D#10 W15 N2 H_D#42
H_A#14 A[13]# IERR# H_INIT#_R R33 1 H_D#11 D[10]# D[42]# H_D#43
K19 V16 2 1K_0402_5% H_INIT# <16> AA13 L2
D H_A#15 A[14]# INIT# H_D#12 D[11]# D[43]# H_D#44 D
J20 Y16 M3
A[15]# D[12]# D[44]#
H_A#16 L21
A[16]# LOCK#
W20 H_LOCK# H_LOCK# <6> Close to CPU H_D#13 W13
D[13]# D[45]#
J2 H_D#45
H_ADSTB#0 K20 H_D#14 AA9 H1 H_D#46
<6> H_ADSTB#0 ADSTB[0]# D[14]# D[46]#
T5 PAD H_AP0 D17 D15 H_RESET# H_RESET# <6> H_D#15 W9 J1 H_D#47
<6> H_REQ#[0..4] AP0 RESET# H_RS#[0..2] <6> D[15]# D[47]#
H_REQ#0 N21 W18 H_RS#0 <6> H_DSTBN#0 H_DSTBN#0 Y14 K2 H_DSTBN#2 H_DSTBN#2 <6>
H_REQ#1 REQ[0]# RS[0]# H_RS#1 H_DSTBP#0 DSTBN[0]# DSTBN[2]# H_DSTBP#2
J21 Y17 <6> H_DSTBP#0 Y15 K3 H_DSTBP#2 <6>
H_REQ#2 REQ[1]# RS[1]# H_RS#2 H_DINV#0 DSTBP[0]# DSTBP[2]# H_DINV#2
G19 U20 <6> H_DINV#0 W16 L1 H_DINV#2 <6>
H_REQ#3 REQ[2]# RS[2]# H_TRDY# H_DP#0 DINV[0]# DINV[2]# H_DP#2
P20 W19 H_TRDY# <6> T10 PAD V9 M4 PAD T15
H_REQ#4 REQ[3]# TRDY# DP#0 DP#2
R19 <6> H_D#[16..31] H_D#[48..63] <6>
REQ[4]# H_HIT# H_D#16 H_D#48
<6> H_A#[17..31] AA17 H_HIT# <6> AA5 C2
H_A#17 HIT# H_HITM# H_D#17 D[16]# D[48]# H_D#49
C19 V20 H_HITM# <6> Y8 G2
H_A#18 A[17]# HITM# H_D#18 D[17]# D[49]# H_D#50
F19 W3 F1
H_A#19 A[18]# BPM0# H_D#19 D[18]# D[50]# H_D#51
E21 K17 U1 D3
H_A#20 A[19]# BPM[0]# BPM1# H_D#20 D[19]# D[51]# H_D#52
A16 J18 W7 B4
A[20]# BPM[1]# D[20]# D[52]#
DATA GRP 1
H_A#21 D19 H15 BPM2# H_D#21 W6 E1 H_D#53
H_A#22 A[21]# BPM[2]# BPM3# H_D#22 D[21]# D[53]# H_D#54
C14 J15 Y7 A5
A[22]# BPM[3]# D[22]# D[54]#
ADDR GROUP 1
H_A#23 C18 K18 PRDY# H_D#23 AA6 C3 H_D#55
H_A#24 A[23]# PRDY# PREQ# H_D#24 D[23]# D[55]# H_D#56
DATA GRP 3
C20 J16 Y3 A6
H_A#25 A[24]# PREQ# ITP_TCK H_D#25 D[24]# D[56]# H_D#57
E20 M17 W2 F2
XDP/ITP SIGNALS
H_A#26 A[25]# TCK ITP_TDI H_D#26 D[25]# D[57]# H_D#58
D20 N16 V3 C6
H_A#27 A[26]# TDI ITP_TDO H_D#27