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D
MS-6526 Version 00A Title
Cover Sheet
Page
1
D
INTEL (R) Brookdale-G Chipset
Block Diagram 2
Willamette/Northwood 478pin mPGA-B Processor Schematics
Voltage Distribution 3
CPU: General SPEC 4
Willamette/Northwood mPGA-478B Processor Clock ICS950218AF & ATA100 IDE CONNECTORS 5
mPGA478-B INTEL CPU Sockets 6-7
System Brookdale-G Chipset: INTEL Brookdale-G GMCH -- North Bridge 8-10
INTEL GMCH (North Bridge) + INTEL ICH4 -- South Bridge 11-12
INTEL ICH4 (South Bridge) LPC I/O -- W83627HF-AW 13
C DDR DIMM1&2 and DDR Terminator Resistor 14-15 C
On Board Chipset: AGP Slot 16
BIOS -- FWH VGA Connector 17
AC'97 Codec -- ALC201A PCI SLOT 1 & 2 & 3 18
LPC Super I/O -- W83627HF-AW FWH & CNR 19
Clock Generation -- ICS950218AF USB Connectors 20
LAN -- RealTek RTL8101L AC'97 Codec ALC201A & Connectors 21-22
IO Connectors 23
Expansion Slots: FAN & 1.5V Votlage Regulator 24
W83302D ACPI Controller 25
B PCI2.2 SLOT * 3 B
VRM9.9 -- CPU Power 26
Front Panel & ATX Connectors 27
RealTek 8101L PCI Lan / MC97 Controller 28
Manual Parts 29
A A
MSI MICRO-STAR INT'L CO.,LTD.
Title
Cover Sheet
Size Document Number Rev
MS-6526 00A
Date: Wednesday, December 19, 2001 Sheet 1 of 29
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D BLOCK DIAGRAM D
Processor 478-PIN P4 PROCESSOR CK_408
VR
ADDR
CTRL
DATA
AGTL+ BUS
ADDR
CTRL
DATA
VGA
Connector
GMCH DDR266
Modules
C BROOKDALE-G C
AGP
Connector
IDE Primary
UDMA/100
PCI CONN 1
PCI CONN 2
PCI CONN 3
IDE Secondary PCI CNTRL
ICH4
PCI ADDR/DATA
USB PORT 1-6 USB
USB2.0
B PCI Lan B
CNR
Connector
FirmWare Hub AC'97 LINK
AC'97
CODEC
SIO
Keyboard
Floppy Game Port Serial 1 Serial 2 Parallel
A A
Mouse
MSI MICRO-STAR INT'L CO.,LTD.
Title
Block Diagram
Size Document Number Rev
MS-6526 00A
Date: Wednesday, December 19, 2001 Sheet 2 of 29
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Power Delivery Map
ATX P/S
with 1A Stby current
Processor
5VSB 5V 3.3V 12V -12V
+/-5% +/-5% +/-5% +/-5% +/-10% VCCVID
D VID voltage 1.2V
BG GMCH D
regulator 30mA VccCORE
1.5V
VccCORE/Vtt
2.46A
1.15V-1.75V
VRM 9/0 60A VccAGP
1.5V
370mA
VccHI
1.5V regulator 1.5V
90mA
VttFSB
2.5V regulator 1.15V-1.75V
2.4A
2.5V Standby VccSM
regulator 2.5V
2.8A
VccGPIO
C 3.3V C
1.25V regulator 30mA
Memory Vcca_DAC
1.5V
Vdd/Vddq 65mA
2.5V
5.92A
ICH4
1.5V Standby Vtt
regulator 1.25V
VccCORE
2.1A 1.5V
970mA
VccHI
1.5V
90mA
Vccsus1_5
1.5V
3.3V Standby 85mA
regulator
V_CPU_IO
B 1.15V-1.75V B
45mA
Vcc3_3
3.3V
610mA
Vccsus3_3
3.3V
70mA
CK-408
Vcc
3.3V
280mA
LPC Super I/O
Vdd
3.3V
25mA
A A
CNR Connector PCI Slot (per slot) AGP Slot FWH
USB
5V 1.0A 5V 5.0A 5V 2.0A Vdd
3.3V 1.0A 3.3V 7.6A 3.3V 6.0A Vdd 3.3V
MSI MICRO-STAR INT'L CO.,LTD.
12V 0.5A 12V 0.5A 12V 1.0A 5V 67mA
3.3Vaux 1.0A 3.3Vaux 0.375A 3.3Vaux 0.375A Title
2.0A
-12V 0.1A -12V 0.1A 1.5V 2.0A Power Delivery Map
5VDual 0.5A
Size Document Number Rev
MS-6526 00A
Date: Wednesday, December 19, 2001 Sheet 3 of 29
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General SPEC
ICH4 FWH
GPIO Pin Type Function
GPIO Pin Type Function
GPIO 0 I REQ#A (multifunction pin)
D
GPI 0 I Pull down through 8.2K ohms (unused) D
GPIO 1 I REQ#B (multifunction pin)
GPI 1 I Pull down through 8.2K ohms (unused)
GPIO 2 I Pull up through 8.2K ohms (PIRQE#)
GPI 2 I P1 customer defined
GPIO 3 I Pull up through 8.2K ohms (PIRQF#)
GPI 3 I P1 customer defined
GPIO 4 I Pull up through 8.2K ohms (PIRQG#)
GPI 4 I Pull down through 8.2K ohms (unused)
GPIO 5 I Pull up through 8.2K ohms (PIRQH#)
GPIO 6 I Pull down through 10K ohms (unused)
GPIO 7 I Pull down through 10K ohms (unused) PCI Config.
GPIO 8 I Pull Up to 3.3VSBY through 4.7K ohms (SIO_PME)
DEVICE ICH INT Pin IDSEL CLOCK CLK GEN PIN OUT
GPIO 9 I Not Implemented
PCI Slot 1 INTA# AD16 PCICLK0 10 (PCI3/FS4)
GPIO 10 I Not Implemented INTB#
INTC#
GPIO 11 I SMB_ALERT (multifuntion pin) INTD#
GPIO 12 I Pull down through 10K ohms (unused) PCI Slot 2 INTB# AD17 PCICLK1 11 (PCI4)
INTC#
GPIO 13 I Pull down through 10K ohms (unused) INTD#
INTA#
GPIO 14~15 I Not Implemented
C PCI Slot 3 INTC# AD18 PCICLK2 12 (PCI5) C
GPIO 16 O GNT#A (multifunction pin) INTD#
INTA#
GPIO 17 O GNT#B (multifuntion pin) INTB#
GPIO 18* O No Connected PCI LAN INTG# AD29 LAN_PCLK 17 (PCI9)
INTF#
GPIO 19 O No Connected
*ICH4 reserved PCI address line AD22 for the PCI-to-ISA Bridge's IDSEL input.
GPIO 20 O No Connected
GPIO 21 O No Connected
GPIO 22 OD No Connected
GPIO 23 O Pull Up to 3.3V through 8.2K ohms (BIOS protect)
DIMM Config.
DEVICE ADDRESS CLOCK
GPIO 24 I/O No Connected
DIMM 1 1010000B DCLK0/DCLK0#
GPIO 25 I/O No Connected DCLK1/DCLK1#
DCLK2/DCLK2#
GPIO 26 I/O Not Implemented
DIMM 2 1010001B DCLK3/DCLK3#
GPIO 27 I/O No Connected DCLK4/DCLK4#
DCLK5/DCLK5#
GPIO 28 I/O No Connected
GPIO 29~31 O Not Implemented
B B
GPIO 32 I/O No Connected
GPIO 33 I/O No Connected
GPIO 34 I/O Primary IDE ATA66/100 detection (PD_DET)
GPIO 35 I/O Secondary IDE ATA66/100 detection (SD_DET)
GPIO 36 I/O No Connected
GPIO 37 I/O No Connected
GPIO 38 I/O No Connected
GPIO 39 I/O No Connected
GPIO 40 I/O No Connected
GPIO 41 I/O No Connected
GPIO 42 I/O No Connected
GPIO 43 I/O No Connected
GPIO 44~47 I/O Not Implemented
* GPIO18 will toggle at 1Hz frequency.
A A
MSI MICRO-STAR INT'L CO.,LTD.
Title
General SPEC
Size Document Number Rev
MS-6526 00A
Date: Wednesday, December 19, 2001 Sheet 4 of 29
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CLOCK GENERATOR BLOCK *Trace < 0.5"
CP18 X_COPPER Shut Source Termination Resistors Pull-Down Capacitors
U1 CPUCLK R1 49.9_1%
FB1 X_80_0805 VCC3V 39 41 CPU0 R2 27.4_1% CPUCLK CPUCLK# R3 49.9_1% CPUCLK C1 X_10p
VCC3 CPU_VDD CPUCLK0 CPUCLK (6)
40 CPU0# R4 27.4_1% CPUCLK# MCHCLK R5 49.9_1%
CPUCLK0# CPUCLK# (6)
CB1 CB195 CB273 CB274 CB2 MCHCLK# R7 49.9_1% CPUCLK# C2 X_10p
0.1u 0.1u 10u-0805 0.1u 0.1u 36 38 CPU1 R10 27.4_1% MCHCLK
CPU_GND CPUCLK1 MCHCLK (8)
37 CPU1# R12 27.4_1% MCHCLK# MCHCLK C3 X_10p
CPUCLK1# MCHCLK# (8)
filtering from 10K~1M Trace less 0.2"
46 MCHCLK# C4 X_10p
MREF_VDD
D
* Put GND copper under Clock Gen. CB3 CPUCLK2 45
RN84 33 49.9ohm for 50ohm M/B impedance D
44
connect to every GND pin 0.1u 43
CPUCLK2#
1 2 MCH_66
MCH_66 (8)
CN10
MREF_GND ICH_66
* 40 mils Trace on Layer 4 3 4
AGPCLK
ICH_66 (12) CLOCK STRAPPING RESISTORS AGPCLK
2 1
32 31 5 6 AGPCLK (16) 4 3
with GND copper around 3V66_VDD 3V66_0
30 7 8 ICH_66 6 5
CB4 3V66_1 FS0 R740 X_10K VCC3V MCH_66
it 0.1u 3V66_2 28
SEL48_2 SIO_48
8 7
29 3V66_GND 3V66_48/SEL66_48# 27 SIO_48 (13)
* put close to every power pin R589 33 FS1 R18 8.2K VCC3V X_10p
* 6 FS2 CN14
FS2/PCI0 FS3 R22 1.5K
Trace Width 7mils. 9 PCI_VDD FS3/PCI1 7
SEL48_1
BSEL0 (6,8)
PCICLK0
7 8
* CB5 SEL48_24#/PCI2 8
PCICLK1
5 6
Same Group spacing 15mils 0.1u FS4
7
RN85 5
8
PCICLK0 PCICLK2
3 4
* 5 PCI_GND FS4/PCI3 10
33
6
PCICLK1
PCICLK0 (18)
RN75
1 2
Different Group spacing 30mils PCI4 11 3 4
PCICLK2
PCICLK1 (18)
SEL48_1 VCC3V X_10p
* 18 PCI_VDD PCI5 12 1 2
LAN_PCLK
PCICLK2 (18)
FS3
1 2
CN11
Differentical mode spacing 7mils on itself CB6 PCI6 14
RN2 5
7 8
SIO_PCLK
LAN_PCLK (28)
FS2
3 4
LAN_PCLK
PCI7 15 6 SIO_PCLK (13) 5 6 2 1
0.1u 13 16 33 3 4 FWH_PCLK FS4 7 8 SIO_PCLK 4 3
PCI_GND PCI8 FWH_PCLK (19)
17 1 2 ICH_PCLK FWH_PCLK 6 5
PCI9 ICH_PCLK (11)
X_10K ICH_PCLK 8 7
24 48_VDD
CP19 X_COPPER C24 22 FS0 R26 33 ICH_48
FS0/48MHz ICH_48 (12)
0.01u 23 FS1 R27 33 DOT_CLK SEL48_2 R741 10K ICH_14 C16 10p
X_10p
FS1/24_48MHz DOT_CLK (8)
21 48_GND SIO_48 C376 10p
FB2 X_80_0805 VDDA3V 2
VCC3 REF_VDD
C26 48 MUL0 R25 33 ICH_14 ICH_48 C20 10p
MUL0/REF0 ICH_14 (12)
C CB7 CB275 0.01u 1 MUL1 MUL0 R742 10K MUL0=0 C
0.1u 4.7u-0805 MUL1/REF1 DOT_CLK C21 10p
47 REF_GND
MUL1=1
MUL1 R871 X_10K
34 3 X1 C23 10p Ioh=6*Iref
C27 CORE_VDD X1
0.01u X1 14M-32pf-HC49S-D
Voh=0.71V
33 4 X2 C25 10p used only for EMI issue
CORE_GND X2
SMBCLK_ISO 26 35 R28 475_1% Iref = 2.32mA Trace less 0.2"
(13,14,19,24,25) SMBCLK_ISO SCLK IREF
SMBDATA_ISO25
(13,14,19,24,25) SMBDATA_ISO SDATA
RESET# 20 FS4 FS3 FS2 FS1 FS0 FSB (MHz)
R30 1K 19 42 PWR_DN# R590 1K VCC3V
VCC3 VTT_GD# PWR_DN#
1 1 1 0 1 100 MHz
ICS950218AF
R35 220 Q1 R39
VCCP VCC3 VCC3 VCC3 VCC3
1 1 1 1 1 133 MHz
3904 X_1K
R512 X_10K
VCC3
R513
Q2 CB312 CB313 CB314 CB315 SMBCLK_ISO R29 4.7K
(6) SKTOCC# VCC3
X_3904 0.1u 0.1u 0.1u 0.1u SMBDATA_ISO R32 4.7K
X_220
ATA100 IDE CONNECTORS
PRIMARY IDE BLOCK SECONDARY IDE BLOCK * Trace Width : 5mils
B * Trace Spacing : 7mils B
* Length(longest)-Length(shortest)<0.5"
* Trace Length less than 5"
IDE1 IDE2
YJ220-CB-1 YJ220-CW-1
HD_RST# R43 33 1 2 HD_RST# R44 33 1 2
(25) HD_RST#
PDD7 3 4 PDD8 SDD7 3 4 SDD8
(12) PDD[0..7] PDD[8..15] (12) (12) SDD[0..7] SDD[8..15] (12)
PDD6 5