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1
Cover Sheet, Block diagram 1-2
Intel LGA775 CPU - Signals
Intel LGA775 CPU - Power
3
4 MS-7046M1 Version 10A
Intel LGA775 CPU- GND 5 Intel (R) Grantsdale (GMCH) + ICH6 Chipset
Intel Tejas & Prescott LGA775 Processor
Intel Grantsdale - CPU 6
Intel Grantsdale - Memory 7
CPU:
Intel Grantsdale - PCI Express 8
Intel Tejas/Prescott - 3.8G
Intel Grantsdale - GND 9 System Chipset:
ICH6 10-12 Intel Grantsdale - GMCH (North Bridge)
CLOCK - ICS954119 13
Intel ICH6 (South Bridge)
LPC I/O - WINBOND83627THF KB/MS 14 On Board Chipset:
FWH/FAN/SERIAL-ATA 15 BIOS -- FWH FLASH 4Mb
Collected by: Azalia Codec -- C MEDIA 9880/9882 CO-LAYOUT
LAN-VIA 6105L 16 Digitally signed by fdsf
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LPC Super I/O -- WINBOND83627THF
IEEE1394-VIA6307 17 DN: cn=fdsf, o=fsdfsd,
A
LAN - VIA 6105L A
ou=ffsdf,
IDE RAID-VIA6410 18 1394 -- VIA VT-6307
email=fdfsd@fsdff, c=US
Azalia CODEC-CMI9880 19 Date: 2009.10.09CLOCK -- ICS954119
07:25:18 +07'00'
PCI EXPRESS X 16 20 Main Memory:
DDR1 DIMM 1 , 2 , 3 & 4 21-23 2 CHANNEL DDR I * 4 (Max 4GB)
PCI SLOT 1 & 2 & 3 24
Expansion Slots:
ATX & Front Panel & IDE CONNECTOR 25
PCI Express X16 SLOT * 1
USB Connectors 26 PCI 2.3 SLOT * 3
MS7 ACPI Controller 27
VRM 10 - Intersil HIP 6561 3 phase 28-29 Intersil PWM:
GPIO & JUMPER SETTING 30 Controller: HIP6565ACV
Manual Parts & Power Delivery 31 Driver: HIP6602B + HIP6601B
Revision History 32 MSI MICRO-STAR INt'L CO., LTD.
Title
COVER SHEET
Size Document Number Rev
10A
MS-7046M1
Date: Thursday, May 27, 2004 Sheet 1 of 30
1
1
VRM_GD
VTT_PWG
VRM 10.1
Intersil 6561 Intel LGA775 Processor Block Diagram
VID_GD
3-Phase PWM
P.3~5
P.28
2 DDR1
FSB
H_CPURST#
H_PWRGD PWR_GD
CHANNEL A DIMM RSMRST#
Modules
PCI MS7 HD_RST#
PCIRST#1 EXPRESS
X16 P.20
Connector
Grantsdale-G
P.15
2 DDR1 PCIRST#1
Analog PCIRST#2
DIMM
Video CHANNEL B
Modules
Out P.6~9
P.19 UltraDMA
33/66/100 P.21
PLRST#
IDE Primary
DMI
HD_RST# PWR_GD
VRM_GD
P.18
IDE Primary PCIRST_ICH6#
P.18
SLP_S4#
PCI Slot 1
PCI Slot 2
PCI Slot 3
SERIAL ATA1
ICH6
P.18
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PCI
SERIAL ATA2
A
P.18 A
SLP_S3#
P.10~12
PWR_OK
USB2.0 USB
USB Port0~ 7
LPC Bus
PCIRST#2
ATX1 P.23 P.23 P.15
P.25 RSMRST#
LPC SIO
C MEDIA
W83627THF
Azalia Codec
P.16
P.14
LAN
VT6105L
P.17
PCIRST#1 PCI
1394 FWH Keyboard Floopy Parallel Serial
VIA VT-6307
P.30 P.14 P.14 P.18 P.18
P.26 SW_ON# FP_RST# Mouse
P.14
JFP1 PCIRST_ICH6#
MSI MICRO-STAR INt'L CO., LTD.
Title
BLOCK DIAGRAM
Size Document Number Rev
10A
MS-7046M1
Date: Thursday, May 27, 2004 Sheet 2 of 30
1
8 7 6 5 4 3 2 1
VID Pull-Up Resistor
R554 X_0/0402 FP_RST#
FP_RST# 11,24
CPU SIGNAL BLOCK VCC_VRM_SENSE VCC_VRM_SENSE 27 VTT_OUT_RIGHT
VSS_VRM_SENSE VSS_VRM_SENSE 27 RN15
8P4R-680
H_VID[0..5] 27 H_VID3 1 2
D H_VID1 3 4 D
H_VID2 5 6
6 H_A#[3..31] H_VID4 7 8
FP_RST_R#
H_VID0 R442 680/0402
TP_VID6
H_VID0
H_VID5
H_VID4
H_VID3
H_VID2
H_VID1
H_VID5 R443 680/0402
H_A#10
H_A#31
H_A#30
H_A#29
H_A#28
H_A#27
H_A#26
H_A#25
H_A#24
H_A#23
H_A#22
H_A#21
H_A#20
H_A#19
H_A#18
H_A#17
H_A#16
H_A#15
H_A#14
H_A#13
H_A#12
H_A#11
H_A#8
H_A#7
H_A#6
H_A#5
H_A#4
H_A#3
H_A#9
AM5
AM3
AM2
AG5
AG4
AG6
AH5
AH4
AC5
AD6
AC2
AN3
AN4
AN5
AN6
AB4
AB5
AA5
AA4
AB6
AK3
AK4
AF4
AF5
AL4
AL6
AL5
AJ6
AJ5
AJ3
W6
W5
M4
M5
U4
U5
U6
R4
CPU_GTLREF
Y4
Y6
V4
V5
P6
T4
T5
L4
L5
CPU_GTLREF 4
U1A H_TRST# R531 49.9RST/0402
A35#
A34#
A33#
A32#
A31#
A30#
A29#
A28#
A27#
A26#
A25#
A24#
A23#
A22#
A21#
A20#
A19#
A18#
A17#
A16#
A15#
A14#
A13#
A12#
A11#
A10#
A9#
A8#
A7#
A6#
A5#
A4#
A3#
DBR#
RSVD
RSVD
VCC_SENSE
VSS_SENSE
ITP_CLK1
ITP_CLK0
RSVD
VID5#
VID4#
VID3#
VID2#
VID1#
VID0#
H_DBI#0 A8 H_TCK R535 49.9RST/0402
6 H_DBI#[0..3] DBI0#
H_DBI#1 G11 H_TMS R534 49.9RST/0402
H_DBI#2 DBI1#
D19
H_DBI#3 DBI2# RN21 1 VTT_OUT_RIGHT
C20 H1 2 8P4R-51/0402
DBI3# GTLREF H_TDO 3 4
6 H_EDRDY# F2 5 6
EDRDY# H_TDI
4 H_IERR# AB2 7 8
IERR# H_BPM#5
AB3 AG3
MCERR# BPM5# H_BPM#4
4,10 H_FERR# R3 AF2
FERR#/PBE# BPM4# H_BPM#3 RN22 7 C395 104P
10 H_STPCLK# M3 AG2 8
STPCLK# BPM3# H_BPM#2
AD3 AD2 5 6
BINIT# BPM2# H_BPM#1 C397 104P
10 H_INIT# P3 AJ1 3 4
INIT# BPM1# H_BPM#0
H4 AJ2 1 2
RSP# BPM0# 8P4R-51/0402
B2 G5 H_PCREQ#
6 H_DBSY# DBSY# PCREQ# H_PCREQ# 6
C C1 J6 H_REQ#4 C
6 H_DRDY# DRDY# REQ4# H_REQ#[0..4] 6
E3 K6 H_REQ#3
6 H_TRDY# TRDY# REQ3#
M6 H_REQ#2
REQ2# H_REQ#1
6 H_ADS# D2 J5
ADS# REQ1# H_REQ#0
6 H_LOCK# C3 K4
LOCK# REQ0#
6 H_BNR# C2
BNR# H_TESTHI12 R11 62/0402 VTT_OUT_LEFT
6 H_HIT# D4 W2 VTT_OUT_LEFT 4
HIT# TESTHI12 H_TESTHI11 H_TESTHI10 7
6 H_HITM# E4 P1 8
HITM# TESTHI11 H_TESTHI10 H_TESTHI11 5
6 H_BPRI# G8 H5 6
BPRI# TESTHI10 H_TESTHI9 H_TESTHI9 3
6 H_DEFER# G7 G4 4
DEFER# TESTHI9 H_TESTHI8 H_TESTHI8 1
G3 2
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H_TDI TESTHI8 RN23 8P4R-62/0402
AD1 F24
H_TDO TDI TESTHI7
AF1 G24
H_TMS TDO TESTHI6
AC1 G26
H_TRST# TMS TESTHI5
AG1 G27
10/10 parallel H_TCK TRST# TESTHI4
AE1 G25
TCK TESTHI3 H_TESTHI2_7 R16 62/0402 V_FSB_VTT
14 CPU_TMPA AL1 F25 V_FSB_VTT 4,6,8,12,13,26,27
THERMDA TESTHI2 H_TESTHI1 R17 62/0402 VTT_OUT_LEFT
14 VTIN_GND AK1 W3
THERMDC TESTHI1 H_TESTHI0 R18 62/0402 V_FSB_VTT
4,10,14 TRMTRIP# M2 F26
THERMTRIP# TESTHI0 RSVD_AK6 R19 X_62/0402 VTT_OUT_RIGHT
AE8 AK6
GND/SKTOCC# RSVD RSVD_G6 R20 X_62/0402 VTT_OUT_LEFT VTT_OUT_RIGHT 4
4 H_PROCHOT# AL2 G6
PROCHOT# RSVD
10 H_IGNNE# N2
IGNNE#
10 ICH_H_SMI# P2 G28 CK_H_CPU# 13
SMI# BCLK1#
10 H_A20M# K3 F28 CK_H_CPU 13
A20M# BCLK0#
10 H_SLP# L2
SLP# H_RS#2
A3 H_RS#[0..2] 6
RS2# H_RS#1
AH2 F5
RSVD RS1# H_RS#0
N5 B3
RESERVED0 RS0#
B AE6 B
RESERVED1
C9 U3
RESERVED2 AP1#
G10 U2
C1 X_104P RESERVED3 AP0#
D16 F3 H_BR#0 4,6
RESERVED4 BR0#
A20
R22 RESERVED5 H_COMP3 R21 100RST/0402 VTT_OUT_LEFT
R1
VTT_OUT_RIGHT X_1K/0402 CPU_BOOT Y1 COMP3 H_COMP2 R23 100RST/0402
G2
LL_ID0 BOOTSELECT COMP2 H_COMP1 R24 60.4RST/0402
27 LL_ID0 V2 T1
TP_LL_ID1 LL_ID0 COMP1 H_COMP0 R25 60.4RST/0402 C2
AA2 A13
LL_ID1 COMP0 X_104P
4,8,13 H_FSBSEL0 G29 J17
BSEL0 DP3# PLACE RESISTORS OUTSIDE SOCKET
4,8,13 H_FSBSEL1 H30 H16
BSEL1 DP2#
4,8,13 H_FSBSEL2 G30 H15 CAVITY IF NO ROOM FOR VARIABLE
BSEL2 DP1#
J16
DP0# RESISTOR DON'T PLACE
4,10 H_PWRGD N1
PWRGOOD
AD5 H_ADSTB#1 6
ADSTB1#
4,6 H_CPURST# G23 R6 H_ADSTB#0 6
RESET# ADSTB0#
C17 H_DSTBP#3 6
H_D#63 DSTBP3#
6 H_D#[0..63] B22 G19 H_DSTBP#2 6
H_D#62 D63# DSTBP2#
A22 E12 H_DSTBP#1 6
H_D#61 D62# DSTBP1#
A19 B9 H_DSTBP#0 6
H_D#60 D61# DSTBP0#
B19 A16 H_DSTBN#3 6
H_D#59 D60# DSTBN3#
B21 G20 H_DSTBN#2 6
H_D#58 D59# DSTBN2#
C21 G12 H_DSTBN#1 6
H_D#57 D58# DSTBN1#
B18 C8 H_DSTBN#0 6
H_D#56 D57# DSTBN0#
A17
H_D#55 D56#
B16 L1 H_NMI 10
H_D#54 D55# LINT1/NMI
C18 K1 H_INTR 10
D54# LINT0/INTR
D53#
D52#
D51#
D50#
D49#
D48#
D47#
D46#
D45#
D44#
D43#
D42#
D41#
D40#
D39#
D38#
D37#
D36#
D35#
D34#
D33#
D32#
D31#
D30#
D29#
D28#
D27#
D26#
D25#
D24#
D23#
D22#
D21#
D20#
D19#
D18#
D17#
D16#
D15#
D14#
D13#
D12#
D11#
D10#
D9#
D8#
D7#
D6#
D5#
D4#
D3#
D2#
D1#
D0#
A A
G22
G21
G17
G18
G16
G15
G14
G13
C14
C15
D17
D20
D22
D13
D10
D11
C12
C11
B15