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A B C D E
1 1
QIQY5
2
Whisky3.0 (Y490) 2
LA-8691P Rev0.2 Schematic
Intel IVY Bridge Processor with DDRIII + Panther Point PCH
3
nVIDIA N13P GT1-A2 + 2nd VGA N13P GT1-A2 3
2012-02-05 Rev0.2
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/11/01 Deciphered Date 2012/12/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Y490-LA8691P
Date: Tuesday, March 20, 2012 Sheet 1 of 65
A B C D E
A B C D E
PCI-Express 16X Gen3
PEG 8~15 PEG 0~7
Intel CPU
Ivy Bridge Memory BUS (DDRIII) DDR3-SO-DIMM X2
2nd VGA, N13P-GT1 N13P-GT1 Dual Channel
1 BANK 0, 1, 2, 3 1
VRAM 64*32 VRAM 64*32
rPGA-989
1.5V DDRIII 1066/1333/1600 MT/s
GDDR5* 8 GDDR5* 8 37.5mm*37.5mm UP TO 16G
Sub/B Page 32 Page 23,24,25,26,27,28,29,30,31
Page 5,6,7,8,9,10,11
FDI *8 DMI *4
2.7GT/s 5GT/s
HDMI Conn. CRT Conn. LVDS Conn. USB Left USB Right
Page 36 Page 35 Page 34 USB 2.0 4x
USB 2.0 Port 2 USB 2.0 Port 9
HDMI1.4b 5V 480MHz USB 3.0 Port 2 USB 2.0 Port 5, Cha
Page 48 Sub/B Page 49
2
Intel PCH USB 3.0 2x Int. Camera BT
2
5V 5GT/s USB 3.0 Port 0 USB 2.0 Port 13
Atheros Panther Point Page 34 Page 47
PCIe Gen1 1x
RJ45 Conn. AR8161 1G 1.5V 5GT/s
Page 39
AR8151 1G
PCIe port 1 Page 38 USB 2.0 1x
PCIeMini Card mSATA SSD
FCBGA-989 Balls 5V 480MHz
WLAN
PCIe Port 2 SATA Port 0
25mm*25mm PCIe Gen1 1x page 37 page 37
CardReader 5V 480MHz
PCIe Gen1 1x PCIeMini Card
JMB38C 1.5V 5GT/s WLAN
SATA Gen3 Port 0 USB Port 10
SD/MMC/MS/XD 5V 6GHz(600MB/s) page 37
PCIe port 4 Page 44
SATA Gen3 Port 1 SATA HDD
5V 6GHz(600MB/s) SATA Port 1
3
SPI ROM SPI BUS page 41 3
(4MB+2MB) 3.3V 33MHz
Page 14 SATA Gen1 Port2 SATA ODD
Page 14,15,16,17,18,19,20,21,22 5V 3GHz(300MB/s) SATA Port 1
page 41
HD Audio
LPC BUS
3.3V 33MHz
3.3V 24MHz
Debug Port EC Codec AMP
SPK Conn.
Page 45 ITE IT8580E-HX ALC269Q-VC3 MAX98400B Page 43
Page 42 Page 43
Page 45
Power Circuit DC/DC
Page 52,53,54,55,56,57,
58,59,60,61,62
4 DC/DC Interface CKT. RTC CKT. Thermal Sensor Int. MIC Conn. 4
Page 51 Page 52 Touch Pad Int.KBD Ext. MIC Conn. HP Conn.
(JCMOS Conn.)
EMC 1403 Page 34 Page 49 Page 49
Page 46 Page 46 Page 40 Sub/B Sub/B
POWER/B Conn. AUDIO, USB/B Conn.
Page 40 Page 49 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/11/01 Deciphered Date 2012/12/31 Title
Block Diagram
ODD/B Conn. NOVO/B Conn. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
page 41 Page 40 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Y490-LA8691P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 20, 2012 Sheet 2 of 65
A B C D E
A B C D E
Voltage Rails ( O --> Means ON , X --> Means OFF )
SIGNAL
+5VS STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
+3VS
Power Plane Full ON HIGH HIGH HIGH HIGH ON ON ON ON
+1.5VS
+VCCSA S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
1
+V1.5S_VCCP 1
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
+CPU_CORE
+3VALW
+VGA_CORE S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
B+ +1.5V
+GFX_CORE
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+5VALW +1.8VS
+1.05VS
State +0.75VS
+3.3VS_VGA
+1.5VS_VGA
+1.05VS_VGA
USB Port Table BOM Structure Table
4 External BOM Structure BTO Item
USB 2.0 USB 3.0 Port USB Port
HDMI@ HDMI part
S0 O O O O Camera
1 0
XHCI 1 CHG@ USB charger part
2 NOCHG@ No USB charger part
S3 O O O X EHCI1
2 USB Port (Left Side) CMOS@ CMOS Camera part
3
2 3 8161@ AR8161 LAN part 2
4 8151@ AR8151 LAN part
S5 S4/AC Only O O X X 4
8161S@ AR8161 LAN surge part
5 USB Port (Right Side) AR8151 LAN surge part
8151S@
6
S5 S4 SURGE@ AR8151&8161 LAN surge part
Battery only O X X X 7
61@ X76 P/N for AR8161
EHCI2 8 51@ X76 P/N for AR8151
9 USB Port (Right Side) X76@ X76 Level part for VRAM
S5 S4 10 Mini Card(WLAN)
GC6@ NV CG6 support part
AC & Battery X X X X 11
NOGC6@ NV no CG6 support part
12 AOAC@ AOAC support part
don't exist Blue Tooth
13 KBL@ K/B Light part
ME@ ME part
SMBUS Control Table OPT@ For optimus function part
Main 2nd WLAN Thermal PCH TP PCIE PORT LIST SLI@ For SLI function part
SOURCE VGA VGA BATT IT8580E SODIMM WiMAX Sensor Module DS3@ Deep S3 support part
Port Device
3 S3@ For S3 function part 3
1 LAN GT@ NV chip part
EC_SMB_CK1 IT8580E
X X V X X X X X X 2 WLAN @ Unpop
EC_SMB_DA1 +3VALW
+3VALW 3
4 Card Reader
EC_SMB_CK2 IT8580E
EC_SMB_DA2 +3VS
V V X X X X V V X 5
+3VS +3VS +3VS +3V_PCH 6
7
SMB_CLK_S3 PCH
SMB_DATA_S3 +3VS
X X X X V V X V V 8
+3VS +3VS +3V_PCH +3VS
Address
EC SM Bus1 address EC SM Bus2 address PCH SM Bus address ZZZ1
4 4
Device Device Address Device Address
Smart Battery 0001 011X b Thermal Sensor EMC1403-2 1001_101xb DDR DIMM0 1001 000Xb
DA80000T10J
Master VGA 0x9E DDR DIMM2 1001 010Xb
Slave VGA 0x9C
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/11/01 Deciphered Date 2012/12/31 Title
Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Y490-LA8691P
Date: Tuesday, March 20, 2012 Sheet 3 of 65
A B C D E
5 4 3 2 1
Hot plug detect for IFP link E
Performance Mode P0 TDP at Tj = 102 C* (GDDR5)
FBVDDQ PCI Express I/O and I/O and Other
VGA and GDDR5 Voltage Rails (N13Px GPIO) GPU Mem NVCLK FBVDD (GPU+Mem) (1.05V) PLLVDD PLLVDD
(4) (1,5) /MCLK NVVDD (1.35V) (1.35V) (6) (1.8V) (1.05V) (3.3V)
GPIO I/O ACTIVE Function Description Products (W) (W) (MHz) (V) (A) (W) (A) (W) (A) (W) (mA) (W) (mA) (W) (mA) (W) (mA) (W)
GPIO0 OUT - GPU VID4 N13X
128bit TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
D
1GB D
GPIO1 OUT - GPU VID3 GDDR5
GPIO2 OUT - VGA_BL_PWM Physical Logical Logical Logical Logical
Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
GPIO3 OUT - VGA_ENVDD ROM_SCLK +3VS_VGA PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG PEX_PLL_EN_TERM
GPIO4 OUT - VGA_ENBKL ROM_SI +3VS_VGA RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
ROM_SO +3VS_VGA FB[1] FB[0] SMB_ALT_ADDR VGA_DEVICE
GPIO5 OUT - GPU VID1
STRAP0 +3VS_VGA USER[3] USER[2] USER[1] USER[0]
GPIO6 OUT - GPU VID2 STRAP1 +3VS_VGA 3GIO_PAD_CFG_ADR[3] 3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1] 3GIO_PAD_CFG_ADR[0]
STRAP2 +3VS_VGA PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
GPIO7 OUT - DPRSLPVR_VGA
STRAP3 +3VS_VGA SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
GPIO8 I/O - Thermal Catastrophic Over Temperature STRAP4 +3VS_VGA RESERVED PCIE_SPEED_ PCIE_MAX_SPEED DP_PLL_VDD33V
CHANGE_GEN3
GPIO9 OUT - GPIO9
Device ID setting I2C Slave addrees ID
GPIO10 OUT - Memory VREF Control N13P-GT SMB_ALT_ADDR
(28nm) 0x0FDB 0 0x9E
(ROM_SO Bit 1)
GPIO11 OUT - GPU VID0
C C
1 0x9C
GPIO12 IN AC Power Detect Input (10K pull High)
GPIO13 OUT - GPU VID5
GPIO14 OUT - FB_CLAMP_TOGGLE_REQ#
GPU ROM_SO ROM_SCLK STRAP0 STRAP1 STRAP2 STRAP3 STRAP4
GPIO15 IN N/A (100K pull low)
PU 10K PU 25K PU 45K PD 35K PD 10K PU 5K PD 10K Master
GPIO16 OUT - FRMLCK# N13P-GT1
28nm PU 20K PU 25K PU 45K PD 35K PD 10K PD 5K PD 10K Slave
GPIO17 IN N/A
GPIO18 IN - dGPU_HDMI_HPD
GPIO19 IN - HPD_IRQ
GPU N13P-GT
FB Memory (GDDR5) ROM_SI
Samsung K4G10325FG-HC04
B
+3VS_VGA 2500MHz B
32Mx32 PD 45K
+VGA_CORE
Hynix H5GQ1H24BFR-T2C
tNVVDD >0 2500MHz
+1.5VS_VGA 32Mx32 PD 35K
tFBVDDQ >0
Samsung K4G20325FD-FC04
+1.05VS_VGA 2500MHz
tPEX_VDD >0 64Mx32 PD 30K
1. all power rail ramp up time should be larger than 40us
Hynix H5GQ2H24MFR-T2C
2500MHz
64Mx32 PD 25K
Other Power rail
+3VS_VGA
A A
Tpower-off <10ms
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/11/01 Deciphered Date 2012/12/31 Title
1.all GPU power rails should be turned off within 10ms
2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA Notes List
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Y490-LA8691P
Date: Tuesday, March 20, 2012 Sheet 4 of 65
5 4 3 2 1
5 4 3 2 1
D D
1. PEG_ICOMPI and RCOMPO signals should be shorted and routed with
a. max length = 500 mils
b. typical impedance = 43 mohms
2. PEG_ICOMPO signals should be routed with
+1.05VS a. max length = 500 mils
JCPU1A ME@ R1
J22 PEG_COMP 2 1 b. typical impedance = 14.5 mohms
PEG_ICOMPI J21
DMI_CRX_PTX_N0 B27 PEG_ICOMPO H22 24.9_0402_1%
<16> DMI_CRX_PTX_N0 DMI_RX#[0] PEG_RCOMPO
DMI_CRX_PTX_N1 B25
<16> DMI_CRX_PTX_N1 DMI_RX#[1]
DMI_CRX_PTX_N2 A25
<16> DMI_CRX_PTX_N2 DMI_RX#[2] PCIE_CRX_GTX_N[0..15] <23,32>
DMI_CRX_PTX_N3 B24 K33 PCIE_CRX_GTX_N0
<16> DMI_CRX_PTX_N3 DMI_RX#[3] PEG_RX#[0] M35 PCIE_CRX_GTX_N1
DMI_CRX_PTX_P0 B28 PEG_RX#[1] L34 PCIE_CRX_GTX_N2
<16> DMI_CRX_PTX_P0 DMI_RX[0] PEG_RX#[2]
DMI_CRX_PTX_P1 B26 J35 PCIE_CRX_GTX_N3 PEG Static Lane Reversal - CFG2 is for the 16x
<16> DMI_CRX_PTX_P1 DMI_RX[1] PEG_RX#[3]
DMI_CRX_PTX_P2 A24 J32 PCIE_CRX_GTX_N4
<16> DMI_CRX_PTX_P2
DMI
DMI_CRX_PTX_P3 B23 DMI_RX[2] PEG_RX#[4] H34 PCIE_CRX_GTX_N5
<16> DMI_CRX_PTX_P3 DMI_RX[3] PEG_RX#[5] H31 PCIE_CRX_GTX_N6 1: Normal Operation; Lane # definition matches
DMI_CTX_PRX_N0 G21 PEG_RX#[6] G33 PCIE_CRX_GTX_N7
<16> DMI_CTX_PRX_N0 DMI_TX#[0] PEG_RX#[7] CFG2 socket pin map definition
DMI_CTX_PRX_N1 E22 G30 PCIE_CRX_GTX_N8
<16> DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 F21 DMI_TX#[1] PEG_RX#[8] F35 PCIE_CRX_GTX_N9
<16> DMI_CTX_PRX_N2 D21 DMI_TX#[2] PEG_RX#[9] E34
DMI_CTX_PRX_N3 PCIE_CRX_GTX_N10 0:Lane Reversed
<16>
<16>
DMI_CTX_PRX_N3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P0 G22
D22
DMI_TX#[3]
DMI_TX[0]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
E32
D33
D31
PCIE_CRX_GTX_N11
PCIE_CRX_GTX_N12 *
DMI_CTX_PRX_P1 PCIE_CRX_GTX_N13
<16> DMI_CTX_PRX_P1 F20 DMI_TX[1] PEG_RX#[13] B33
DMI_CTX_PRX_P2 PCIE_CRX_GTX_N14
<16> DMI_CTX_PRX_P2 DMI_TX[2] PEG_RX#[14]
PCI EXPRESS* - GRAPHICS
DMI_CTX_PRX_P3 C21 C32 PCIE_CRX_GTX_N15
<16> DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15]
C PCIE_CRX_GTX_P[0..15] <23,32> C
J33 PCIE_CRX_GTX_P0
PEG_RX[0] L35 PCIE_CRX_GTX_P1
PEG_RX[1] K34 PCIE_CRX_GTX_P2
FDI_CTX_PRX_N0 A21 PEG_RX[2] H35 PCIE_CRX_GTX_P3
<16> FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 H19 FDI0_TX#[0] PEG_RX[3] H32 PCIE_CRX_GTX_P4
<16> FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 E19 FDI0_TX#[1] PEG_RX[4] G34 PCIE_CRX_GTX_P5
<16> FDI_CTX_PRX_N2 F18 FDI0_TX#[2] PEG_RX[5] G31
FDI_CTX_PRX_N3 PCIE_CRX_GTX_P6
<16> FDI_CTX_PRX_N3 FDI0_TX#[3] PEG_RX[6]
Intel(R) FDI
FDI_CTX_PRX_N4 B21 F33 PCIE_CRX_GTX_P7
<16> FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 C20 FDI1_TX#[0] PEG_RX[7] F30 PCIE_CRX_GTX_P8
<16> FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 D18 FDI1_TX#[1] PEG_RX[8] E35 PCIE_CRX_GTX_P9
<16> FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 E17 FDI1_TX#[2] PEG_RX[9] E33 PCIE_CRX_GTX_P10
<16> FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10] F32 PCIE_CRX_GTX_P11
PEG_RX[11] D34 PCIE_CRX_GTX_P12
FDI_CTX_PRX_P0 A22 PEG_RX[12] E31 PCIE_CRX_GTX_P13
<16> FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 G19 FDI0_TX[0] PEG_RX[13] C33 PCIE_CRX_GTX_P14
<16> FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 E20 FDI0_TX[1] PEG_RX[14] B32 PCIE_CRX_GTX_P15
<16> FDI_CTX_PRX_P2 G18 FDI0_TX[2] PEG_RX[15]
FDI_CTX_PRX_P3
<16> FDI_CTX_PRX_P3 B20 FDI0_TX[3] M29 1 2 PCIE_CTX_GRX_N[0..15] <23,32>
FDI_CTX_PRX_P4 PCIE_CTX_GRX_C_N0 C1 0.22U_0402_10V6K PCIE_CTX_GRX_N0
<16> FDI_CTX_PRX_P4 C19 FDI1_TX[0] PEG_TX#[0] M32 1 2
FDI_CTX_PRX_P5 PCIE_CTX_GRX_C_N1 C2 0.22U_0402_10V6K PCIE_CTX_GRX_N1
<16> FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 D19 FDI1_TX[1] PEG_TX#[1] M31 PCIE_CTX_GRX_C_N2 1 2 PCIE_CTX_GRX_N2
C3 0.22U_0402_10V6K
<16> FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 F17 FDI1_TX[2] PEG_TX#[2] L32 PCIE_CTX_GRX_C_N3 1