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A B C D E

ZZZ1

LA-6001P
DAZ0CG00100
1 1

Compal Confidential
2 2

NBLB3/5 Schematics Document
Intel Clarksfield Processor with DDRIII + Ibex HM55

2010-04-28
3 3

REV:1.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
SCHEMATIC,MB A6001
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401839 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, June 10, 2010 Sheet 1 of 59
A B C D E
A B C D E

Compal Confidential
Clock Gen.
Model Name : NBLB3/5 SLG8SP587
9LRS3199AKLFT
File Name : LA-6001P(Madison) page23

1 1

LVDS Conn.
page 22 VRAM 64M*16
DDR3*8 DDR3-SO-DIMM X2
page 18,19 PCI-Express Intel Mobile Clarkfield Dual Channel BANK 0, 1, 2, 3 page 11,12
ATI Madison /Arrandale
DDR3-1066/1333(1.5V)
uPGA989
Switch page5~10

Switch CRT
page 21

FDI*8 DMI*4
2
HDMI Switch 2

page 20 Level shift
Bluetooth CMOS Camera USB conn x4
Conn page 41 page 47 page 42

3.3V 48MHz USB
Intel Ibex Peak-M
3.3V 24.576MHz/48Mhz HD Audio
PCI-Express FCBGA 1071
PM55/HM55 S-ATA
Card Reader
page24~32 RTS5159
port 0 port 1 page 34

LAN(GbE) HDA Codec
MINI Card ALC272
page 44
WLAN RTL8111E
S-ATA HDD S-ATA ODD 3 in 1
3
page 37 page 35
LPC BUS Conn.page 33 Conn. page 33 socket 3

page 34

Audio AMP
RJ45 page 45
RTC CKT. page 36
page 43
EC
Conductive/B ENE KB926D3
Power USB/B page39 HP/MIC
Power On/Off CKT. EXT Jack
page 40
page 42 page 45

USB I/O Conn. Int.KBD
DC/DC Interface CKT. CIR Touch Pad page40
page41
page 48
LID SW BIOS
4 4
page41
Power Circuit DC/DC Debug port
page 42
page 48,49,50,52
53,54,55,56
TPM Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title

CHARGER LED SCHEMATIC,MB A6001
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
page 51 page 47 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401839 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, June 10, 2010 Sheet 2 of 59
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DDR3 Voltage Rails
1 1

EC SM Bus1 address EC SM Bus2 address
+5VS Device Address Device Address
power
+3VS Smart Battery 0001 011X b EMCI 1402 100_1100X b
plane
+1.5VS EEPROM(24C16/02) 1010 000X b NVIDIA N10P-GE1
+5VALW +CPU_CORE
+5VALW
+B +1.5V +VGA_CORE
+3VALW +1.8VS
Battery EEPROM
+0.75VS
State +1.05VS
+1.1VS_VTT SMB1 +3VALW
+1.5VS_VRAM +3VS
EC VGA Thermal
VGA PCH for thermal
Sensor Mornitor
2 2

S0 SMB2 2B7002
O O O O
S1
O O O O
+3VALW
S3 +3VALW
O O O X
S5 S4/AC DDR VREF WLAN1 New Card CLK_GEN
O O X X
S5 S4/ Battery only
O X X X 2B7002

S5 S4/AC & Battery SMB
don't exist X X X X
DDR VREF WLAN2 DIMMI1 DIMMI2

PCH
+3VALW
GPIO PIN Define
3 3

SML0
ID3 ID2 ID1 ID0
NBLB2(1100 ) R358 R361 R766 R765
For system
Reserve (1101 ) X X X X +3VALW +3VS thermal mornitor
Reserve (1110 ) X X X X
Reserve (1111 ) X X X X EC_SMB1
NBLB1 (0000 ) R353 R350 R766 R765
Reserve( 0001 ) X X X X SML1 2B7002
Reserve( 0010 ) X X X X
Reserve( 0011 ) X X X X
Reserve( 0100 ) X X X X
Reserve( 0101 ) X X X X
Reserve (0110 ) X X X X
Reserve (0111 ) X X X X
4 4
Reserve (1000 ) X X X X
Reserve (1001 ) X X X X
Reserve (1010 ) X X X X
Reserve (1011 ) X X X X
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
SCHEMATIC,MB A6001
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401839
Date: Thursday, June 10, 2010 Sheet 3 of 59
A B C D E
A B C D E

VGA (Madison)
+3VS_DELAY
power +1.8VS
plane +VGA_CORE
State +1.5VS_VRAM
+1.1VS

S0
1
O O 1
S1
O O
S3
S5 S4/AC
X X
S5 S4/ Battery only
X X
S5 S4/AC & Battery
X X
don't exist X X

47132_madison_ds_nda_1.04
Madison sequence
POWER UP/DOWN Sequence Power-Up/Down Sequence
Madison has the following requirements with regards to power supply sequencing to avoid damaging the ASIC.

1, All the ASIC supplies must fully reach their respective nominal voltages within 20 ms of the start of the ramp-up
sequence, though a shorter ramp-up duration is preferred.

2, VDDR3 should ramp-up before or simultaneously with VDDC.
2 2
3, For LVDS, DPx_VDD10 should ramp-up before DPx_VDD18 and the PCIe reference clock should begin before
DPx_VDD18. For power-down, DPx_VDD18 should ramp-down before DPx_VDD10.

4, The external pull-ups on the DDC/AUX signals (if applicable) should ramp-up before or after both VDDC and
VDD_CT have ramped up.

5, VDDC and VDD_CT should not ramp-up simultaneously. (e.g., VDDC should reach 90% before VDD_CT starts to
ramp-up (or vice versa).)

6, For power-down, reversing the ramp-up sequence is recommended.

t0>=0
3 3
(VDDR3) +3VS_DELAY

(VDDC) +VGA_CORE

+VDDCI

(VDDR1) +1.5VS_VRAM (DPX_PDD10) +1.0VS

(VDD_CT,DPX_PVDD,DPX_VDD18) +1.8VS

<=20ms <=20ms

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/24 Deciphered Date 2010/02/24 Title
SCHEMATIC,MB A6001
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401839
Date: Thursday, June 10, 2010 Sheet 4 of 59
A B C D E
5 4 3 2 1

JCPU1E

JCPU1A AJ13
PEG_IRCOMPR151 1 RSVD32
<26> DMI_PTX_HRX_N[0..3] PEG_ICOMPI B26 2 49.9_0402_1% RSVD33 AJ12
A26 R152 1 2 750_0402_1%
DMI_PTX_HRX_N0 PEG_ICOMPO
A24 DMI_RX#[0] PEG_RCOMPO B27 AP25 RSVD1
DMI_PTX_HRX_N1 C23 A25 EXP_RBIAS AL25 AH25
DMI_PTX_HRX_N2 DMI_RX#[1] PEG_RBIAS RSVD2 RSVD34
B22 DMI_RX#[2] AL24 RSVD3 RSVD35 AK26
DMI_PTX_HRX_N3 A21 K35 PCIE_GTX_C_MRX_N15 AL22
<26> DMI_PTX_HRX_P[0..3] DMI_RX#[3] PEG_RX#[0] RSVD4
J34 PCIE_GTX_C_MRX_N14 AJ33 AL26
DMI_PTX_HRX_P0 PEG_RX#[1] PCIE_GTX_C_MRX_N13 RSVD5 RSVD36
B24 DMI_RX[0] PEG_RX#[2] J33 PCIE_GTX_C_MRX_N[0..15] <13> AG9 RSVD6 RSVD_NCTF_37 AR2
DMI_PTX_HRX_P1 D23 G35 PCIE_GTX_C_MRX_N12 M27
DMI_RX[1] PEG_RX#[3] RSVD7

DMI
DMI_PTX_HRX_P2 B23 G32 PCIE_GTX_C_MRX_N11 L28 AJ26
DMI_RX[2] PEG_RX#[4] PCIE_GTX_C_MRX_P[0..15] <13> RSVD8 RSVD38
D DMI_PTX_HRX_P3 A22 F34 PCIE_GTX_C_MRX_N10 J17 AJ27 D
<26> DMI_HTX_PRX_N[0..3] DMI_RX[3] PEG_RX#[5] PCIE_GTX_C_MRX_N9
<11> H_DIMMA_REF RSVD9 (SA_DIMM_VREF) RSVD39
PEG_RX#[6] F31 <12> H_DIMMB_REF H17 RSVD10(SB_DIMM_VREF)
DMI_HTX_PRX_N0 D24 D35 PCIE_GTX_C_MRX_N8 G25
DMI_HTX_PRX_N1 DMI_TX#[0] PEG_RX#[7] PCIE_GTX_C_MRX_N7 RSVD11
G24 DMI_TX#[1] PEG_RX#[8] E33 PCIE_MTX_C_GRX_N[0..15] <13> G17 RSVD12
DMI_HTX_PRX_N2 F23 C33 PCIE_GTX_C_MRX_N6 E31 AP1
DMI_HTX_PRX_N3 DMI_TX#[2] PEG_RX#[9] PCIE_GTX_C_MRX_N5 RSVD13 RSVD_NCTF_40
<26> DMI_HTX_PRX_P[0..3] H23 DMI_TX#[3] PEG_RX#[10] D32 PCIE_MTX_C_GRX_P[0..15] <13> E30 RSVD14 RSVD_NCTF_41 AT2
B32 PCIE_GTX_C_MRX_N4
DMI_HTX_PRX_P0 PEG_RX#[11] PCIE_GTX_C_MRX_N3
D25 DMI_TX[0] PEG_RX#[12] C31 RSVD_NCTF_42 AT3
DMI_HTX_PRX_P1 F24 B28 PCIE_GTX_C_MRX_N2 AR1
DMI_HTX_PRX_P2 DMI_TX[1] PEG_RX#[13] PCIE_GTX_C_MRX_N1 RSVD_NCTF_43
E23 DMI_TX[2] PEG_RX#[14] B30
DMI_HTX_PRX_P3 G23 A31 PCIE_GTX_C_MRX_N0
DMI_TX[3] PEG_RX#[15]
J35 PCIE_GTX_C_MRX_P15 R153 AL28
PEG_RX[0] PCIE_GTX_C_MRX_P14 3.01K_0402_1% RSVD45
<26> FDI_CTX_PRX_N[0..7] PEG_RX[1] H34 1 @ 2 CFG0 AM30 CFG[0] RSVD46 AL29
H33 PCIE_GTX_C_MRX_P13 CFG1 AM28 AP30
FDI_CTX_PRX_N0 PEG_RX[2] PCIE_GTX_C_MRX_P12 R154 CFG2 CFG[1] RSVD47
E22 FDI_TX#[0] PEG_RX[3] F35 AP31 CFG[2] RSVD48 AP32
FDI_CTX_PRX_N1 D21 G33 PCIE_GTX_C_MRX_P11 3.01K_0402_1% 1 2 CFG3 AL32 AL27
FDI_CTX_PRX_N2 FDI_TX#[1] PEG_RX[4] PCIE_GTX_C_MRX_P10 CFG4 CFG[3] RSVD49
D19 FDI_TX#[2] PEG_RX[5] E34 1 2 AL30 CFG[4] RSVD50 AT31
FDI_CTX_PRX_N3 D18 F32 PCIE_GTX_C_MRX_P9 3.01K_0402_1% @ R155 CFG5 AM31 AT32
FDI_CTX_PRX_N4 FDI_TX#[3] PEG_RX[6] PCIE_GTX_C_MRX_P8 CFG6 CFG[5] RSVD51
G21 FDI_TX#[4] PEG_RX[7] D34 AN29 CFG[6] RSVD52 AP33

PCI EXPRESS -- GRAPHICS
FDI_CTX_PRX_N5 E19 F33 PCIE_GTX_C_MRX_P7 R156 1 @ 2 CFG7 AM32 AR33
FDI_CTX_PRX_N6 FDI_TX#[5] PEG_RX[8] PCIE_GTX_C_MRX_P6 3.01K_0402_1% CFG8 CFG[7] RSVD53
F21 FDI_TX#[6] PEG_RX[9] B33 AK32 CFG[8] RSVD_NCTF_54 AT33

Intel(R) FDI
FDI_CTX_PRX_N7 G18 D31 PCIE_GTX_C_MRX_P5 CFG9 AK31 AT34

RESERVED
FDI_TX#[7] PEG_RX[10] PCIE_GTX_C_MRX_P4 CFG10 CFG[9] RSVD_NCTF_55
<26> FDI_CTX_PRX_P[0..7] PEG_RX[11] A32 AK28 CFG[10] RSVD_NCTF_56 AP35
C30 PCIE_GTX_C_MRX_P3 WW41 Recommend not pull down CFG11 AJ28 AR35
FDI_CTX_PRX_P0 PEG_RX[12] PCIE_GTX_C_MRX_P2 CFG12 CFG[11] RSVD_NCTF_57
D22 FDI_TX[0] PEG_RX[13] A28 PCIE2.0 Jitter is over on ES1 AN30 CFG[12] RSVD58 AR32
FDI_CTX_PRX_P1 C21 B29 PCIE_GTX_C_MRX_P1 CFG13 AN32
FDI_CTX_PRX_P2 FDI_TX[1] PEG_RX[14] PCIE_GTX_C_MRX_P0 CFG14 CFG[13]
D20 FDI_TX[2] PEG_RX[15] A30 AJ32 CFG[14]
FDI_CTX_PRX_P3 C18 CFG15 AJ29 E15
C FDI_CTX_PRX_P4 FDI_TX[3] PEG_HTX_GRX_N15 C316 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N15 CFG16 CFG[15] RSVD_TP_59 C
G22 FDI_TX[4] PEG_TX#[0] L33 1 2 AJ30 CFG[16] RSVD_TP_60 F15
FDI_CTX_PRX_P5 E20 M35 PEG_HTX_GRX_N14 C315 1 2 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N14 CFG17 AK30 A2
FDI_CTX_PRX_P6 FDI_TX[5] PEG_TX#[1] PEG_HTX_GRX_N13 C314 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N13 CFG18 CFG[17] KEY R157
F20 FDI_TX[6] PEG_TX#[2] M33 1 2 H16 RSVD_TP_86 RSVD62 D15
FDI_CTX_PRX_P7 G19 M30 PEG_HTX_GRX_N12 C313 1 2 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N12 C15 0_0402_5%
FDI_TX[7] PEG_TX#[3] PEG_HTX_GRX_N11 C312 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N11 RSVD63 RSVD64_R 2 @
PEG_TX#[4] L31 1 2 RSVD64 AJ15 1
FDI_FSYNC0 F17 K32 PEG_HTX_GRX_N10 C311 1 2 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N10 AH15 RSVD65_R 2 @ 1
<26> FDI_FSYNC0 FDI_FSYNC[0] PEG_TX#[5] RSVD65
FDI_FSYNC1 E17 M29 PEG_HTX_GRX_N9 C310 1 2 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N9 R158
<26> FDI_FSYNC1 FDI_FSYNC[1] PEG_TX#[6]
J31 PEG_HTX_GRX_N8 C309 1 2 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N8 B19 0_0402_5%
FDI_INT PEG_TX#[7] PEG_HTX_GRX_N7 C308 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N7 R160 RSVD15
<26> FDI_INT C17 FDI_INT PEG_TX#[8] K29 1 2 A19 RSVD16
H30 PEG_HTX_GRX_N6 C307 1 2 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N6 0_0402_5%
FDI_LSYNC0 PEG_TX#[9] PEG_HTX_GRX_N5 C306 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N5 @ H_RSVD17_R
<26> FDI_LSYNC0 F18 FDI_LSYNC[0] PEG_TX#[10] H29 1 2 1 2 A20 RSVD17
FDI_LSYNC1 D17 F29 PEG_HTX_GRX_N4 C305 1 2 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N4 1 @ 2 H_RSVD18_R B20
<26> FDI_LSYNC1 FDI_LSYNC[1] PEG_TX#[11] RSVD18
E28 PEG_HTX_GRX_N3 C304 1 2 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N3 AA5
PEG_TX#[12] PEG_HTX_GRX_N2 C303 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N2 R159 RSVD_TP_66
PEG_TX#[13] D29 1 2 U9 RSVD19 RSVD_TP_67 AA4
D27 PEG_HTX_GRX_N1 C302 1 2 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N1 0_0402_5% T9 R8
PEG_TX#[14] PEG_HTX_GRX_N0 C301 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N0 RSVD20 RSVD_TP_68
PEG_TX#[15] C26 1 2 RSVD_TP_69 AD3
AC9 RSVD21 RSVD_TP_70 AD2
L34 PEG_HTX_GRX_P15 C332 1 2 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P15 AB9 AA2
PEG_TX[0] PEG_HTX_GRX_P14 C331 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P14 RSVD22 RSVD_TP_71
PEG_TX[1] M34 1 2 RSVD_TP_72 AA1
M32 PEG_HTX_GRX_P13 C330 1 2 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P13 R9
PEG_TX[2] PEG_HTX_GRX_P12 C329 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P12 RSVD_TP_73
PEG_TX[3] L30 1 2 RSVD_TP_74 AG7
M31 PEG_HTX_GRX_P11 C328 1 2 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P11 C1 AE3
PEG_TX[4] PEG_HTX_GRX_P