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Revisions Approvals
REV ECN NO. Description Of Change DATE DFTG. ENGR. REL.
TABLE OF CONTENTS
PAGE PAGE
4 - CLOCK GENERATOR 32 - MULTIBAY
5-7 - BANIAS PROCESSOR 33 - INT KBD./ POINTING DEVICE
8-10 - ODEM 34 - LID SWITCH/LEDS
11-14 - DDR 35 - PORT REPLICATOR
15,16 - ATI_M7/M9_P 36 - MINI PCI
17 - VIDEO RAM 37 - USB, IR
18 - CRT & LCD INVERTER CONNECTOR INTERFACE 38 - MULTIPORT/BLUETOOTH
19,20 - ICH4-M 39 - THERMAL SENSOR & FAN CONTROLLER
21 - SUPER-I/O 40 - BATT CONN
22 - KAHUNA LITE 41 - PWR MODULE CONN
23 - FWH & EEPROM 42 - DECOUPLING CAPS
24 - SERIAL & PARALLEL PORTS 43 - DRILL HOLE
25 - CARDBUS CONTROLLER 44 - HIGH SPEED
26 - PC CARD SLOT 45 - PULL UPS
27 - AC97 CODEC 46,47 - LAN INTERFACE
28 - EQ & MIC JACK 48-51 - POWER
29 - AUDIO AMP & HP JACK 52 - IO BOARD
30 - MB PWR AND SWITCH 53 - POWER ON SEQUENCE
31 - HDD CONNECTOR Engineer
EE1
Drawn by INVENTEC
EE1
R&D CHK Size
TITLE
A3
DOC CTRL CHK
MFG ENGR CHK
Fenway 3.0
TABLE OF CONTENTS
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 1 of 53
EE1 Friday, January 24, 2003 2:43:52 pm 240 PVR2
ITP BANIAS CK TITAN
(Micro-FCPGA)
mPGA478
AGP/M7/M9-P
Display Cache
DDR_SODIMM0
DDR_SODIMM1
Odem
Multibay HDD
Bluetooth
CONN A
CONN B
USB0
USB1
Dock
Dock
USB3
USB5
USB2
USB4
USB ICH4-M LAN INTERFACE LOM
2.0/1.1
System
AC'97 CODEC CARDBUS Mini PCI
DC/DC
FWH
Module
BATTERY PORT REPLICATOR SIO SMC/KBC
Engineer
EE1
Drawn by
EE1
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK
MFG ENGR CHK
Fenway 3.0
BLOCK DIAGRAM
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 2 of 53
EE1 Friday, January 24, 2003 2:45:05 pm 240 PVR2
+VADPTR
+VADPTR
ADPT
+VCC_CORE
+VBAT
+VCC_CORE
+VBAT SWICHING
+V5S
MOSFET VGATE_U +VBAT +V5S
PWR_GOOD3 +VCCP
ISL6216
ISL6207 MCH_PWRGD
+VADPTR_SW +V1.5S
+V1.2L +V1.2_MCH
+VADPTR_SW
2VREF
I/O BOARD
PWR_GOOD3
LAN_ON_3
+V1.5A PGOOD
V2.5
+V1.25S
+V2.5S
SKIP#
+V2.5L SM_VREF
+V1.5A PG1.8S
+VBAT +V1.5A +V3
+V1.8S
+V2.5L
+V2.5L
+V3A +V3S
3V
+V5ALWAYS
+VADPTR_SW +V5
+V12 +V12
+V3_LAN
+V5
5VALWAYS +V5a
DC/DC BOARD +V5S +V3
ACPRES_3
+V12
Engineer
+V5a EE1
Drawn by
EE1
INVENTEC
R&D CHK Size
TITLE
A3
DOC CTRL CHK
MFG ENGR CHK
Fenway 3.0
BLOCK DIAGRAM
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 3 of 53
EE1 Friday, January 24, 2003 2:46:08 pm 240 PVR2
L512 +V3S
NFM40P12C223
(15/5) 1 2
2
1 3 4 C598
C600 10NF_16V
C618 C601 C597 C599 1 C596
4 3
1 1 1 1 1 C602
1
2 2 2 2 2
0.01UF 0.01UF 0.01UF 0.01UF 22UF_6.3V 0.01UF 8 7 6 5
2 10UF_K_6.3V
(10/5) (10/5)
1 L16 2
BLM11A221S
1 C151 1 C173
U14 2 0.01UF 22UF_6.3V
1 VDD VDDA 26
8 VDD
14 VDD VSSA 27 1 2
19 VDD R581 49.9_1%
R117
+V3S Place crystal within 500
32 VDD CPU2 45 CLK_CPU_BCLK_3 1 2 33_5% 44-,5-
CLK_CPU_BCLK
NO_STUFF_10PF 37 VDD CLK_CPU_BCLK#_3 R116 2 33_5%
mils of CLK_TITAN
C153 OPEN
46 VDD CPU2# 44 1 44-,5-
CLK_CPU_BCLK#
1 50 VDD
1 2
1 2
R579 49.9_1% R584 49.9_1%
X2 2 XTAL_IN CLK_MCH_BCLK_3 R119 2 33_5% 1 2
1 1 CPU1 49 1 44-,9-
CLK_MCH_BCLK
R417 R589 14.318MHZ R118
CPU1# 48 CLK_MCH_BCLK#_3 2 33_5%
C152 OPEN 3 XTAL_OUT 1 44-,9-
OPEN 1K_5% 2 CLK_MCH_BCLK#
1 2 NO_STUFF_10PF 1 2
R793 33_5% R796 49.9_1% R582 49.9_1%
2 2 R580 2
1 40 SEL2 CPU0 52 CLK_ITP_3 1 2 1 2 44-,6- 1 2
CLK_ITP
1K_5% R795 0_5%
CPU0# 51 CLK_ITP#_3 1 33_5% 2 1 2
55 SEL1 R588 R593 49.9_1%
66INPUT 24 1 2 44-,6-
CLK_ITP#
R590 0_5%
54 SEL0 66BUF2 23 CLK_AGPCONN_3 R567 33_5% 44-,15-
CLK_AGPCONN
1 2
R578 2 R566 2 25 PWRDWN# CLK_MCH66_3 33_5% 44-,8-
SLP_S1#_3R 20- 1 1 66BUF1 22 CLK_MCH66
1 2
0_5% 1 1 33_5% CLK_ICHHUB_3 R95 R568 33_5%
PCISTOP#_3 20- 34 PCI_STOP# 66BUF0 21 1 2 44-,19- CLK_ICHHUB
1 R576 2
50-,48-,41-,29-,27-,22-,20- R591
SLP_S3#_3R R416 R120 CLK_ICHPCI_3 R76 33_5%
OPEN 1K_5% OPEN CPUSTOP#_3 49-,20- 1 2 53 CPU_STOP# PCIF2 7 1 2 44-,19- CLK_ICHPCI_3R
2 2 0_5%
28 VTT_PWRGD# PCIF1 6
R583 1 2
R586
+V3S 10K_5% 1 2 43 MULT0 PCIF0 5
OPEN
29 SDATA CLK_CBPCI_3 R96
ICH_SMDAT_3 45-,39-,19-,11- PCI6 18 1 2 33_5% 44-,25- CLK_CBPCI_3R
45-,39-,19-,11- 30 SCLOCK PCI5 17 CLK_NICPCI_3 1 R97 2 33_5% 46-,44-
ICH_SMCLK_3 CLK_NICPCI_3R
33 DRCG0 PCI4 16 CLK_MINIPCI_3 1 R98 2 33_5% 44-,36- CLK_MINIPCI_3R
35 DRCG1_VCH PCI3 13
42 IREF CLK_FWHPCI_3 1 R569 2 33_5%
PCI2 12 44-,23- CLK_FWHPCI_3R
PCI1 11 CLK_SIOPCI_3 1 R99 2 33_5% 44-,21-
1 CLK_SIOPCI_3R
41 VSSIREF
R115 R100
475_1% 4 PCI0 10 CLK_KBCPCI_3 1 2 33_5% 44-,22-
VSS CLK_KBCPCI_3R
2 9 VSS R114
15 USB 39 CLK_ICH48_3 1 2 33_5% 44-,20- CLK_ICH48_3R
VSS
20 VSS ADI48M_3 L33 2
VR_PWRGD_CK# 31 VSS DOT 38 1 27- ADI48M
36 VSS
BLM11B121SB
47 REF 56 CLK_SIO14_3 1 R121 2 33_5% 44-,21-
VSS CLK_SIO14_3R
1 R122 2 33_5% 44-,20- CLK_ICH14_3R
+V3S ICS_950810_TSSOP_56P 1 R123 2 33_5% 44-,22- CLK_KBC14_3R
1
1 R94
R93 10K_5%
OPEN
2
2
Q14 3
D
49- 1 R92 2 2G
VGATE_U
0_5% S
NDS7002A 1
1 C150
2 OPEN
EE1
EE1
INVENTEC
A3
Fenway 3.0
CLK GENERATOR
4 53
240 PVR2
H_A#(3:16) 44-,9- CN508
H_A#(3) P4 N2 44-,9-
A3# ADS# L1 H_ADS# +VCCP
H_A#(4) U4 A4# BNR# 44-,9- H_BNR#
H_A#(5) V3 J3 44-,9-
A5# BPRI# H_BPRI#
H_A#(6) R3 A6# 1
L4
ADDR GROUP 0
H_A#(7) V2 A7# DEFER# 44-,9- H_DEFER#
H_A#(8) W1 H2 44-,9- R59
A8# DRDY# M2 H_DRDY# 56_5%
H_A#(9) T4 A9# DBSY# 44-,9- H_DBSY#
H_A#(10) W2 A10# 2
Y4 N4
CONTROL
H_A#(11) A11# BR0# 44-,9- H_BR0#
H_A#(12) Y1 A12#
H_A#(13) U1 A4
A13# IERR# B5
H_A#(14) AA3 A14# INIT# 44-,19- H_INIT#
H_A#(15) Y3 A15#
H_A#(16) AA2 J2 44-,9-
A16# LOCK# H_LOCK#
44-,9- 44-,9- U3
H_REQ#(4:0) H_ADSTB#0 ADSTB#0 B11
H_REQ#(0) R2 REQ0# RESET# 44-,9-,6- H_CPURST# 44-,9- H_RS#(0:2)
H_REQ#(1) P3 H1 H_RS#(0)
REQ1# RS0# K1
H_REQ#(2) T2 REQ2# RS1# H_RS#(1)
H_REQ#(3) P1 L2 H_RS#(2)
REQ3# RS2#
H_REQ#(4) T1 REQ4# TRDY#
M3 44-,9- H_TRDY# H_D#(0:15) 44-,9- CN508 44-,9- H_D#(32:47)
44-,9- H_D#(0) A19 Y26 H_D#(32)
H_A#(17:31) K3 A25 D0# D32# AA24
H_A#(17) AF4 A17# HIT# 44-,9- H_HIT# H_D#(1) D1# D33# H_D#(33)
H_A#(18) AC4 K4 44-,9- H_D#(2) A22 T25 H_D#(34)
A18# HITM# H_HITM# B21 D2# D34# U23
H_A#(19) AC7 A19# +VCCP H_D#(3) D3# D35# H_D#(35)
H_A#(20) AC3 C8 6- H_D#(4) A24 V23 H_D#(36)
A20# BPM#0 B8 6- H_BPM0_ITP# B26 D4# D36# R24
H_A#(21) AD3 A21# BPM#1 A9 H_D#(5) D5# D37# H_D#(37)
H_A#(22) AE4 ADDR GROUP 1 6- H_BPM1_ITP# H_D#(6) A21 R26 H_D#(38)
A22# BPM#2 H_BPM2_ITP# 1 B20 D6# D38#
C9 R23
ITP SIGNALS
H_A#(23) AD2 6- H_D#(7) H_D#(39)
DATA GRP 0
DATA GRP 2
A23# BPM#3 A10 6- H_BPM3_ITP# R53 C20 D7# D39# AA23
H_A#(24) AB4 A24# PRDY# B10 6-
H_TCK H_D#(8) D8# D40# H_D#(40)
H_A#(25) AC6 6- H_BPM4_PRDY# 150_5% H_D#(9) B24 U26 H_D#(41)
A25# PREQ# H_BPM5_PREQ# D24 D9# D41#
H_A#(26) AD5 A13 6- H_D#(10) V24 H_D#(42)
A26# TCK C12 H_TCK 2 E24 D10# D42# U25
H_A#(27) AE2 A27# TDI A12 6- TDI_FLEX H_D#(11) D11# D43# H_D#(43)
H_A#(28) AD6 6- H_D#(12) C26 V26 H_D#(44)
A28# TDO H_TDO B23 D12# D44#
H_A#(29) AF3 C11 6- H_D#(13) Y23 H_D#(45)
A29# TMS B13 H_TMS E23 D13# D45# AA26
H_A#(30) AE1 A30# TRST# A7 6- H_TRST# H_D#(14) D14# D46# H_D#(46)
H_A#(31) AF1 20-,6- H_D#(15) C25 Y25 H_D#(47)
A31# DBR# ITP_DBRESET# LAYOUT NOTES C23 D15# D47#
44-,9- AE5 44-,9- W25 44-,9-
H_ADSTB#1 ADSTB#1 B17 1
H_TCK FORKS H_DSTBN#0 C22 DSTBN0# DSTBN2# W24 H_DSTBN#2
PROCHOT# B18 TP138 H_DSTBP#0 44-,9- DSTBP0# DSTBP2# 44-,9- H_DSTBP#2
THERM
44-,19- C2 A20M# 39- R51 44-,9- D25 T24 44-,9-
H_A20M# THERMDA H_THERMDA 680_5% AT CPU PIN H_DINV#0 DINV0# DINV2# H_DINV#2
44-,19- D3 FERR# A18 39-
H_FERR_S# THERMDC C17 H_THERMDC
H_IGNNE# 44-,19- A3 IGNNE# THERMTRIP# 20- PM_THRMTRIP# 2
H_D#(16:31) 44-,9- 44-,9- H_D#(48:63)
44-,19- C6 A15 H_D#(16) H23 AB25 H_D#(48)
H_STPCLK# STPCLK# ITP_CLK1 A16 D16# D48#
H_CLK
44-,19- D1 H_D#(17) G25 AC23 H_D#(49)
H_INTR LINT0 ITP_CLK0 B14 44-,4-
D17# D49# AB24
H_NMI 44-,19- D4 LINT1 BCLK1 B15 H_D#(18) L23 D18# D50# H_D#(50)
44-,19- B4 44-,4- CLK_CPU_BCLK# H_D#(19) M26 AC20 H_D#(51)
H_SMI# SMI# BCLK0 CLK_CPU_BCLK D19# D51# AC22
H_D#(20) H24 D20# D52# H_D#(52)