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A G R E AT E R M E A S U R E O F C O N F I D E N C E However, Keithley Instruments and Mesa-
tronic Group (Voiron, France) have formed a
technical alliance that is blazing new trails
in the quest for small geometry, mixed RF
and DC testing. Engineers from the two
companies are working together to create
probe cards for parametric test systems
that take RF and low level DC measure-
ments on any combination of wafer prober
pins. Project objectives include easier layout
and manufacture of the probe cards, shorter
production times, and ultimately lower cost
to parametric test users. In addition, users
should be able to reduce their probe card in-
Enabling
ventory by using one card design for many
different applications.
Simultaneous Rf and
Semiconductor Wafer Trends
Because of today's fast switching digital
devices and their combination with RF ana-
Dc Measurements log devices on the same wafer, wafer level
RF testing is needed to predict product per-
During Wafer Probing
formance and reliability. Still, DC paramet-
ric testing remains just as important as ever
in detecting phenomena that affect device
lifetimes and failure modes. As the indus-
try progresses toward the 65nm node and
Randall lee, Keithley instruments, and beyond, high-performance/low-cost digital,
RF, and analog/mixed-signal devices pres-
Bernard Berger, Mesatronic Group ent a significant challenge to test equipment
T
and probe card manufacturers. The big
RaDiTionally, probe cards for compounded when both RF and ultra-low challenge in parametric tester design is to
parametric testers have been de- current DC measurements are desired. In combine the measurement of GHz frequen-
signed for either RF signals or low RF measurements, an important consider- cies and femtoamp DC signals in a way that
level DC measurements, but not ation is minimizing RF signal losses through helps improve device reliability while lower-
both. This was fine as long as a a variety of techniques, such as maintaining ing test costs.
semiconductor wafer contained only RF test the desired characteristic impedance to min- At the same time, a challenge for probe
circuits, or those designed for DC operation. imize RF energy reflections along the signal card manufacturers is the continuous shrink-
However, as digital switching speeds have path. In ultra-low current measurements (for ing of wafer scale dimensions to allow more
increased to RF frequencies, and mixed RF example, sub-nanoamp magnitudes), it is devices per unit area. This includes shrink-
and DC test devices are designed into wafers, important to minimize the effects of extra- ing scribe lanes on wafers, which are cur-
separate RF and DC probing has become neous voltage potentials in the vicinity of the rently trending toward a 30-micron width.
very costly. It requires a changeover from test point. That means probe pads must be just as small
one type of probe card to the other, recali- To help alleviate this situation, some or smaller. Card designs must incorporate
bration of the parametric tester and its inter- probe cards have recently been designed for probe needles that can hit these smaller tar-
connects, and then re-probing the wafer for a a few RF connections, with the remaining gets without excess scrubbing motion that
second set of measurements. probes calibrated for DC. This helps to some causes a probe tip to go off the pad. Cur-
In addition, on-wafer testing of semicon- extent but limits the effectiveness of para- rently, conventional cantilever probe tech-
ductor devices often utilizes the interfacing metric test systems, most of which could be nology is restricted to pad sizes larger than
between test instruments and the test points programmed to conduct either RF or DC 50 microns.
and structures located within wafer scribe measurements on any pin. Still, parametric
lanes. As semiconductor dies and scribe testers themselves need to be designed so implications for
lanes decrease in size, it becomes more that interconnections on any signal path can Parametric Testers
difficult to connect test instruments to the handle either type of signal. Up to now, this For the past few years, manufacturers of
device under test (DUT). This problem is type of system has not been available. parametric testers have been grappling with
Enabling Simultaneous Rf and Dc Measurements During Wafer Probing February2007
the technical problems of mixed RF and low rently, there are very few probe card tech- layout and manufacturing costs. Ultimately,
level DC measurements. A prerequisite for nologies available that allow single insertion this should drive down the end price and
accurate measurements is the creation of a RF and low current DC measurements, and create a more favorable cost of ownership
low-loss broadband signal path and good RF measurements are limited to only a few model for parametric testers.
calibration techniques. The key element in dedicated probe pins that cannot be used for In the resulting probe card, Mesatronic's
effective calibration is fast, automatic de- accurate low current DC measurements. vertical probe technology will allow very
embedding of probe pad/interconnect im- The Keithley/Mesatronic collaboration limited probe pin scrub lengths and mini-
pedance that impairs data integrity. When is concentrating on development of the spa- mum pad damage and contamination on the
used with a suitable probe card design and tial transformer that is used as an intercon- wafer. Reduced contamination may translate
test structures on the wafer, a well designed nection between test instruments and probe immediately to process yield improvements.
and calibrated parametric tester should be needles or membranes that make actual con- The shape of the probes can be varied to
able to execute independent DC and RF tests tact with the DUT on the wafer. Thus, the match up with various probe materials, and
in parallel on separate probes, greatly reduc- spatial transformer serves as an intermedi- they can be used with aluminum, gold, or
ing the time and cost of testing. ate structure that concentrates the test instru- copper pads, as well as tin/lead bumps. The
However, an "any pin" RF/DC meas- ment connections into a form more suited wafer test pads can be as small as 30 microns,
urement objective faces several technical to the high density inputs of the needles or the current trend in scribe lane dimensions,
hurdles. Most of these are associated with membrane. and the probes can consistently hit these
interconnections along the signal path and When both RF and precision DC meas- smaller targets without excess scrubbing
system calibration, which involves wafer urements need to be made, the practice in motion that causes probe tips to go off the
test pads, probe pins, the probe card, inter- the past has been to use a specially designed smaller pads.
connecting cables, and the parametric tester spatial transformer for each desired combi- Mesatronic's DOD Technology exhibits
itself. To successfully probe high frequency nation of RF and DC test terminals. Each DC contact resistances as low as 0.2 to 0.5
and sensitive DC devices, one must master RF connection uses RF terminals having a ohms, while achieving leakages currents of
the mechanical and electrical properties of desired characteristic impedance and each less than 10fA/V at a typical overdrive of 2
the signal path. precision DC connection uses a "guarded" mils. DOD Technology has been successful-
Physically, a probe card is a circuit board. terminal to minimize leakage currents. This ly tested at frequencies of up to 6GHz with
At high frequencies, probe cards become greatly complicates and increases the cost of a total insertion loss less than -3dB. Probe
transmission lines, so a major consideration obtaining a suitable spatial transformer. cards using this technology are being used at
is how they affect signal propagation (for A key feature of the Keithley/Mesatronic various customer sites and are routinely pro-
example, RF energy reflections), interaction spatial transformer design is the creation of duced at Mesatronic's Voiron facility.
between signals (crosstalk), and interactions "broadband guarding." As with other types of
with the outside world (in the form of electro- guarding, the appropriate points along the conclusions
magnetic interference). These and other con- signal path are effectively surrounded with When this new probe card technology is
siderations, such as wave phenomena, are re- elements at the same voltage as the points combined with Keithley's S600 Series para-
lated to the characteristic impedance of the of interest. This prevents them from "see- metric testers, users will be able to make
signal path and any mismatch that occurs at ing" any other potentials that would cause single insertion RF/DC wafer measurements
the signal source or measurement end. DC leakage currents and measurement inac- for automated process monitoring. This will
curacies. However, the Keithley/Mesatronic include fully automated single-pass calibra-
Keithley/Mesatronic Spatial development goes a step further. The guard tion that is quickly executed during testing
Transformer Development traces on the spatial transformer, in com- without the need for human verification. This
Keithley Instruments has partnered with bination with the center conductor traces, calibration includes automatic de-embed-
Mesatronic to develop advanced probe cards also provide the desired characteristic im- ding of probe pad/interconnect impedance
for parametric test and production applica- pedance for an RF signal traveling along the that would impair data integrity, and can be
tions. When the project is completed, the same signal path. completed in minutes. With the new probe
new cards can be used to measure RF sig- Keithley's expertise in sensitive DC and cards, users will have the ability to measure
nals and very low level DC currents on any RF measurement guard circuitry and other RF and low current DC signals on any com-
combination of probe pins that contact a interconnect technology is being used to bination of prober pins by simply changing
semiconductor wafer. Moreover, the probes create the low-loss broadband signal path the type of cabling and termination used for
for these cards will be suitable for 30-micron design of the spatial transformer. Mesatron- the RF and DC pins. This system will pro-
test pads. ic's D.O.D ("Die-On-Die") Technology