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1 1
Compal Confidential
2 2
Qiao Hong Schematics Document
Intel Diamondville Processor with Calistoga(945GSE) + DDRII + ICH7M
3
2008-07-07 3
REV: 1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Docum ent Num ber Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4421P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, Augus t 08, 2008 Sheet 1 of 40
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Compal Confidential Diamondville SC
ZZZ1 ZZZ2 ZZZ FCBGA8
Model Name : KIZ00 437Pins
File Name : LA-4421P PCB PCB PCB 22x22mm
1
page 4,5 1
DAZ@ DAZ@
CRT Conn FSB Clock Generator
H_A#(3..31) H_D#(0..63)
400/533MHz CK505
page 19 page 12
RGB
Calistoga GSE Memory BUS(DDRII) DDRII-SO-DIMM
Thermal Sensor page 11
EMC1402 FCBGA998
1.8V DDRII 400/533
page 2 LCD Conn. LVDS
page 18 27x27mm
page 6,7,8,9,10
USB Port X1
DMI
page 28
X2 mode
USB USB Port X1
2
PCI-Express ICH7M HDA
2
page 28
BGA652
USB Port X1
31x31mm
page 28
page 15,16,17,18
New Card 10/100 Ethernet BlueTooth
JMB385 MINI Card x2 PATA
RTL8102EL page19
page 23
SSD CONTROL
page 19 page 24
SM223AC CMOS CAM
LPC BUS W/S 2G/4G/8G/16G
page22
SD/MMC/MS NAND Flash page 22
CONN page 23 Transfermer
3
page 24 3
Aralia Codec
ALC268-VB-GR
page 22
Power ON/OFF RJ45
DC/DC Interface
page 29 page 24
& LED CONN
page 26
3VALW/5VALW
page 33
ENE KBC SPI
DC IN KB926
page 31 page 25
1.5VS/0.9VS/
AMP & INT INT MIC HeadPhone &
BATT IN 2.5VS MIC Jack
page 37 page 35 Speaker 23
page
page 23
page 23
Int.KBD SPI ROM
page 27 page 25
CHARGER 1.8V/VCCP Touch Pad
page 32 page 27
4
page 34 4
CPU_CORE
page 36
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
Block Diagrams
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Docum ent Num ber Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4421P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, Augus t 08, 2008 Sheet 2 of 40
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1 1
Voltage Rails
External PCI Devices
Power Plane Description S1 S3 S5
VIN Adapter power supply (19V) N/A N/A N/A
DEVICE IDSEL # REQ/GNT # PIRQ
B+ AC or battery power rail for power circuit. N/A N/A N/A
No PCI Device
+CPU_CORE Core voltage for CPU ON OFF OFF
+0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF
+VCCP VCCP switched power rail ON OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF
+1.8V 1.8V power rail for DDR ON ON OFF
+2.5VS 2.5V switched power rail ON OFF OFF
+3VALW 3.3V always on power rail ON ON ON*
+3VS 3.3V switched power rail ON OFF OFF
+5VALW 5V always on power rail ON ON ON*
+5VS 5V switched power rail ON OFF OFF
2 2
+VSB VSB always on power rail ON ON ON*
+RTCVCC RTC power ON ON ON
EC SM Bus1 address EC SM Bus2 address
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Device Address Device Address
Smart Battery 0001 011X b EMC1402 1001 100X b
EEPROM(24C16/02) 1010 000X b
SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Full ON HIGH HIGH HIGH ON ON ON ON
S1(Power On Suspend) HIGH HIGH HIGH ON ON ON LOW
S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF
S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF
S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF
3
ICH7M SM Bus address 3
BOARD ID Table(Page 25) Device Address
ID BRD ID Ra Rb Vab Clock Generator 1101 001Xb
(SLG8SP556VTR)
0 R01 (EVT) NC 0 0V DDR DIMMA 1010 000Xb
1 R02 (DVT) 100K 8.2K 0.25V
2 R03 (PVT) 100K 18K 0.50V
3 R10A (MP) 100K NC 3.3V
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Docum ent Num ber Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4421P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, Augus t 08, 2008 Sheet 3 of 40
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5 4 3 2 1
<6> H_A#[3..16]
<6> H_D#[0..15] H_D#[32..47] <6>
U5A U5B
H_A#3 P21 V19 H_ADS# +VCCP +VCCP H_D#0 Y11 R3 H_D#32
A[3]# ADS# H_ADS# <6> D[0]# D[32]#
H_A#4 H20 Y19 H_BNR# H_BNR# <6> H_D#1 W10 R2 H_D#33
H_A#5 N20 A[4]# BNR# U21 H_BPRI# H_D#2 Y12 D[1]# D[33]# P1 H_D#34
H_BPRI# <6>
1
1
H_A#6 R20 A[5]# BPRI# H_D#3 AA14 D[2]# D[34]# N1 H_D#35
A[6]# D[3]# D[35]#
0
GROUP
ADDR
DATA GRP 0
H_A#7 J19 T21 H_DEFER# R201 R27 H_D#4 AA11 M2 H_D#36
H_A#8 A[7]# DEFER# H_DRDY# H_DEFER# <6> H_D#5 D[4]# D[36]# H_D#37
N19 T19 H_DRDY# <6> 56_0402_5% 330_0402_5% W12 P2
H_A#9 G20 A[8]# DRDY# Y18 H_DBSY# H_D#6 AA16 D[5]# D[37]# J3 H_D#38
A[9]# DBSY# H_DBSY# <6> D[6]# D[38]#
H_A#10 M19 H_D#7 Y10 N3 H_D#39
DATA GRP 2
2
2
H_A#11 H21 A[10]# T20 H_BR0# H_D#8 Y9 D[7]# D[39]# G3 H_D#40
A[11]# BR0# H_BR0# <6> D[8]# D[40]#
H_A#12 L20 H_D#9 Y13 H2 H_D#41
A[12]# D[9]# D[41]#
CONTROL
H_A#13 M20 F16 H_IERR# H_D#10 W15 N2 H_D#42
H_A#14 K19 A[13]# IERR# V16 H_INIT#_R R33 1 2 1K_0402_5% H_D#11 AA13 D[10]# D[42]# L2 H_D#43
D A[14]# INIT# H_INIT# <16> D[11]# D[43]# D
H_A#15 J20 H_D#12 Y16 M3 H_D#44
H_A#16 L21 A[15]# W20 H_LOCK# Close to CPU H_D#13 W13 D[12]# D[44]# J2 H_D#45
A[16]# LOCK# H_LOCK# <6> D[13]# D[45]#
H_ADSTB#0 K20 H_D#14 AA9 H1 H_D#46
<6> H_ADSTB#0 ADSTB[0]# D[14]# D[46]#
T5 H_AP0 D17 D15 H_RESET# H_RS#[0..2] <6> H_D#15 W9 J1 H_D#47
<6> H_REQ#[0..4] H_REQ#0 AP0 RESET# H_RS#0 H_RESET# <6> H_DSTBN#0 D[15]# D[47]# H_DSTBN#2
PAD N21 W18 Y14 K2
REQ[0]# RS[0]# <6> H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 <6>
H_REQ#1 J21 Y17 H_RS#1 H_DSTBP#0 Y15 K3 H_DSTBP#2
REQ[1]# RS[1]# <6> H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 <6>
H_REQ#2 G19 U20 H_RS#2 H_DINV#0 W16 L1 H_DINV#2
REQ[2]# RS[2]# <6> H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 <6>
H_REQ#3 P20 W19 H_TRDY# H_DP#0 V9 M4 H_DP#2
REQ[3]# TRDY# H_TRDY# <6> DP#0 DP#2
H_REQ#4 R19 T10 PAD PAD T15
REQ[4]# <6> H_D#[16..31] H_D#[48..63] <6>
<6> H_A#[17..31] AA17 H_HIT# H_HIT# <6> H_D#16 AA5 C2 H_D#48
H_A#17 C19 HIT# V20 H_HITM# H_D#17 Y8 D[16]# D[48]# G2 H_D#49
A[17]# HITM# H_HITM# <6> D[17]# D[49]#
H_A#18 F19 H_D#18 W3 F1 H_D#50
H_A#19 E21 A[18]# K17 H_D#19 U1 D[18]# D[50]# D3 H_D#51
H_A#20 A16 A[19]# BPM[0]# J18 H_D#20 W7 D[19]# D[51]# B4 H_D#52
A[20]# BPM[1]# D[20]# D[52]#
DATA GRP 1
H_A#21 D19 H15 H_D#21 W6 E1 H_D#53
H_A#22 C14 A[21]# BPM[2]# J15 H_D#22 Y7 D[21]# D[53]# A5 H_D#54
A[22]# BPM[3]# D[22]# D[54]#
ADDR GROUP 1
ADDR GROUP 1
H_A#23 C18 K18 H_D#23 AA6 C3 H_D#55
H_A#24 C20 A[23]# PRDY# J16 PREQ# H_D#24 Y3 D[23]# D[55]# A6 H_D#56
DATA GRP 3
A[24]# PREQ# D[24]# D[56]#
XDP/ITP SIGNALS
H_A#25 E20 M17 ITP_TCK H_D#25 W2 F2 H_D#57
H_A#26 D20 A[25]# TCK N16 ITP_TDI H_D#26 V3 D[25]# D[57]# C6 H_D#58
H_A#27 B18 A[26]# TDI M16 ITP_TDO H_D#27 U2 D[26]# D[58]# B6 H_D#59
H_A#28 C15 A[27]# TDO L17 ITP_TMS H_D#28 T3 D[27]# D[59]# B3 H_D#60
H_A#29 B16 A[28]# TMS K16 ITP_TRST# H_D#29 AA8 D[28]# D[60]# C4 H_D#61
H_A#30 B17 A[29]# TRST# V15 H_D#30 V2 D[29]# D[61]# C7 H_D#62
H_A#31 C16 A[30]# BR1# H_D#31 W4 D[30]# D[62]# D2 H_D#63
H_A#32 A17 A[31]# G17 H_PROCHOT#_R 1 2 H_DSTBN#1 Y4 D[31]# D[63]# E2 H_DSTBN#3
A[32]# PROCHOT# H_PROCHOT# <36> <6> H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 <6>
H_A#33 B14 E4 H_THERMDA R202 22_0402_5% H_DSTBP#1 Y5 F3 H_DSTBP#3
THERM
A[33]# THRMDA <6> H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 <6>
H_A#34 B15 E5 H_THERMDC Close to CPU H_DINV#1 Y6 C5 H_DINV#3
A[34]# THRMDC <6> H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 <6>
H_A#35 A14 H_DP#1 R4 D4 H_DP#3
H_ADSTB#1 B19 A[35]# H17 H_THERMTRIP# T13 PAD DP#1 DP#3 PAD T12
<6> H_ADSTB#1 ADSTB[1]# THERMTRIP# H_THERMTRIP# <6,16>
H_AP1 M18 +CPU_GTLREF A7 T1 COMP0 1 R57 2 27.4_0402_1%
T7 PAD AP1 R240 1 @ 2 1K_0402_5% ACLKPH U5 GTLREF COMP[0] T2 COMP1 1 R58 2 54.9_0402_1%
C H_A20M# U18 R239 1 @ 2 1K_0402_5% DCLKPH V5 ACLKPH COMP[1] F20 COMP2 2 R208 1 27.4_0402_1% C
<16> H_A20M# A20M# DCLKPH COMP[2]
H_FERR# T16 V11 CLK_CPU_BCLK T17 F21 COMP3 2 R209 1 54.9_0402_1%
<16> H_FERR# FERR# BCLK[0] CLK_CPU_BCLK <12> BINIT# COMP[3]
H_IGNNE# J4 V12 CLK_CPU_BCLK# R6 MISC
<16> H_IGNNE# H_STPCLK# IGNNE# BCLK[1] CLK_CPU_BCLK# <12> EDM H_DPRSTP#
R16 +CPU_EXTBGREF M6 R18 H_DPRSTP# <16,36>
<16> H_STPCLK# H_INTR T15 STPCLK# N15 EXTBGREF DPRSTP# R17 H_DPSLP#