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SPECIFICATIONS
MODEL
Receiving System Mains Voltage Power Consumption Sound Output Antenna Impedance Tuning System Number of Program Reception Channel Remote Control Unit Screen Size (Diagonal) Indication
DVT-20F4PA
DVT-20F4FA
DVT-21F4LA
Terminal
PAL-I PAL-B/G P/S-B/G, S-L/L' 230V AC 50Hz 72W Approx.(20 inch) 76W Approx.(21 inch) 1.5W Approx.(at 60%, 10% THD) x 2 75 ohm unbalanced Frequency Synthesis Tuning System 99 Programs Refer to the TUNER description R-30C(RH400) R-30C(RC1400) R-30C(RCT400) 20" : 480mm 21" : 510mm On Screen Display -Program No. (01-99) -Sleep (10-120, step 10 min) -Mute & Volume -AV1, AV2 -Main menu( Picture, Clock Set, TV Timer, Video Timer, Language,Preset) -Picture Menu(Brightness, Colour, Contrast, Sharpness) -TV Timer Menu(ON Time, PR., OFF Time) -Preset Menu(Full Auto Search, Auto Search, Fine Tuning, VideoPlus+ Preset) 21 Pin EURO SCART
2
AUX TERMINAL
20 21 19
18 17
16 15
14 13
12 11
10 9
8 7
6 5
4 3
2 1
21 PIN EURO-SCART
PIN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
Signal Designation
Audio Out(linked with 3) Audio In(linked with 6) Audio Out(linked with 1) Audio Earth Blue Earth Audio in (linked with 2) Blue in Slow(Function) Switching Green Earth NC Green In NC Red Earth NC Red In Rapid(Blanking) switching Video Earth Rapid Blanking Earth Video Out Video In Common Earth
Matching Value
0.5Vrms,lmp<1 (RF 60% MOD) 0.5Vrms,lmp>10 0.5Vrms,lmp<1 (RF 60% MOD)
0.5Vrms,lmp>10 0.7Vpp 3 ,lmp75 TV:0-2V,PERI:9.5-12V,lmp>10
0.7Vpp 3
,lmp75
0.7Vpp 3 ,lmp75 Logic 0:0-0.4V,Logic 1:1-3V,Imp 75
1Vpp 3 ,lmp75 1Vpp 3 ,lmp75
RCA JACK
IN AUDIO OUT
3
VIDEO
SAFETY INSTRUCTIONS
WARNING: BEFORE SERVICING THIS CHASSIS, READ THE "X-RAY RADIATION PRECAUTION","SAFETY PRECAUTION" AND "PRODUCT SAFETY NOTICE" BELOW.
X-RAY RADIATION PRECAUTION
1. Excessive high voltage can produce potentially hazardous X-RAY RADIATION.To avoid such hazards, the high voltage must not exceed the specified limit. The nominal value of the high voltage of this receiver is 25.5 (21":26.5 ) at max beam current. The high voltage must not, under any circumstances, exceed 27.5 (21":29.0 ). Each time a receiver requires servcing, the high voltage should be checked following the HIGH VOLTAGE CHECK procedure on page 9 of this manual. It is recommended the reading of the high voltage be recorded as a part of the service records, It is important to use an accurate and reliable high voltage meter. 2. The only source of X-RAY Radiation in this TV receiver is the picture tube.For continued X-RAY RADIATION protection,the replacement tube must be exactly the same type tube as specified in the parts list.
SAFETY PRECAUTION
1. Potentials of high voltage are present when this receiver is operating. Operation of the receiver outside the cabinet or with the back board removed involves a shock hazard from the receiver. 1) Servicing should not be attempted by anyone who is not thoroughly familiar with the precautions necessary when working on highvoltage equipment. 2) Always discharge the picture tube before handling the tube. The picture tube is highly evacuated and if broken, glass fragments will be violently expelled. 2. If any Fuse in this TV receiver is blown, replace it with the FUSE specified in the Replacement Parts List. 3. When replacing a high wattage resistor(oxide metal film resistor)in circuit board, keep the resistor 10mm away from circut board. 4. Keep wires away from high voltage or high temperature components. 5. This receiver must operate under AC230 volts, 50Hz. NEVER connect to DC supply or any other power or frequency.
PRODUCT SAFETY NOTICE
Many electrical and mechanical parts in this have special safety-related characteristics. These characteristics are often passed unnoticed by a visual inspection and the X-RAY RADIATION protection afforded by them cannot necessarily be obtained by using replacement components rated for higher voltage,wattage,etc. Replacement parts which have these special safety characteristics are identified in this manual and its supplements, electrical components having such features are identified by designated symbol on the parts list. Before replacing any of these components, read the parts list in this manual carefully. The use of substitute replacement parts which do not have the same safety characteristics as specified in the parts list may create X-RAY Radiation.
5
ASSEMBLY VIEW
MAIN BOARD VIEW
6
INSTALLATION & SERVICE ADJUSTMENTS
GENERAL INFORMATION All adjustments are thoroughly checked and corrected when the receiver leaves the factory. Therefore the receiver should operate normally and produce proper colour and B/W pictures upon installation. But, several minor adjustments may be required depending on the particular location in which the receiver is operated. This receiver is shipped completely in a card-board carton. Carefully draw out the receiver from the carton and remove all packing materials. Plug the power cord into an AC power outlet. Turn the receiver ON and adjust the FINE TUNING for the best picture detail. Check and adjust all the customer controls such as BRIGHTNESS, CONTRAST and COLOUR Controls to obtain a natural B/W picture. PROTECTION CIRCUIT CHECK 1. Turn on the receiver. 2. The receiver must be turned off and changed to stand-by mode. HIGH VOLTAGE CHECK 1. Connect an accurate high voltage metre to the anode of the picture tube. 2. Turn on the receiver. Set the BRIGHTNESS and CONTRAST controls to minimum(zero beam current). 3. High voltage should be below 27.5 (21":29.5 ) AUTOMATIC DEGAUSSING A degaussing coil is mounted around the picture tube so that external degaussing after moving the receiver is normally unnecessary. Providing the receiver is properly degaussed upon installation. The degaussing coil operates for about 1 second after the power of the receiver is switched ON.If the set is moved or placed in a different direction, the power switch must be switched off for at least 15 minutes in order to make the automatic degaussing circuit operate properly. Should the chassis or parts of the cabinet become magnetized to cause poor colour purity,use an external degaussing coil. Slowly move the degaussing coil around the faceplate of the picture tube, the sides and front of the receiver and slowly withdraw the coil to a distance of about 2m before disconnecting it from the AC source. If colour shading still persists, perform the COLOUR PURITY ADJUSTMENT and CONVERGENCE ADJUSTMENTS procedures, as mentioned later.
DYNAMIC CONVERGENCE ADJUSTMENT
Dynamic convergence (convergence of the three colour field at the edges of the CRT screen)is accomplished by proper insertion and positioning of three rubber wedges between the edges of the deflection yoke and the funnel of the CRT. This is accomplished as follows: 1. Switch the receiver on allow it to warm up for 15 minutes. 2. Apply crosshatch pattern from dot/bar generator to the receiver. Observe spacing between lines around edges of the CRT screen. 3. Tilt the deflection yoke up and down, and insert tilt adjustment wedges 1 and 2 between the deflection yoke and the CRT until the misconvergence illustrated in figure. 2(A) has been corrected. 4. Tilt the deflection yoke right and left, and insert tilt adjustment wedge 3 between the deflection yoke and the CRT until mis-convergence illustrated in figure. 2(B) has been corrected. 5. Alternately change spacing between, and depth of the insertion of, the three wedges until proper dynamic convergence is obtained. 6. Use a strong adhesive tape to firmly secure latch of the three rubber wedges to the funnel of the CRT. 7. Check purity and readjust, if necessary.
STATIC (CENTRE) CONVERGENCE ADJUSTMENT
1. Switch the receiver on and allow it to warm up for 15 minutes. 2. Connect the output of a crosshatch generator to the receiver and concentrating on the centre of the CRT screen, proceed as follows: a. Locate the pair of 4 pole magnet rings. Rotate individual rings (Change spacing between tabs)to converge the vertical red and blue lines.Rotate the pair of rings (maintaing spacing between tabs)to converge the horizontal red and blue lines. (Refer to fig. 1 (A)) b. After completing red and blue centre convergence, locate the pair of 6 pole magnet rings. Rotage individual rings (change spacing between tabs) to converge the vertical red and blue (Magenta)and green lines. Rotate the pair of rings (maintaining spacing between tabs)to converge the horizontal red and blue(Magenta) and green lines.(Refer to Fig. 1(B))
8
COLOR PURITY ADJUSTMENT
For the best result,it is recommended that the purity adjustment is made in final receiver location. If the receiver will be moved, perform adjustment with it facing east. The receiver must have been operating 15 minutes prior to this procedure and the faceplate of the CRT must be at room temperature. The receiver is equipped with an automatic degaussing circuit. But, if the CRT shadow mask has become excessively magnetized, it may be necessary to degauss it with manual coil. Do not switch the coil. The following procedure is recommended while using a dot generation. 1. Check for correct location of all neck components (See figure. 5). 2. Rough-in the static convergence at the centre of the CRT, as explained in the static convergence procedure. 3. Rotate the picture control to centre of its rotation range, and rotate brightness control to max. CW position. 4. Apply green color signal to produce a green raster. 5. Loosen the deflection yoke tilt adjustment wedges (3), loosen the deflection yoke clamp screw and push the deflection yoke as close as possible to the CRT screen. 6. Begin the following adjustment with the tabs on the round purity magnet rings set together, initially move the tabs on the round purity magnet rings to the side of the CRT neck. Then, slowly separate the two tabs while at the same time rotaing them to adjust for a uniform green vertical band at the CRT screen. 7. Carefully side the deflection yoke backward to achieve green purity. (uniform green screen) Centre purity was obtained by adjusting the tabs on the round purity magnet rings, outer edge purity was obtained by sliding the deflection yoke forward. Tighten the deflection yoke clamp screw. 8. Check for red and blue field purity by applying red signal and touch up adjustments, if required. 9. Perform black and white tracking procedure.
4. Set the G,B Drive VR (R515,R505)to center. 5. Set the CONTRAST, BRIGHTNESS, COLOR control to MIN, and Sub-bright VR(R 13)to CENTER. 6. Rotate the R, G and B Bias VR of the other color which did not appear on the screen clockwise, until a dim white is obtained. 7. Set the CONTRAST, BRIGHTNESS, COLOR control to MAX. 8. Set the G, B Drive VR to obtain the best white uniformity on the screen. 9. Rotate the CONTRAST, BRIGHTNESS, COLOR controls until a dim raster is obtained and touch-up adjustment of RGB Bias VR to obtain the best white uniformity on the screen.
SUB-BRIGHTNESS ADJUSTMENT
1. White balance adjustment must proceed this procedure. 2. Set the CONTRAST, BRIGHTNESS, COLOR control to MIN. 3. Rotate the SUB-BRIGHTNESS VR (R 13) gradually CCW until the last beam disappears on the screen.
VERTICAL HEIGHT ADJUSTMENT
1. Receive RETMA pattern signal. 2. Set the BRIGHTNESS control and CONTRAST control to Max., and the COLOR control to centre. 3. Adjust R 11 for the optimum vertical height and over scanning.
VERTICAL CENTER ADJUSTMENT
1. Receiver RETMA pattern signal. 2. Adjust R 3 so that the vertical center of the picture may be coincident with the mechanical center of CRT.
HORIZONTAL CENTER ADJUSTMENT
1. Receive RETMA pattern signal. 2. Adjust R 12 so that the horizontal center of the picture may be coincident with the mechanical center of CRT.
SCREEN & WHITE BALANCE ADJUSTMENT
1. This adjustment is to be made only after warming up at least 15 minutes. 2. Receive RETMA pattern signal. 3. Set the RGB Bias VR (R522,R512,R502) to minimum.
FOCUS VOLTAGE ADJUSTMENT
1. Receive RETMA pattern signal. 2. Adjust the FOCUS VOLUME on the FBT and make the picture on the screen be finest.
9
RF AGC ADJUSTMENT(MAIN)
1. Receive PAL COLOR BAR signal in the VHF high band where the strength of signal can be 75dB. 2. Set the CONTRAST control to Max., the BRIGHTNESS control to provide adequate black and gray scales. 3. Connect an oscilloscope to P211.(Tuner AGC point) 4. Maintain the fine tuning on the screen, and adjust R010(AGC DELAY CONTROL VR.) to max. 5. Adjust the VR(R010) max to below 2.2V(FA/LA:2.2V).
RF AGC ADJUSTMENT(SUB)
1. Receive PAL COLOR BAR signal in the VHF high band where the strength of signal can be 75dB. 2. Set the CONTRAST control to Max., the BRIGHTNESS control to provide adequate black and gray scales. 3. Connect an oscilloscope to P211.(Tuner AGC point) 4. Maintain the fine tuning on the screen, and adjust R090(AGC DELAY CONTROL VR.) to max. 5. Adjust the VR(R090) max to below 2.2V(FA/LA:1.6V).
MAIN B+(+103V) ADJUSTMENT
1. Set the picture level to service 1 mode.(Bright:31, Colour:31, Contrast:48, Sharpness:48) 2. Connect DC voltage meter to the P805 and adjust R080 for +103V DC.
10
BLUE RED
RED/BLUE GRN
BLUE RED
RED/BLUE GRN
(A) 4-Pole Magnets Movement
(B) 6-Pole Magnets Movement
FIG. 1 CENTER CONVERGENCE BY CONVERGENCE MAGNETS
B G R
B G R B G R BGR R G B
BGR
R G B
R G B
(A) Incline the Yoke up (or down)
(B) Incline the Yoke right (or left)
FIG. 2 CIRCUMFERENCE CONVERGENCE BY DEF .YOKE
ADJUST THE ANGLE (VERTICAL LINES)
CONSTANT WEDGE1
WEDGE2
WEDGE3
ROTATE TWO TABS AT THE SAME TIMER (HORIZONTAL LINES) ADJUSTMENT OF MAGNETS
DEFLECTION YOKE REAR VIEW
FIG. 3 ADJUSTMENT OF MAGNETS
DEFLECTION YOKE CLAMP SCREW
FIG. 4 RUBBER WEDGE LOCATION
PURITY MAGNETS 6 POLE CONV MAGNETS RUBBER WEDGES TAPE 4 POLE CONV MAGNETS DEFLECTION YOKE TILT ADJUSTMENT WEDBE
FIG. 5 PICTURE TUBE NECK COMPONENT
11
PIF ADJUSTMENT(MAIN)
1. APPARATUS PRESETTING CONNECTION AND PRESET 1) Oscilloscope Scaling a) Put the scale of X and Y of the oscilloscope to DC level. b) Set the horizontal time display to X-Y. c) Put the horizontal axis(X) to 1V/div. And the vertical axis(Y) to 2V/div. 2) LSW-480 MARKER FREQ. SETTING.
Fp(n+1) B/G,L/L' 31.9 I 31.9 fs 33.4 33.5 fc 34.5 35.07 fp-2 36.9 37.5 fp 38.9 39.5 fs(n-1) 40.4 41
CONNECTION 1) Connect H-out of LSW-480 to X-axis of the oscilloscope and V-out of LSW-480 to Yaxis of the oscilloscope. 2) Connect the sweep signal output to TP1. 3) Set ATTENUATOR of LSW-480 to 10dB. 4) Supply 12V DC voltage(B+) to TP4 and TP6. 5) Supply 4-5V DC voltage to TP3.
(ADJUSTMENT OF L') T.P PIF SWEEP MARKER GENERATOR (LSW-480,480-U80) OUTPUT TP5 (Q205 COLLECTOR) TP2 (AFT,I201 #44) GND
MAIN PCB
TP1 (U1, IF1) TP4 (1717 #1) TP6(C727) (B+) TF3 (I201 #48) (IF AGC)
V-Scope
H-Scope
Through a 4.7K resistor OSCILLOSCOPE 14V DC POWER SUPPLY 4-5V DC POWER SUPPLY
X Y
Connection For PIF Adjustment
2. ADJUSTMENT OF AFT(B/G, I, L)
1) Connect the test point of LSW-480 to TP2. 2) Adjust L201(AFT COIL) so that the P marker point is located on the reference level.
B/G, L : 38.9MHz I : 39.5MHz P
AFT WAVEFORM
3. ADJUSTMENT OF SECAM-L' AFT
L' : 34.5MHz
1) Connect the TP5 (Q205 collector) to GND. 2) Adjust C200(L'AFT TRIMMER) so that the C marker point (34.5MHz) is located on the reference level. 12
C
L'AFT WAVEFORM
PIF ADJUSTMENT(SUB) 1. APPARATUS CONNECTION AND PRESETTING CONNECTION 1) Connect RF-out of PM5518 to TP7. 2) Connect DC voltage meter to TP8. 3) Supply 14V DC voltage(B+) to TP4 and TP6. PRESET 1) PM5518 SETTING Freq. (MHz) 38.9 39.5 34.5 Remark FA/LA PA LA
B/G,L I L'
PM5518 PATTERN GENERATOR RF OUTPUT TP7 (U2, IF1) TP8 (I901 #15) DIGITAL MULTIMETER
MAIN PCB
TP4 (I717 #1) TP6(C727)
TP9 (Q904 BASE) Through a 22K resistor (ADJUSTMENT OF L')
14V DC POWER SUPPLY
5V DC POWER SUPPLY
Connection For PIF Adjustment
2. ADJUSTMENT OF AFT(B/G, I, L) 1) Connect the DC voltage meter to TP8. 2) Adjust L902(AFT COIL) for 2.2±0.1V.
3. ADJUSTMENT OF SECAM-L' AFT 1) Supply 5V DC voltage to TP9. 2) Connect the DC voltage meter to TP8. 3) Adjust R091(L'AFT VR.) for 2.2±0.1V
13
IC OPERATION DESCRIPTION
M37206MC-xxxSP (Micro-controller)
(1) General Description It is a one-chip micro-controller with an 8-bit CPU. (2) Functional Block Diagram
OSD OSC OSD OSC (PULL UP) PIF MUTE AFT IN1 P.F IN(L) AFT IN2 (PULL UP) VOLUMOUT (PULL UP)CONT. OUT (PULL UP)BRIGHT OUT (PULL UP)COLOUR OUT (PULL UP)PEAKING OUT (PULL UP)TINT OUT (PULL UP)L1' OUT (PULL UP)L2' OUT TEXT1 USE TEXT2 LANG TEXT3 LANG SYS OSD SECAML SYNC1 "H" (PULL UP) IIC CLK (PULL UP) IIC DATA (IDENT) SYNC LOW IN (PULL UP) SERIAL IN (PULL UP) SERIAL CLK (PULL UP) SERIAL OUT GND GND RESET(L) 8.0 MHz 8.0 MHz GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
OSC1 OSD2 P MUTE AFT1 P.F IN AFT2 VOL. PWM CONT. PWM BRI. PWM COL. PWM PEA. PWM TINT. PWM L1' OUT L2' OUT OP.8 OP.9 OP.10 OP.11 OP.12 SYNCI SCL SDA SYNC. L SD_IN SD_CLK SD_OUT GND GND RESET XIN XOUT GND
Vcc H. SYNC V. SYNC R G B
64 63 62 61 60 59 58
+ 5V H.SYNC INPUT V.SYNC INPUT R OUT GUT B OUT NC BLANKING OUT TV 1/2 SEL OUT STSTEM1 OUT SYSTEM2 OUT
BLK TV 1/2 SYS1 SYS2
57 56 55 54 53 52 51
V MUTE S MUTE TV PWR DISABLE A/V1 A/V2' A/V1' SCIN A/V OP. 7 OP. 6 OP. 5 OP. 4 OP. 3 OP. 2 OP. 1 XCOUT XCIN
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
V MUTE OUT SPEAKER MUTE TV POWER ON/OFF DISABLE A/V1 SEL OUT A/V2' SEL OUT A/V1' SEL OUT SCART IN (S/SW) A/V SEL OUT VPS/PDC CLK TEST POWER ON START SHOWVIEW AV2 U BAND TAPE SPEED 32.768 KHz 32.768 KHz
14
(3) Functional Block Diagram Pin No. 1 2 3 4 Symbol OSC IN OSC OUT P MUTE AFT1 Name Oscillator for OSD PIF MUTE ADC Input Function Description OSD (On Screen Display) Not used Comparison voltage input terminal connected to built-in comparator. Input AFT signal from MAIN TUNER with level conversion (0 to Vdd) The results of the comparison are used when the auto search and digital AFT works. Power fail detect input. Input AFT signal from SUB TUNER with level conversion ( 0 to Vdd) Output the pulse width modulated signal in 63 level in accordance with 6-bit latch data.
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
P.F INPUT AFT2 VOL CON BRI COL PEA TINT L1' L2' OP. 8 OP. 9 OP.10 OP.11 OP.12 SYNC1
POWER FAIL Input ADC Input Volume Control Output Contrast Control Output Brightness Control Output Colour Control Output Peaking Control Output Tint Control Output L1' Output(SECAM) L2' Output(SECAM) Text use Option TURKISH Option EAST Option System OSD Option SECAM-L Option Sync Ident Input
Not used Not used SECAM Only Input terminal of image synchronous signal necessary for auto search and AFT operation. In the case of the determination of the level signal synchronization, the signal state ("H" or "L") which is input at this terminal is determined every 4ms. "H" ------------ Presence of synchronization "L" ------------ Absence of synchronization Pin SCL and SDA are respectively the data and clock wire or the multi-master two-wire bidirection IIC-bus control bus. If a transmission does not succeed the controller will retry it for up to 5 times. If the bus is occupied for longer than 1.18 seconds the u-controller will generate bursts of nine clock pulses with intervals of 1.18 seconds until bus is free again. Sync low input (Ident) from SUB TUNER Syscon serial DATA input Syscon serial CLOCK out Syscon serial DATA out GND
21 22
SCL SDA
Clock Pin for IIC(O) Data Pin for IIC(I/O)
23 24 25 26 27
SYNC L SD IN S CLK SD OUT GND
Sync Low
15
Pin No. Symbol 28 GND. 29 RESET
Name Reset Input
30 31
OSCI OSCO
Clock Input for CPU Clock Output for CPU
32 33 34 35 36 37 38 39 40 41 42 43 44 45
GND XCIN XCOUT OP. 1 OP. 2 OP. 3 OP. 4 OP. 5 OP. 6 OP. 7 A/V S/SW AV1' AV2'
XC IN XC OUT Tape Speed Option UHF only Option AV2 Option ShowView Option Factory Power Option Clock Test Option VPS Option A/V Mode Switching Scart Input AV1' Switching Out AV2' Switching Out
Function Description GND This pin is used to reset the u-controller after a power-on reset. In order to be sure that the ucontroller starts from an initialized state after the supply voltage is available, a reset signal has to be applied. This reset signal has to be low until a stable 4.19V supply voltage is available. The OSCI and OSCO are used to control the onchip oscillator of the u-controller. OSCI is the input terminal and OSCO the output terminal. All internal timing of the u-controller (except for the OSD part) are derived from this oscillator. The oscillator frequency has to be 8MHz. GND 32.768KHz input 32.768KHz output SP/LP option
Power-On start
Active "L" Slow switch input TV2, AV1', AV2' (VCR REC. mode) AV1' AV2' Function L H AV1 H L AV2 H H TV2 Active "L" Switching Regulator ON/OFF output The switch-mode power supply is controlled. "L" ----------- power OFF "H" ---------- power ON Mute Output is active "H" On power on/off state, instantaneously cut off the sound and video. Not Connected Not Connected Not Connected Not Connected SECAM-L/L' switch(TV2) SECAM-L/L' switch(TV1) 16
46 47 48
AV1 DISABLE POWER
AV1 Switching Out Disable Out Stand by ON/OFF Control Output Sound Mute Control
49
S. MUTE
50 51 52 53 54 55
V. MUTE n.c. n.c. n.c. SYS2 SYS1
Video Mute Control
SECAM-L/L' Switch SECAM-L/L' Switch
Pin No. 56
Symbol TV1/2
Name
Function Description TV1 / TV2 selection switch "H" -------------- TV1 "L" --------------- TV2
57 58 59 60 61 62
BLK n.c. B G R V-sync
Blanking Signal for OSD OSD Blue Colour Output OSD Green Colour Output OSD Red Colour Output V-sync input for OSD Not Connected Output R,G and B deliver the colour components for the OSD while output BLK is used as a test blanking signal. The output polarity of the R,G,B and BLK terminals are active "H". Input terminal for CRT display vertical synchronous signal. Input rectangular pulses whose amplitude is in the range from 0 to 5V. The signal state should be active for the time more than that required for three scanning lines. The input polarity is active "L". Input terminal for CRT display horizontal synchronous signal. Input rectangular pulses whose amplitude is in the range from 0 to 5V. The input polarity is active "L". The signal state should be active for the time more than that required for three scanning lines. Connected to the 5V power supply.
63
H-sync
H-sync input for OSD
64
Vcc
Power supply input terminal
17
TDA 8362
(1) Features
Multi-standard vision IF circuit (positive and negative modulation) Multi-standard FM sound demodulator (4.5 MHz to 6.5 MHz) Video and audio switches (CVBS int/ext, S-VHS and audio int/ext) Integrated chroma trap and bandpass filters (autocalibrated) Luminance delay line integrated PAL/NTSC colour decoder with automatic search system Easy interfacing with the TDA 8395 (SECAM decoder)for multi-standard applications RGB-control circuit with linear RGB inputs and fast blanking Horizontal synchronization with two control loops and alignment-free horizontal oscillator Vertical count-down circuit and vertical pre-amplifier Low dissipation(only 600mW) Small amount of peripheral components compared with competition IC's Only one adjustment (vision IF demodulator)
(2) Description
Vision IF amplifier, video demodulator, video amplifier, AGC and AFC suitable for both negative and positive modulation. Sound limiter,demodulator and amplifier with volume control. Inputs and switches for external audio and CVBS signals. Synchronization circuit with drive circuits for horizontal and vertical deflection. X-ray protection (combined with the 2nd phase detector pin). PAL/NTSC color decoder in which the chroma filters (bandpass and trap) and the luminance delay line have been integrated. The circuit has a separate chroma input and the filters can be switched-off so that S-VHS signals (via an external switch) can be applied to the IC. For SECAM applications an (alignment-free) SECAM-decoder can be added to the IC. Peaking circuit in the luminance channel. RGB-output circuit with linear inputs for On-screen Character Display.
(3) Block Diagram
SHIFT AUDIO OUT AUDIO IN POS/NECC MCO. +BV + START
AUDIO PAE-AMP +VOL.-CONTR. T.O.P. TUNER AGC FOR IF + TUNER
AUDIO SWITCH
SYNC SEPARATOR + 1st LOOP
VCO + CONTROL
2nd LOOP + HOR SHIFT
H. OUT
H +
REF SOUND LIMITER MODULATOR CHROMA TRAP + DELAY LINE V VERT.SYNC SEPARATOR H/V DIVIDER VERT.DEFL.
SW IF VIF AMPLIFIER +DEMODULATOR FILTER TUNING
LUMINANCE PROCESSING
RGB-INPUT +SWITCH
BL R G B
AFG AFC + S/M VIDEO AMPL CVBS
A CHROMA BANDP. RGB-MATRIX +OUTPUT G B
Chr IDENT VIDEO IDENT SWITCH CONTROL PAL/NTSC DECODER G+Y MATRIX + SATURATION CONTROL R.Y 4.4 PEAKING VOLUME CONTROL 3.6 TDA 4661 CONTRAST BRIGHTNESS SATURATION B.Y R.Y B.Y PEAK-WHITE LIMITER
VIDEO SWITCH
Chr CVS in Chr +sw. HUE + SW. + Chr out SECUMREF.
SOUND TRAP
SOUND BANDP.
18
Pin No.
1
Name
Audio De-emphasis
Function Description
At this pin the audio signal is available for scart. The signal has an amplitude of 350mVrms (at f= 50KHz) is non volume controlled and has to be buffered.(notice the output impedance influences the deemphasis).For scart requirements, the buffer should be dimensioned as an amplifier in order to increase the output signal. A third function of this pin is the positive modulation switch. When the voltage at this pin is above Vcc-1V positive modulation is selected. The current needed is 100 A typical. Because the demodulator performance depends on the Q factor, we want to keep the Q factor as high as possible. But this means that the steepness of the AFC will change with the Q factor of the tuned clicuit itself and also with the input impedance of the IC A compromise has to be made. The input impedance of the IC is as large as possible (about 12 kOhms) and the Q factor of normal tuned circuits varies from 70 to 90. By means of an external resistor, it is possible to damp the circuit to a Q of 40 to reduce the steepness variation of the AFC. The identification output has a three level output, 0.5, 6 or 8V. Output voltage "video not identified" Output voltage "video identified" and colour signal available with fsc = 3.5MHz Output voltage "video identified" and colour signal available with fsc = 4.4MHz or no colour signal detected The maximum load current on this pin is 25 A. The output impedance is 20 K . 0.5V max 6V 8V
2,3
IF
Demodulator Tuned Circuit
4
Video
Identification Output
5
SIF input
+Volume control
The sound input impedance is 8.5K /5pF which has to be taken into account for the ceramic filiters. For DC, the impedance is very high. The PLL is sensitive for high freq. AC signal > 1mVrms. Because of the chosen principle: an adjustment free PLL it is needed to have an internal PLL with a large bandwidth (catching range). This implies the system also is sensitive for spurious frequencies. Both layout and sound band pass filters need special attention. The volume can be controlled at this pin by means of a DC voltage of 0.2-5V for min-max gain. External sound signals from scart, for example, can be applied to this pin via a capacitor. The input impedance is 25 K . A multistandard concept requires several filters at the video output (sound-trap and sound-band pass filters). This causes a too big capacitive load at the video output so an EMITTER FOLLOWER as buffer should be added. The required emitter current depends on the number of filter applied. Decoupling Digital Supply
6 7
External Audio Input IF Video Output
8
Decoupling digital Supply
9 10 11
Ground Positive Supply (8V) Ground
Ground 1 (IF, H sync, RGB output, Digital, H output) Supply (IF,Sound,H sync,Chroma, Filters,RGB output, Digital,) Ground 2 (Sound,Chroma,Filters,Hosc, PHI-1, PHI-2) 19
Pin No.
12
Name
Decoupling
Function Description
Variations in the tuning voltage outside calibration (i.e. during field scan), due to external leakage current or interference sources, will result in mistuning of the luminance notch filter, chroma bandpass filter and luminance delay stage. Unwanted voltage signals at pin 12 due to external leakage currents or cros-stalk from interference sources should be less than 100mV. A capacitor of 100nF requires that external leakage at pin 12 should be less than 0.5 A. The internal and external CVBS amplitudes should be 2Vpk-pk and 1Vpk-pk respectively; their source impedances should be low so as to minimze cross-talk from interference sources. The internal CVBS input is derived from the IF video output (pin 7) and the external CVBS input can be derived from either SCART CVBS or YSVHS; they should be AC coupled to pins 13 & 15 respectively. The coupling capacitors are chosen in order to have fast clamping and minimum line/field sag. The input impedance of pin 14 is very high (MOS input). The DC voltage at the peaking control input controls the gain of the peaking amplifier. The peaking control input voltage should have a DC voltage range from 0 to 5V. The input impedance of the chroma and A/V switch input(pin 16) is 15K in parallel with 5pF. A DC voltage on this pin controls the internal/ external CVBS and AUDIO selection where the following table gives the various possibilities: Vpin 16 (dc) <0.5V Between 3V &5V >7.5V Internal CVBS on off off External CVBS/Y off on(Y) on (CVBS) CSVHS signal off on off Luminance notch on off on Audio signal Internal External External Model TV S VHS AV
filter tuning
13 15
Internal CVS input External CVS input
14
Peaking control input
16
+ Chroma (SVHS) input
AV switch input
17
Brightness Control input
18 19 20
B-output G-output R-output
21
RGB insertion + Blanking input
22 23 24
R-input for insertion G-input for insertion B-input for insertion
The brightness control voltage present at pin 17 controls the dc level of the RGB outputs where a brightness control voltage of 0 5V at pin 17 results in a black level shift at the RGB outputs of 1V about the nominal. The RGB output signals are supplied to the video output stages. For nominal input signals (i.e. CVBS and -(R-Y)/-(B-/Y) signals) and for nominal gain settings then the RGB output signal amplitudes (black-to-white)are typically 4V with a black level at approximately 1.3V. The blanking level is 0.8V and maximum peak white level is 6.0V Since the RGB output stages are made with emitter followers, the maximum sink current is limited to 1.5mA. Therefore the current delivered from the video output stages to the RGB pins must not exceed 1.5mA.When the RGB switch control (pin 21) voltage exceeds 4V then the RGB outputs are blanked and consequently on-screen display signals (OSD) can be supplied to the video output stages. The RGB insertion signals are selected by means of a fast switch control.With the conditions that:0.8V
20
Pin No.
25
Name
Contrast Control input
Function Description
The contrast control input of 0 5V at pin 25 gives a 20dB gain range at the RGB outputs. When one of the RGB output signals exceed 6V, it is then clipped to 6V and also the gain of the RGB output amplifiers can be reduced by adapting the contrast voltage using the peak white limiter (PWL) current, The PWL current during PWL operation is 100 A. The saturation control input voltage, present at pin 26, is 0 5V. this corresponds to a 52dB gain range of the -(R-Y)/-(B-Y) signals. If the Vpin27>6V, the ASM does not search for NTSC signals and the decoder application can only be PAL or PAL/SECAM. The output impedance with an external resistance of 22K to 8V is then approximately 500 .The hue control input pin should be provided with a voltage of 0 to 5V for NTSC decoder applications; within this voltage range the input impedance is very high (MOS input). The -(R-Y)/-(B-Y) signals, present at pins 11 and 12 of the TDA4661, are coupled via 100nF (these capacitors are also clamping capacitors) to pins 29 and 28. The maximum input current of both pins is 1 A. With 100nF coupling capacitors the voltage drop over a line period is less than 0.5mV Since the output impedance of pin 11 and 12 of the TDA then the signal tracks between the TDA 4661 4661 is maximal 400 and the TDA8362 should have good ground shielding and be as short as possible. The output impedance of pins 30 & 31 is approximately 250 when PAL/NTSC signals are identified. For SECAM signals the output impedance is very high (output switch is open) and any external circuity is not loaded (i.e. the demodulator output of the TDA 8395). During the line/field blanking periods of the sandcastle pulse, the demodulator outputs are set to the correct dc levels so as no offsets exist. The-(R-Y)/-(B-Y) outputs are coupled, via 1nF, to pins 16 & 14 of the TDA4661 respectively. A SECAM reference signal (4.43 MHz only ) is delivered directly from pin 32 of the TDA8362 to pin 1 of the TDA8395. When SECAM siganals are identified by the TDA8395, it withdraws a current of 150 A from pin 32.The SECAM interface communicates the ident information via this current to the ASM. If PAL/NTSC signals are not already identified by the ASM and the identified signal is 50 Hz then an acknowledge will be given by ASM to the TDA8395 by setting the voltage at pin 32 to 5V. With SECAM identified, the SECAM reference signal signal is gated and present at pin 32 only during the field retrace period. When PAL/NTSC is identified, the output level is 1.5V. One of the important aspects of the PLL is the loop filter connected to pin 33. It ensures that the PLL synchronizes the VCXO, in both frequency and phase, with the incoming burst (average burst for PAL standards). It also determines the dynamic performance of the loop where the important parameters are: -Noise immunity - Transient response -Acquisition behaviour The remaining aspects of the PLL/VCXO are static phase error and X-tal type used at pins 34 or 35. For small static phase errors (less than 5 the requirements are: -The combined buest phase detector and VCXO sensitivity are high. The offset of the burst phase detector output is small. -The external leakage current at pin 33 is small. The TDA8362 determines the first two; the third is determined by the external leakage resistance of pin 33 to ground. Deviations in the VCXO free running frequency due to X-tal or X-tal load capacitance spreads have negligible influence on the static phase error because the combined phase detector and VCXO sensitivity is high. The static phase error is due to the internal offset of the phase detector output and the external leakge current at pin 33. Static phase errors much less than 5 were measured.
26 27
Saturation Control Input Chroma output + Hue Control Input
28 29
B-Y input R-Y input
30 31
R-Y output B-Y output
32
4.43 MHz output for TDA8395
33
Loop Fitter (Burst Phase Detector)
21
Pin No.
34 35
Name
3.58MHz X-TAL Connection 4.43MHz X-TAL Connection Start Horizontal Oscilator
Function Description
To ensure correct operation of both colour processing and sync calibrationcircuits in the TDA8362, 4.43 X-tals must not be connected to pin 34 and 3.58 X-tals must not be connected to pin 35. The minimum current required for the start function is 6.5mA, then the voltage will be approx. >7.2V. The voltage at pin 36 may not exceed 8.8V, so depending on the application external clamping is necessary. If the start voltage is below approximately 5.8V then the horizontal output will be disabled. The decoupling should be sufficent because the start pin supplies the circuitries needed for the horizontal output. (The oscillator references, however, are supplied by the bandgap.) This pin must be connected directly to the supply pin when no start function is used. This open collector output drives the horizontal output stage. The maximum allowable current is 10mA. The saturation voltage then will be 0.3V. A sandcastle signal is available at this pin for external use. The signal levels are: Burst typ 5.3V, the output impedance is approx. 1k Flyback typ 3 V, impedance defined by the flyback circuit. Field blanking typ 2 V, the output impedance is approx. 4k The flyback input signal is used for the PHI-2 loop and RGB line blanking. Pin 38 requires a current of only a few in order to reach the 3V flyback clamping level. Detection of the flyback pulse (and thus RGB blanking) only occurs when the input current is at least 100 A. (The maximum allowable current is 300 A.) Additonal remarks: -Due to an internal base current at pin 38, the voltage level becomes 3V when the pin is not loaded. -During start-up pin 38 is forced low by 2mA.
36
37
Horizontal Output
38
Flyback input +Sandcastle Output
39
-2 loop Filter +X-Ray Protection
The phase error on screen due to storage time variations depends on the PHI-2 loopgain. In principle this figure is fixed but will decrease when an additional resistor comes in parallel to the capacitor at pin 39. The time constant is defined by the external capacitor. The voltage to switch on the X-ray protection is 6V. (min.) The PHI-1 behaviour depends on both the loop filter externally connected at pin 40 and the PHI-1 output currents. The PHI-1 output current has been made switchable during scan (a fixed current ratio) in order to avoid the need of switching the loop filter for normal-and noisysignals. This implies the loop filter can be optimised for both VCR-and noisy-signals. The feedback signal is derived by sensing the deflection coil current by means of a resistor. The feedback signal is related to the vertical ramp signal. The ramp amplitude should be 1Vpp while the DC level is 2.5V typical. The guard levels are 1 and 4Vtyp. In order to filter horizonatal into a capacitor is mounted at the input. The vertical ramp is defined as: -DC clamping voltage of 2V -AC amplitude of 1.5Vpp for a 50Hz field signal -AC amplitude of 1.25Vpp for a 60Hz field signal The AC amplitude of 1.5V is important for optimal pre-correction and 50/60Hz gain correction.
40
-1 loop Filter
41
Vertical Feedback Input
42
Vertical Ramp Generator
22
Pin No.
43
Name
Vertical Output.
Function Description
The vertical drive output is fed to the deflection-IC. The available output current is minimal 1mA, and the available output voltage is 4-5V. During retrace the drive output has to be constant and equal to the low level of 0.3V. The AFC steepness can be influenced by the Q of the tuned circuit and output impedance output resistors at the AFC output pin (60k intermally). Due to current reserve the steepness can be reduced by a factor 4-5 while the output voltage swing remains 6V. Some small video information can still be present at the AFC output pin although a S&H function is applied. This video information can be filtered by an external capacitor at this pin. The AFC output voltage changes from approximately 0.5-6.3V. The output impedance of AFC circuit is 50k . DC coupling is allowed, so no series capacitors are necessary. The circuit matches the required load impedance for commonly used SAW filters(2k/3pF). The tuner AGC is an open collector output which is acting as a variable current source to ground. Normally the output application circuit is designed for an output current swing of 1-2mA. In order to improve the dynamical behaviour during channel switching it is possible to sink with a current of approximately 12mA maximal. The max voltage is Vcc+1V. Increasing of the AGC time constant is achieved by increasing the AGC capacitor on pin 48. Increasing this capacitor also results in an improvement in the catching and holding range of the ident circuit. The control range at this pin is 0.5-4.5V. Characteristics: The tuner take over adjust voltage versus IF input signal is a linear function with a slope of approximately 20mV/dB. (Measured at an AGC output current of 1mA) In order to achieve a stable AGC control at strong signals a decoupling capacitor of at least 1nF at this pin is required. Alignment: With the potentiometer connected to pin 49 of the TDA8362, the tuner take over point can be adjusted when an RF signal is applied to the aerial input of the tuner. The DC output voltage is 3.3V. The volume controlled output signal is AC coupled to the sound output amplifier. The output impedance is 250 . This pin defines the DC voltage at the deemphasis and sound output. The pin forms a low pass filter in the DC feedback loop. This implies that the sound amplitude for lower frequencies, < fk, is attenuated. A bigger capacitor, in order to decrease fk, is allowed but increases the DC setting time. Decoupling Bandgap Supply
44
AFC Output
45,46
IF Input
47
Tuner AGC Output
48
AGC Decoupling Capacitor Tuner Take-Over Adjustment
49
50 51
Audio Input Decoupling Sound Demodulator
52
Decoupling Bandgap Supply
23
TDA4661(Base Band Delay Line)
(1) Features · Two comb filters, using the switched-capacitor technique,for one line delay time (64µs) · Adjustment free application · No crosstalk between SECAM colour carriers · Handles negative or positive colour-difference input signals · Clamping of AC-coupled input signals(±(R-Y)and±(B-Y)) · VCO without external components · 3MHz internal clock signal derived from a 6MHz VCO, line-locked by the sandcastle pulse (64µs line) · Sample-and -hold circuits and low-pass filters to suppress the 3 MHz clock signal · Addition of delayed and non-delayed output signals · Output buffer amplifiers · Comb filtering functions for NTSC colour-difference signals to suppress cross-colour (2) General Description The TDA4661 is an integrated baseband delay line circuit with one line delay. It is suitable for decoders with colour-difference signal outputs±(R-Y)and±(B-Y). (3)Block Diagram
(R-Y)
16
SIGNAL CLAMPING LINE MEMORY SAMPLEANDHOLD LP
11 (R-Y)
colour-difference input signals
pre-amplifiers addition stages output buffers colour-difference output signals
(B-Y)
14
SIGNAL CLAMPING LINE MEMORY SAMPLEANDHOLD LP 2 3 MHz shifting clock FREQUENCY PHASE DETECTON
12 (B-Y)
VP1
0
analog supply
n.c. n.c. n.c. n.c.
TDA4661
6 13 15
5 sandcastle pulse input
SANDCASTLE DETECTOR
DIVIDER BY 192 6MHz VCO 1
LP 10 GND1 VP2 digital supply
DIVIDER BY 2 3
7 4,8
I.c.
GND2
(4)Pin Description SYMBOL PIN
Vp2 n.c. GND2 i.c. SAND n.c. i.c. i.c. 1 2 3 4 5 6 7 8
DESCRIPTION
+5V supply voltage for digital part not connected ground for digital part (0V) internally connected sandcastle pulse input not connected internally connected internally connected
SYMBOL PIN
Vp1 GND1 V0 (R-Y) V0 (B-Y) n.c. V1 (B-Y) n.c. V1 (R-Y) 9 10 11 12 13 14 15 16
DESCRIPTION
+5V supply voltage for analog part ground for analog part (0V) ± (R-Y) output signal ± (B-Y) output signal not connected ± (B-Y) input signal not connected ± (R-Y) input signal
24
TDA8395 (Secam Decoder)
(1) Features Fully integrated filters Alignment free For use with baseband delay (2) Description The TDA8395 is a self-calibrating,fully integrated SECAM decoder. The IC should preferably be used in conjunction with the PAL/NTSC decoder TDA8362 and with the switch capacitor baseband delay circuit TDA4661. The IC incorporates HF and LF filters, a demodulator and an identification circuit (Iuminance is not processed in this IC). A highly stable reference frequency is required for calibration and a two-level sandcastle pulse for blanking and burst gating. (3) Block Diagram
CLOCHEref 100 nF 7 220 nF 7 3 6 2 PLLref Vp GND TEST
BANDGAP
TUNING
TUNING
TDA8395
CVBS
16 ACC
CLOCHE FILTER
PLL
DEEMPHASIS
9 INTERFACE CONTROL IDENTIFICATION OUTPUT STAGE 10
(R-Y)
(B-Y) 1 fref/IDENT 15 SAND
(4) Pin Description SYMBOL PIN fp1/IDENT 1 TEST 2 Vp 3 n.c. 4 n.c. 5 GND 6 CLOCHEref 7 PLL ref 8 -(R-Y) 9 -(B-Y) 10 n.c. 11 n.c. 12 n.c. 13 n.c. 14 SAND 15 CVBS 16
DESCRIPTION reference frequency input/identification input test output positive supply voltage not connected not connected ground Cloche reference filter PLL reference -(R-Y) output -(B-Y) output not connected not connected not connected not connected sandcastle pulse input video (chrominance) input
25
AT24C08PC (EEPROM)
(1)Features IC Bus compatible Low power CMOS Technology 16 Byte page write Buffer Self-Timed write cycle with Auto-Clear 100,000 program/Erase cycles 100 Year Data Retention Optional High Endurance Device Available (2)General Description The AT24C08PC is a 8K bit serial CMOS E2PROM internally organized as 1024x8bits. Catalyst's advanced CMOS technology substantially reduces device power requirements. The AT24C08PC features a 16 byte page write buffer. (3) Block Diagram
EXTERNAL
D OUT AKC Vcc Vgg WORD ADDRESS BUFFERS COLUMN DECODERS SENSE AMPS SHIFT REGISTERS
SDA
START/STOP LOGIC
XDEC TEST CONTROL LOGIC
64
E2 PROM 64 128
DATE IN STORAGE
HIGH VOLTAGE/ TIMING CONTROL SEL A0 A1 A3 STATE COUNTERS SLAVE ADDRESS COMPARATORS
(4) Pin Description PIN 1-3 4 5 6 7 8 SYMBOL A0,A1,A2 Vss SDA SCL TEST Vcc DESCRIPTION Device Address Inputs Ground Serial Data/Address Serial Clock Connect to Vss +5V Power supply
26
AN5515 (TV Vertical Defelection Output Circuit)
(1)Features Low power consumption, direct deflection coil driving capability (Flyback voltage two times as high as supply voltage is supplied during flyback period only) High breakdown voltage: 50V (2)General Description
5.9±0.25 3.6 8.2±0.3 7.8±0.25
1.8R
7 6 5 4 3 2 1
1.2 1.45
17.7±0.3
15.3±0.3 7.6±6.2
0.6±0.1
1.2±0.1
(3)Block Diagram
1.8
Driver
Output
Pulse Amp.
1
2
3
4
5
6
3.5±0.3
2.54
1.4
7
(4)Pin Description PIN 1 2 3 4 5 6 7 DESCRIPTION GND Output Supply Voltage for Output Input Trigger Pulse Input Pulse Amp. Output Vcc
27
16.9±0.3
CF70200 (Teletext Decoder)
(1) Features Eight pages of on-chip Display RAM Europe-wide solution Automatic FLOF & TOP decoding Flicker-free packet 26 processing on chip Program delivery control Minimum software requirement Menu page capability Instantaneous page memory clear 75 RGB outputs Digital PLL Upgrade path from UNITEXT (2) Block Diagram
RAM SYNC VIDEO CSB SYNC SWITCH PLL RGBSET REF 75 DRIVER R G B
RTSK PROCESSOR
VDP
BLANK
SDA TDATA TCLK TELETEXT FRONT END IC INTER FACE SCL
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14
PIN NAME TEST5 SYNC CVBS DVcc RSTB CLKIN DGND T1 T4 TDATA TCLK CSB MUTE T2
DESCRIPTION Test Pin The output of an internal sync switch Video input to sync switch +5V System reset active low System clock 13.875MHz Ground Test Pin Test Pin Teletext Data Teletext Clock Signal Composite Sync Signal Mute Test Pin
PIN 15 16 17 18 19 20 21 22 23 24 25 26 27 28
PIN NAME WIND T3 SCL SDA BLK B AVcc G R AGND RGBSET REF FLAG1 FLAG2
DESCRIPTION WIND Test Pin I2C Clock Line I2C Data Line Blanking Display Data +5V Display Data Display Data Ground Adjustment for theRGB,Blank levels Internal Reference Pin System Information System Information
28
CF72306
(1) Features Forms a custom 2-chip solution when used with an ASICTEXT decoder Low power 1um CMOS Standard 20 pin/300mH package Tolerates a range of video distortions Operates with 13.875MHz fundamental mode crystal (2) Block Diagram
1 SIG 10pF SSIG CSIG 220pF 13.87MHz 15pF OSC 1 15pF OSC 1 AVGC CREF 220pF AGND 2 BIAS BIAS OSC 13.875MHz FREOUENCY MULTIPLER 69MHz CLK DISADLE DATA SLICER AGND 1 VBIAS ADAPTIVE SYNC SEPARATOR I BIAS
SCANOUT SYNC DGND 1 WIND DVCC OSCOUT SCANOUT DGND 2 TCLK TSTAPLB
(3) Pin Description PIN 1 2 3 4 5 6 7 8 9 10 SIGNAL TSIG SSIG CSIG AGND1 OSC1 OSC2 AVCC CREF AGND2 BIAS DESCRIPTION Video Sync Input 1 Video Sync Input 2 Video Data Input Analogue Ground 13.875MHz Oscillator 13.875MHz Oscillator Analogue Vcc Video Data Reference Input Analogue Ground Internal Reference PIN 11 12 13 14 15 16 17 18 19 20 SIGNAL TSTAPLB TCLK TDATA DGND2 OSCOUT DVCC WIND DGND1 SYNC SCANOUT DESCRIPTION Test/Application Teletext Clock Teletext Data Digital Ground Oscillator Output Digital Vcc Timing Signal Digital Ground Separated Sync Output Test Scan Output
29
SDA5648 (VPS/PDC Decoder)
(1) Features Single-chip receiver for PDC data, broadcast either - in Broadcast Data Service Packet (BDSP) 8/30/2 according to CCIR teletext system B, or - in dedicated line no. 16 of the vertical blanking interval(VPS) Reception of Unified Data and Time (UDT) broadcast in BDSP 8/30/1 Low external components count On-chip data and sync slicer IIC-Bus interface for communication with external micro-controller Selection of PDC/VPS operating mode software controlled by IIC-Bus register Pin and software compatible to VPS Decoder SDA5642 Supply voltage : 5 V ±10 % Video input signal level : 0.7 Vpp to 1.4 Vpp Operating temperature range : 0 to 70°C (2) General Description The CMOS circuit SDA 5648 is intended for use in video cassette recorders to retrieve control data of the PDC system from the data lines broadcast during the vertical blanking interval of a standard video signal. The SDA 5648 is devised to handle PDC data transported either in Broadcast Data Service Packet(BDSP) 8/30 format 2 (bytes no. 13 through 25) of CCIR teletext system B or in the dedicated data line no. 16 in the case of VPS. Furthermore it is able to receive the Unified Date and Time (UDT) information transmitted in bytes no. 5 through 21 of packet 8/30 format 1. Operating mode (PDC/VPS) is selected by a control register which can be written to via the IIC-Bus interface. (3) Block Diagram
PD1 PD2/VCO 2 IREF VCO 1 CVBS VCS DATASyncSlicer Clock-PLL
SDA DataAcquisition I2 C Businterface SCL CSO
Timing
VDD A VDD
VSS A
VSS D DAVN EHB TI
30
(4) Pin Description PIN 1 2 3 4 SYMBOL Vss SCL SDA CS0 DESCRIPTION GND Serial Clock input of I2C-Bus Serial Clock input of I2C-Bus Chip select 20H/21H, when pulled low 22H/23H , when pulled high Video Composite Sync output VPS/PDC data recognition Identification signal for first half frame PIN 8 9 10 11 12 13 14 SYMBOL TI PD1 PD2/ VCO2 VCO1 IREF CVBS VDD DESCRIPTION Test Input Phase detector/charge pump output Connector of the Loop filter for the SYSPLL Oscillator control input Reference current CVBS input Supply voltage (+ 5 V nom.)
5 6 7
VCS DAVN EHB
31
TDA 4601(SMPS Controller)
(1) Features Direct control of the switching transistor Low start-up current Reversing linear overload characteristic Base current drive proportional to collector current Protective circuit in case of disturbance (2) General Description The integrated circuit TDA4601 is designed for driving, controlling and protecting the switching transistor in self-oscillation flyback converter power supplies as well as for protecting the overall power supply unit. (3) Block Diagram
Start-Up Circuit
Control Amplifier Standby Operation Trigger Start Hold
Base Current Amplifier
Coupling-c Charging Circurt Voltage Control Overload Identification Control Logic Base Current Switch-Off
Reference Voltage
Zero Passage Identification
Collector Current Simulation
Ext. Trigger Blocking Function
1
2
3
4
5
6
7
8
9
(4) Pin Description PIN 1 2 3 4 5 6 7 8 9 DESCRIPTION VREF output Zero passage identification Input control amplifier,overload amplifier Collector current simulation Connection for additional protective circuit Ground DC output for charging coupling capacitor Pulse output-driving of switching transistor Supply voltage
32
TDA9800 (VIF-PLL demodulator and FM-PLL detector)
(1) Features Suitable for negative vision modulation Gain controlled 3-stage IF amplifier; suitable for VIF frequencies up to 60 MHz True synchronous demodulation with active carrier regeneration (ultra-linear demodulation, good intermodulation figures, reduced harmonics and excellent pulse response) Peak sync AGC Video amplifier to match sound trap and sound filter AGC output voltage for pnp tuner; adjustable take over point (TOP) AFC detector without extra reference circuit Alignment-free FM-PLL detector with high linearity Stabilizer circuit for ripple rejection and to achieve constant output signals (2) General Description Monolithic integrated circuit for vision and sound IF signal processing in TV and VTR sets. (3) Block Diagram
VP - 5V TPLL 20 18 INTERNAL REFERENCE VOLTAGE 3-stage IF amplifier 3.6V C AF FREQUENCY DETECTOR AND PHASE DETECTOR VIDEO DEMODULATOR VIDEO AMPLIFIER FM.PLL TRAVELLING WAVE DIVIDER 6 17 2f PC 16 AFC
15 AFC AF AMPLIFIER 9 VO AF 10
+
VCO
1 IF input VI PC 2
4
TDA9800
TUNER AGC IF AGC AGC DETECTOR
sound mute
phase adjust 3 take over point 12 19 5 8 n.c. tuner AGC output CAGC sound MUTE 13
BUFFER AND NOISE CLIPPING 14 11
7
CVBS 2 V (P-P)
SOUND TRAP 1 V (P-P)
SOUND FILLTER
MEH191-1
FIG.1 Block diagram.
33
(4) Pin Description PIN 1 2 3 4 5 6 7 8 9 10 SYMBOL Vi IFa Vi IFb TADJ PADJ MUTE TPLL Vo CVBS n.c. VO AF CAF DESCRIPTION Vision IF differential input Vision IF differential input tuner AGC take over adjust(TOP) phase detector adjust mute switch input PLL time constant OF phase detector CVBS(positive) output signal not connected audio frequency output signal decoupling capacitor of audio frequency amplifier PIN 11 12 13 14 15 16 17 18 19 20 SYMBOL Vi IC TAGC Vo VID Vi VID AFC VCO1 VCO2 GND CAGC VP DESCRIPTION sound intercarrier input signal tuner AGC output video and sound intercarrier output signal video input signal to buffer amplifier automatic frequency control output VCO reference circuit for 2 fPC VCO reference circuit for 2 fPC GND AGC capacitor positive supply voltage
34
TDA9802 (Multistandard VIF-PLL demodulator and FM-PLL detector)
(1) Features Suitable for negative vision modulation Gain controlled 3-stage IF amplifier; suitable for VIF frequencies up to 60 MHz True synchronous demodulation with active carrier regeneration (ultra-linear demodulation, good intermodulation figures, reduced harmonics and excellent pulse response) Peak sync AGC for negative modulation, e.g. B/G standard Peak white AGC for positive modulation, e.g. L standard Video amplifier to match sound trap and sound filter AGC output voltage for tuner; adjustable take over point (TOP) AFC detector without extra reference circuit Alignment-free FM-PLL detector with high linearity Stabilizer circuit for ripple rejection and to achieve constant output signals (2) General Description Monolithic integrated circuit for vision and sound IF signal processing in Multistandard TV and VTR sets.
VP - 5V TPLL 20 18 INTERNAL REFERENCE VOLTAGE 3-stage IF amplifier 3.6V C AF FREQUENCY DETECTOR AND PHASE DETECTOR VIDEO DEMODULATOR VIDEO AMPLIFIER
mute
2f PC 6 17 16
AFC
15 AFC AF AMPLIFIER 9 10 VO AF
TRAVELLING WAVE DIVIDER
VCO
+
1 IF input VI PC 2
FM.PLL
4
TDA9802
TUNER AGC IF AGC AGC DETECTOR
sound mute
phase adjust 3 take over point 12 19 5 8 13
BUFFER AND NOISE CLIPPING 14 11
7
CVBS 2 V (P-P)
tuner AGC output
CAGC
SOUND TRAP 1 V (P-P) sound MUTE negative/ positive modulation
SOUND FILLTER
MEH115
FIG.1 Block diagram.
35
(4) Pin Description PIN 1 2 3 4 5 6 7 8 SYMBOL Vi IFa Vi IFb TADJ PADJ CBL TPLL Vo CVBS STD DESCRIPTION Vision IF differential input Vision IF differential input tuner AGC take-over adjust (TOP) phase detector adjust black level capacitor, mute switch input PLL time constant OF phase detector CVBS(positive) output signal standard switch negative = HIGH positive = LOW audio frequency output signal decoupling capacitor of audio frequency amplifier PIN 11 12 13 14 15 16 17 18 19 20 SYMBOL Vi IC TAGC Vo VID Vi VID AFC VCO1 VCO2 GND CAGC VP DESCRIPTION sound intercarrier input signal tuner AGC output video and sound intercarrier output signal video input signal to buffer amplifier automatic frequency control output VCO reference circuit for 2 fPC VCO reference circuit for 2 fPC GND AGC capacitor positive supply voltage
9 10
VO AF CAF
36
TDA9830 (TV sound AM-demodulator and audio source switch)
(1) Features Adjustment free wideband synchronous AM demodulator Audio source-mute switch(low noise) Audio level according EN55049 5 to 8 V power supply or 12 V alternative Low power consumption (2) General Description The TDA9830, a monolithic integrated circuit, is designed for AM-sound demodulation used in L and L' standard. The IC provides an audio source selector and a mute switch. (3) Block Diagram
VP1 or VP1
13 14 4 + SUPPL Y BANEGAP
11
TDA9830
12 mute (closed) 10 input : open = pin 9 closed = pin 0 dB 8 AF output
16 IF signal 1
AGC CONTROL
AGC DETECTOR
3
6
7
9
AM output
AM input
external input
(4) Pin Description PIN 1 2 3 4 5 6 7 8 SYMBOL IFIN n.c. CAGC CREF n.c. AMOUT AMIN AFOUT DESCRIPTION sound IF differential input signal not connected AGC capacitor REF voltage filtering capacitor not connected AM demodulator output input signal (from AM) to audio switch output signal from audio switch PIN 9 10 11 12 13 14 15 16 SYMBOL EXTIN SWITCH Vp2 MUTE GND Vp1 n.c. IFIN DESCRIPTION input signal (from external) to audio switch switch input select control supply voltage +12V (alternative) mute control ground (0 V) supply voltage +5 to +8 V not connected sound IF differential input signal
37
TDA1519B (BTL or STEREO audio amplifier)
(1) Features Requires very few external components for Bridge Tied Load (BTL) Stereo or BTL application High output power Low offset voltage at output (important for BTL) Fixed gain Good ripple rejection Mute/stand-by switch Load dump protection SC and DC short-circuit-safe to ground and VP Thermally protected Reverse polarity safe Capability to handle high energy on outputs (VP = 0 V) No switch-on/switch-off plop Protected against electrostatic discharge Identical inputs (inverting and non-inverting) Compatible with TDA1519A (except output power)
(2) General Description The TDA1519B is an integrated class-B dual output amplifier in a 9-lead single in-line (SIL) plastic medium power package. The device is primarily developed for car radio applications. (3) Block Diagram PRINTING 1 NINV non-inverting input 2 GND1 ground (signal) 3 RR supply voltage ripple rejection 4 OUT1 output 1 5 GND2 ground (substrate) 6 OUT2 output 2 7 Vp positive supply voltage 8 M/SS mute/stand-by switch 9 INV inverting input
1
mute switch Cm 60k
VA 183
power stage
4
18.1 k
Vp
+ 8
standby switch
VA
standby reference voltage
15k
x1
3
+ +
mute switch
15k
mute reference voltage
TDA1519B
18.1 k
183
power stage
6 9
VA Cm 60k input reference voltage
+
mute switch
signal ground 2
Vp
7 5
power ground (substrate)
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MC14053BCP (IC CMOS LOGIC)
(1) Features Triple Diode Protection on Control Inputs Switch Function is Break Before Make Supply Voltage range - 3.0 Vdc to 18 Vdc Linearized transfer characteristics (2) General Description The MC14053B analog multiplexer are digitally controlled analog switches. The MC14053B effectively implements an SPDT solid state switch. The device features low ON impedance and very low OFF leakage current. Control of analog signals up to the complete supply voltage range can be achieved. (3) Block Diagram
MC14053B Triple 2-Channel Analog Multiplexer/Demultiplexer
6 11 10 9 12 13 2 1 5 3
Inhibit A B C X0 X1 Y0 Y1 Z0 Z1 Z 4 Y 15 X 14
VDD = Pin16 VSS = Pin8 VEE = Pin7
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CP-350 CIRDUIT DESCRIPTION
The function of the circuits used in CP-350 are described in this chapter. For the component numbers used in this description, refer to the circuit diagram.
1. Small Signal Part with TDA8362
TDA8362 is realized in BIMOS process; the high frequency bipolar process is used for video processing and the MOS process is used for the digital part. TDA8362 combines all small signal functions, except the tuning, required for a colour television receiver. Newly developed internal circuitry, such as integrated luminance delay line, chroma bandpass and trap, PLL sound demodulator and switches, reduce the number of required pins, external components and alignments. The reference tuned circuit is the only remaining alignment for this 52 pins (S-Dil) TV-processor. The alignment-free SECAM add-on colour decoder circuit (TDA8395) can be used for applications with automatic standard switching. The internal functions of TDA8362 are - Completely symmetrical AC-coupled vision I.F. amplifier and synchronous video demodulator - A.G.C. detector suited for positive and negative modulation - Tuner A.G.C., for PNP tuners - Sample and hold A.F.C. circuit, with internal 90 phase shift - Video pre-amplifier - Inputs and switches for external audio, CVBS and S-VHS signals - Sound I.F. limiter, automatic PLL demodulator and pre-amplifier with DC volume control. - Separate supply pin to start the horizontal circuitry from the mains rectifier - Horizontal synchronization circuit with 2 control loops - Vertical synchronization (divider system), automatic 50/60Hz adaption - Vertical and horizontal drive circuits - PAL/NTSC colour decoder, with automatic standard switching - Chroma filters (bandpass and trap) with automatic system adaption - Luminance delay line - Peaking circuit is the luminance channel - Mute function - X-ray protection possibility. 1.1. Vision I.F. Amplifier, Video Demodulator and Identification Circuit. The vision I.F. amplifier consists of three AC-coupled differential stages. The gain control per stage is more than 20dB, which results in a total gain control of 64dB min. The amplifier is completely symmetrical, which has the advantage of a less critical application; the I.F. amplifier inputs can be coupled directly to the SAW-filter output. The input impedance is 2k in parallel with 3pF. The input sensitivity for on-set of A.G.C. is 70 V (typ.), for I.F. frequencies between 38.9MHz and 58.75MHz. The reference carrier for the video demodulator is obtained via passive regeneration of the picture carrier. The reference tuned circuit is connected between pin 2 and 3. The IC and handle positive and negative modulated signals, the polarity of the demodulation can be switched at pin 1(open=neg. modulation, high=pos. modulation). A transmitter identification circuit operates independently of the synchronization circuit, to allow separate use of the front-end section and the display section of the TDA8362.
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1.2. A.G.C., Tuner A.G.C. and A.F.C. The A.G.C. detector operates at top-sync level for signals with negative modulation and at peak-white level for positive modulated signals. This A.G.C. detector is gated for negative modulated signals to reduce sensitivity to impulsive noise. The time constant capacitor (C216) is connected externally at pin 48. The tuner AGC take-over point can be set by adjusting the DC-voltage at pin 49, with a potentiometer of 10k (R010). The tuner A.G.C. (pin 47) is an open collector output stage with an output swing of 2mA min. the voltage swing, required by the tuner, can be obtained with an external resistor network, connected at pin 47. Pin 47 may rise 2V above the actual supply voltage level for min. gain. The A.F.C. circuit is driven by the same reference signal as the video demodulator. A sample and hold circuit avoids video bread-through from the video demodulator to the A.F.C. voltage. The A.F.C. output voltage range is from 0 to 8V. 1.3. Sound Circuit The sound carrier which is present at the video output pin 7 is fed via the sound bandpass to the sound input at pin5. This has a double function; sound I.F. input (AC) and volume control (DC). The filtered intercarrier signal is fed to an amplifier/limiter circuit and demodulated by a PLL demodulator. This PLL demodulator tunes automatically to the incoming frequency, hence no alignment is required. The A.F. signal (pin 50) has an amplitude of 700mVrms at maximum volume control setting (f = 50KHz). This volume control voltage is between 0 and 5V. The de-emphasis capacitor (CC211) is connected externally at pin 1. The noncontrolled audio signal (Peri-television) is also obtained from pin 1 via a amplifier buffer stage (Q730 & Q741) and has an amplitude of 500mVrms (f=300KHz). Audio input signal from an external source with an amplitude up to 350mVrms(+/- 6dB) can be fed to pin 6. The audio switch is controlled via the pin 16, as described in Chapter 1.8. The volume control operates upon the external audio input signal, when TDA8362 is switched to the external mode. 1.4. Horizontal and Vertical Synchronization The incoming video signal, pin 15 for the video signal is fed to the synchronization separator circuit. Internally the black level and the top sync level are detected, next the synchronization pulses are amplified to a fixed level and sliced at 50% of that level. In this way a very good synchronization performance is obtained. The separated synchronization pulses are fed to the first phase detector circuit and to the coincidence detector. The components which determine the loop gain of the first phase detector are connected at pin 40 (CC213, C218 and RC222). The coincidence detector is only used to detect whether the line oscillator is synchronized, not for transmitter identification. The line oscillator is running at twice the line frequency and locked to the X-tal controlled oscillator frequency of the colour decoder, consequently no adjustment is required. The freerunning frequency has a maximum deviation of 2% compared to the nominal frequency. The second phase detector generates the pulses for the horizontal driver stage (pin 37). The loop filter capacitor (CC212) is connected at pin 39. Horizontal shift can be obtained by a potentiomet