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8 7 6 5 4 3 2 1
AMD OPTERON(TM) PROCESSOR 200 SERIES
ATCA RDK SCHEMATIC
D PAGE INDEX HISTORY TABLE
SCHEMATIC PART NUMBER
D
SHEET TITLE
1 COVER PAGE--THIS PAGE
PID 42682
2 SYSTEM BLOCK DIAGRAM
SCHEMATIC CHANGE HISTORY
3 POWER AND GROUND SCHEME
REVISION DATE HISTORY
4 POWER SEQUENCE SCHEME
REV. A 2007-03-12 REV. A INITIAL RELEASE
5 CPU0 - HYPER TRANSPORTS
REV. B 2007-04-03 FIX TYPOS ON SHEET 1
ADD PIGEON POINT NOTICE ON SHEETS 37 AND 38
6 CPU0 - MEMORY I/F AND MISC.
7 CPU0 - POWERS AND GROUNDS
8 POWERS - CPU0 CORE VOLTAGE
9 POWERS - DIMM 0 AND 1 MEMORY VOLTAGE
10 DIMM 0 AND 1 FOR CPU0
C 11 DIMM 0 AND 1 TERMINATORS
C
1. THIS DOCUMENT MAY NOT REFLECT THE MOST RECENT CHANGES IN BOARD DEVELOPMENT
12 CPU1 - HYPER TRANSPORTS
AND DEBUG. ANY DEVELOPER INTENDING TO USE THIS SCHEMATIC AS A REFERNCE SHOULD
13 CPU1 - MEMORY I/F AND MISC.
CONTACT THEIR LOCAL FIELD APPLICATIONS ENGINEER, REGIONAL SALES OFFICE, OR
14 CPU1 - POWERS AND GROUNDS
PROGRAM MANAGER FOR SCHEMATIC UPDATES, DESIGN RECOMMENDATIONS AND PCB LAYOUT
15 POWERS - CPU1 CORE VOLTAGE
GUIDELINES. AMD ALSO RECOMMENDS A DESIGN REVIEW OF BOTH THE SCHEMATIC DIAGRAM
16 POWERS - DIMM 2 AND 3 MEMORY VOLTAGE
AND PCB LAYOUT BEFORE CONSIDERING PRODUCTION.
17 DIMM 2 AND 3 FOR CPU1
2. AMD RESERVES THE RIGHT TO CHANGE DESIGNS OR SPECIFICATIONS WITHOUT NOTICE.
18 DIMM 2 AND 3 TERMINATORS
CUSTOMERS ARE ADVISED TO OBTAIN THE LATEST VERSIONS OF PRODUCT SPECIFICATIONS,
19 HT2000 - HYPER TRANSPORT,PCI EXPRESS
WHICH SHOULD BE CONSIDERED IN EVALUATING A PRODUCT'S APPROPRIATENESS FOR A
20 HT2000 - PCI-X AND GE
PARTICULAR USE.
21 HT2000 - POWERS AND GROUNDS 3. AMD MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, FOR MERCHANTABILITY OR FITNESS
B 22 HT1000 - HYPER TRANSPORT,PCI-X,PCI,SATA,USB
FOR A PARTICULAR APPLICATION. IN NO EVENT SHALL AMD BE LIABLE FOR ANY INDIRECT, B
23 HT1000 - LPC,MISC, POWERS AND GROUNDS SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES AS A RESULT OF THE PERFORMANCE,
24 AMC AB CONNECTOR - A PORT
OR FAILURE TO PEFORM, OF ANY AMD PRODUCT OR DOCUMENTATION.
25 AMC AB CONNECTOR - B PORT
26 CLOCK SYNTHESIZER
(C)2007 ADVANCED MICRO DEVICES, INC. ALL RIGHTS RESERVED. AMD, THE AMD ARROW LOGO,
27 SUPER IO AMD OPTERON AND COMBINATIONS THEREOF ARE TRADEMARKS OF ADVANCED MICRO DEVICES, INC.
28 FLASH,USB,RJ-45,SERIAL,PUSH BUTTON
HYPERTRANSPORT IS A LICENSED TRADEMARK OF THE HYPERTRANSPORT TECHNOLOGY CONSORTIUM.
29 BASE I/F DUAL GE - PCI-X IS A REGISTERED TRADEMARK, AND PCIE IS A TRADEMARK, OF PCI-SIG.
30 BASE I/F DUAL GE - POWERS AND GROUNDS
OTHER NAMES USED IN THIS PUBLICATION ARE FOR IDENTIFICATION PURPOSES ONLY AND
31 FABRIC I/F DUAL GE - MAY BE TRADEMARKS OF THEIR RESPECTIVE COMPANIES.
32 FABRIC I/F DUAL GE - POWERS AND GROUNDS
33 10 PORT UNMANAGED GBIT SWITCH
A 34 POWERS - -48V, STANDBY, 3.3V AND 1.5V A
35 POWERS - 2.5V AND 1.2V
AMD OPTERON(TM) PROCESSOR ATCA RDK
36 ATCA ZONE1 AND ZONE 2 CONNECTOR (P10, J23)
37 PIGEON POINT BRD MANAGEMENT - IPM ATCA
38
39
PIGEON POINT
POWER SEQUENCER
BRD MANAGEMENT - IPM AMC AMD
ADVANCED MICRO DEVICES
1351 SOUTH SUNSET ST.
LONGMONT, CO 80501
40 ESD STRIP, MOUNTING HOLES AND MISC.
41..44 SIGNAL CROSS REFERENCE Title COVER PAGE
45..57 PART CROSS REFERENCE
Size B 42682 Rev: B
Date: 2007-04-03 Sheet 1 of 57
8 7 6 5 4 3 2 1
CR-2 : @ATCA_BLADE_LIB.SCHEMATIC(SCH_1):PAGE2
8 7 6 5 4 3 2 1
SYSTEM BLOCK DIAGRAM
D
D
FRONT DIMM 1 DIMM 3
PANEL
RJ45X2 DIMM 0 DIMM 2
DDR1 400 DDR1 400
128 BIT 128 BIT
2X GE DUAL GE
BACKPLANE CPU 0 HT X16 CPU 1
MARVELL 88E8062
AMD OPTERON 2XX AMD OPTERON 2XX
C BASE I/F C
940 PIN SOCKET 940 PIN SOCKET
HT X16
4X GE 2X GE DUAL GE
BACKPLANE
MARVELL 88E8062 2X GE
FABRIC I/F
PCI-E X4
PCI-E X4
PCI-E X4 HT2000
GBIT SWITCH 2X GE
AMC 0 PCI-E X4
MARVELL 88E612
B B
HT X8
-48V TO 12V
2X SATA FRONT PANEL 12V TO CPU CORE VOLTAGES
2X USB
HT1000 POWERS 12V TO MEMORY VOLTAGES
2X GE 12V TO BOARD VOLTAGES
AMC 1 2X SATA
PIGEON MICROCONTROLLER AND MEMORY
POINT POWER CONTROL
IPM CNTL VOLTAGE/TEMP. MONITORING
I2C COMMUNICATION
LPC
A A
1X COM AMD OPTERON(TM) PROCESSOR ATCA RDK
BIOS SIO
AMD
ADVANCED MICRO DEVICES
1351 SOUTH SUNSET ST.
LONGMONT, CO 80501
Title SYSTEM BLOCK DIAGRAM
Size B 42682 Rev: B
Date: 2007-04-03 Sheet 2 of 57
8 7 6 5 4 3 2 1
CR-3 : @ATCA_BLADE_LIB.SCHEMATIC(SCH_1):PAGE3
8 7 6 5 4 3 2 1
ATCA POWER AND GROUND SCHEME
D +3.3VSTBY
200W ATCA POWER MODULE
DC/DC +3.3STBY D
FUSE 48/3.3
-48V RTN A (LONG PIN) ORING FET
FUSE
-48V RTN B (LONG PIN) ORING FET
DC/DC 12VEN#(1ST ON)
EMI HOLD
UP
FUSE FILTER 48/12
-48V A (MEDIUM LONG PIN) ORING FET CAP
LOCAL_GND
FUSE
-48V B (MEDIUM LONG PIN) ORING FET
LOGIC_GND (LONG PIN)
+12V
+12V
MIC4684
C SWITCHING ISL6539 ISL6559 ISL6539 ISL6559 ISL6539 C
SWITCHING SWITCHING SWITCHING SWITCHING SWITCHING
PWRSEQ_8B
+5V 1A
PWRSEQ_8A
PWRSEQ_6A
PWRSEQ_6B
+3.3V VARIABLE VLTG +2.5V VARIABLE VLTG +2.5V
PWRSEQ_1
PWRSEQ_3
+1.5V 46A +1.25V 46A +1.25V
AS 12V IS ON
USB VLTG.
(3.3V)
(1.5V)
CPU0'S MEMORY CPU1'S MEMORY
ON AS SOON
BRD VLTG CPU0 VLTG. VLTG CPU1 VLTG. VLTG
+5V
+5V VCORE0 VCORE1
VMEM0+2.5V VMEM1+2.5V
VCORE0 VMEM0+2.5V VCORE1 VMEM1+2.5V
VMEM0_VTT VMEM1_VTT
VMEM0_VTT VMEM1_VTT
+3.3V
+3.3V
SC1592 SC1592 MIC5219 MIC5219
LDO LDO LDO LDO
B B
+2,5V 1.5A +2,5V 2A +2.5V 0.25A +2.5V 0.25A
PWRSEQ_2
PWRSEQ_2
PWRSEQ_7
PWRSEQ_7
BRD VLTG GE SWITCH VLTG.
CPU0 VDDA CPU1 VDDA
+2.5V +2.5VSW VDDA_P0 VDDA_P1
+2.5V +2.5VSW VDDA_P0 VDDA_P1
+1.5V +1.5V
A SC1592 SC1592 A
LDO LDO
SC1592 SC1592 EL7566 SC1592 SC1592
LDO LDO SWITCHING LDO LDO
+1.2V 2A +1.2V 1A
+1.2V 1.6A +1.2V 0.6A +1.2V 8.3A +1.2V 1.7A +1.2V 2A AMD OPTERON(TM) PROCESSOR ATCA RDK
PWRSEQ_9
PWRSEQ_9
PWRSEQ_9
PWRSEQ_4
PWRSEQ_4
PWRSEQ_5
PWRSEQ_5
CPU0 HT VDD CPU1 HT VDD
HT2000 VPCIE HT2000 VHT HT2000 CORE HT1000 CORE GE SWITCH VLTG.
AMD
VP0_HT VP1_HT
VHT_SB VHT_NB VCORE_NB VCORE_SB +1.2VSW
VP0_HT VP1_HT
VHT_SB VHT_NB VCORE_NB VCORE_SB +1.2VSW
ADVANCED MICRO DEVICES
1351 SOUTH SUNSET ST.
LONGMONT, CO 80501
Title POWER AND GROUND SCHEME
Size B 42682 Rev: B
Date: 2007-04-03 Sheet 3 of 57
8 7 6 5 4 3 2 1
CR-4 : @ATCA_BLADE_LIB.SCHEMATIC(SCH_1):PAGE4
8 7 6 5 4 3 2 1
OR
ON
HOT PLUG IN
-48V TURNED
+3.3VSTBY
STBY ALWAYS ON
(AS SOON AS -48V AVAILABLE)
IPMB ACTIVITIES
BMC_DCDC_EN
D SIO_PS_ON#
D
+12V +5V
+12V,+5V TURNED ON
+3.3V
3.3V TURNED ON
PWRON_SEQ1_GD
+2.5V +2.5VSW
2.5V TURNED ON
PWRON_SEQ2_GD
+1.5V
1.5V TURNED ON
PWRON_SEQ3_GD
C VCORE_NB VHT_NB C
HT2000 PWR RAIL ON
PWRON_SEQ4_GD
VCORE_SB +1.2VSW
HT1000 PWR RAIL ON
PWRON_SEQ5_GD
VMEM0+2.5V VMEM0_VTT VMEM1+2.5V VMEM1_VTT
MEMORY PWR ON
PWRON_SEQ6A_GD PWRON_SEQ6B_GD
VDDA_P0 VDDA_P1
CPU VDDA PWR ON
B B
PWRON_SEQ7_GD
VCORE0 VCORE1
CPU CORE PWR ON
PWRON_SEQ8A_GD PWRON_SEQ8B_GD
VP0_HT VP1_HT VHT_SB
CPU&HT1000 HT PWR ON
PWRON_SEQ9_GD
BMC_PAYLD_RST#
CPLD_PONRST#,NB_PWROK,SB_PWROK,BI_ETH_PWROK,FI_ETH_PWROK,CPU0_PWROK,CPU1_PWROK (COLD RESET)
A NB_RST#,SB_RESET#,BI_ETH_RST#,FI_ETH_RST#,LPC_RESET#,OPTERON0_RST#,OPTERON1_RST#
A
AMD OPTERON(TM) PROCESSOR ATCA RDK
WHEN POWER DOWN, THE ORDER IS REVERSED. AMD
ADVANCED MICRO DEVICES
1351 SOUTH SUNSET ST.
LONGMONT, CO 80501
Title POWER SEQUENCE SCHEME
Size B 42682 Rev: B
Date: 2007-04-03 Sheet 4 of 57
8 7 6 5 4 3 2 1
CR-5 : @ATCA_BLADE_LIB.SCHEMATIC(SCH_1):PAGE5
8 7 6 5 4 3 2 1
SIGNALS 0F HT: DIFF. 96 OHM IMPEDANCE BETWEEN CPU AND HT2000 SIGNALS 0F HT: DIFF. 90 OHM IMPEDANCE BETWEEN 2 CPUS
AMD OPTERON(TM) HT1 - 2/7 AMD OPTERON(TM) HT0 - 1/7
SKT0501 SKT0501
1 E18 L1_CLKIN1+ L1_CLKOUT1+ D7 1 1 L5 L0_CLKIN1+ L0_CLKOUT1+ AB4 1
1 E17 L1_CLKIN1- L1_CLKOUT1- C7 1 1 M5 L0_CLKIN1- L0_CLKOUT1- AB3 1
D 0 C18 L1_CLKIN0+ L1_CLKOUT0+ A7 0 0 L3 L0_CLKIN0+ L0_CLKOUT0+ AB1 0
19B8> IN P0HT1_CLKIN+<1:0>
0 B18 L1_CLKIN0- L1_CLKOUT0- A8 0
P0HT1_CLKOUT+<1:0>
OUT 19D8< 12D1> IN P0HT0_CLKIN+<1:0>
0 L2 L0_CLKIN0- L0_CLKOUT0- AA1 0
P0HT0_CLKOUT+<1:0>
OUT 12D4< D
19B8> P0HT1_CLKIN-<1:0> P0HT1_CLKOUT-<1:0> 19D8< 12D1> P0HT0_CLKIN-<1:0> P0HT0_CLKOUT-<1:0> 12D4<
IN OUT IN OUT
19B8> IN P0HT1_CTLIN+ A14 L1_CTLIN0+ L1_CTLOUT0+ B12 P0HT1_CTLOUT+
OUT 19D8< 12D1> IN P0HT0_CTLIN+ R1 L0_CTLIN0+ L0_CTLOUT0+ U2 P0HT0_CTLOUT+
OUT 12D4<
19B8> IN P0HT1_CTLIN- A13 L1_CTLIN0- L1_CTLOUT0- C12 P0HT1_CTLOUT-
OUT 19D8< 12D1> IN P0HT0_CTLIN- T1 L0_CTLIN0- L0_CTLOUT0- U3 P0HT0_CTLOUT-
OUT 12D4<
19B8> P0HT1_CADIN+<15:0> P0HT1_CADOUT+<15:0> 19D8< 12D1> P0HT0_CADIN+<15:0> P0HT0_CADOUT+<15:0> 12D4<
IN P0HT1_CADIN-<15:0>
15 E14 L1_CADIN15+ L1_CADOUT15+ D11 15
P0HT1_CADOUT-<15:0>
OUT IN P0HT0_CADIN-<15:0>
15 R5 L0_CADIN15+ L0_CADOUT15+ V4 15
P0HT0_CADOUT-<15:0>
OUT
19B8> IN 15 E13 C11 15 OUT 19D8< 12D1> IN 15 T5 V3 15 OUT 12D4<
L1_CADIN15- L1_CADOUT15- L0_CADIN15- L0_CADOUT15-