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Taken from DAS-8, DAS-8/PGA(G2), DAS-8/AO, & DAS-8/LT USER GUIDE Revision
F, April 1993
Chapter 3 PROGRAMMING Section 3.2 only
I/O Address Map of DAS-8/PGA(G2)/AO/LT
First let's look at the DAS-8/PGA(G2)/AO/LT I/O address map:
ADDRESS READ WRITE
Base Address + 0 A/D Lo byte Start 8 bit A/D conversion
+ 1 A/D Hi byte Start 12 bit A/D conversion
+ 2 STATUS register CONTROL register
+ 3* Status & Gain Gain Control Register
+ 4 Read Counter 0 Load Counter 0
+ 5 Read Counter 1 Load Counter 1
+ 6 Read Counter 2 Load Counter 2
+ 7 - Counter control
+ 8** Simul. Update DAC 0 Lo Byte
+ 9** Simul. Update DAC 0 Hi Byte
+10** Simul. Update DAC 1 Lo Byte
+11** Simul. Update DAC 1 Hi Byte
* DAS-8/PGA(G2) only.
**DAS-8/AO
Since the A/D provides 12 bits of data, it requires two bytes to handle each
word of data. Data is held as Low Byte first, then High Byte. This sequence is
a convenience for Assembly Language programmers, since the 8088 processor in the
IBM PC accesses data in this order. Now that we know register location, let's
examine the data format of each register and illustrate data transfer using
INP's and OUT's.
Initiating A/D Conversion
An A/D conversion is initiated by writing to Location BASE ADDRESS+0 or BASE
ADDRESS+1. If you write to BASE ADDRESS+1, a full 12-bit A/D conversion is
performed. Writing to BASE ADDRESS+0 initiates a short cycle (8-bit)
conversion. A 12-bit conversion takes no more than 35 microseconds (max) to
complete, while a short cycle 8-bit conversion takes less time (25 microseconds,
max). These times are dependent upon the type and manufacturer of AD574 ADC
used in your DAS-8/PGA(G2)/AO/LT and may be less, but will not exceed the
durations specified.
A/D conversion example code (BASICA):
12 bits xxx10 OUT BASADR% + 1, 0
8 bits xxx10 OUT BASADR%, 0
Data written to these locations is irrelevant and is lost; the decoded Address
Write Pulse is, in fact, what triggers the A/D.
A/D Data Format
At the end of a conversion cycle, data from the A/D may be read from Locations
BASE ADDRESS+0 and BASE ADDRESS+1. Data follows the usual Intel Low Byte/High
Byte sequence. BASE ADDRESS+1 contains the most significant 8 bits from the
conversion:
Bits D7 D6 D5 D4 D3 D2 D1 D0
Base Addr+1 B1 B2 B3 B4 B5 B6 B7 B8
(MSB)
The remaining four LSBs (followed by 4 zeroes) are read from BASE ADDRESS+0:
Bits D7 D6 D5 D4 D3 D2 D1 D0
Base Addr+0 B9 B10 B11 B12 0 0 0 0
(LSB)
A/D data bits B1-B12 correspond to an offset binary code, as follows:
BINARY HEX ANALOG INPUT VOLTAGE
0000 0000 0000 000 -5.0000 V (-Full scale)
0000 0000 0001 001 -4.9976 V
. . . . .
0100 0000 0000 400 -2.5000 V (-1/2 scale)
. . . . .
1000 0000 0000 800