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2. Reference Information
2-1 IC Dsecriptions
2-1-1 AIC1 (AK4324 ; Digital-to-Analog Converter)
DIF0 DIF1 DIF2 DEM0 DEM1 AVDD AVSS
LRCK De-emphasis
Serial Input Control
BICK Interface DZFL
SDATA
AOUTL+
PD 8X
SCF
Interpolator Modulator AOUTL-
SMUTE
AOUTR+
DFS
8X
Interpolator SCF
Modulator AOUTR-
Clock Divider
DZFR
MCLK CKS DVDD DVSS VREF
PIN I / O NAME FUNCTION PIN I / O NAME FUNCTION
1 - DVSS Digital ground pin 13 I DIF0 Digital input format pin
2 I DVDD Digital power supply 14 I DIF1 Digital input format pin
Master clock select pin (Internal pull-down pin)
3 I CKS Nomal speed "L":MCLK = 256fs, "H":MCLK = 384fs 15 I DIF2 Digital input format pin
Double speed "L":MCLK = 128fs, "H":MCLK = 192fs
4 I MCLK Master clock input pin 16 0 AOUTR- Rch negative analog output pin
Power-Down mode pin. When at "L", the AK4324 is in
5 I PD power-down and is held in rest. 17 O AOUTR+ Rch positive analog output pin
The AK4324 should always be reset upon power-pin
Audio serial data input pin
6 I BICK 18 O AOUTL- Lch negative analog output pin
64fs clock is recommended to be input on this pin
Audio serial data input pin
7 I SDATA 19 O AOUTL+ Lch positive analog output pin
2's complement MSB-first data is input on this pin.
8 I LRCK L/R clock pin. 20 - AVSS Analog ground pin
Soft mute pin
9 I SMUTE When this pin goes "H", soft mute cycle is initiated 21 O VREF Voltage reference input pin
When returning "L", the output mute releases.
Double speed sampling mode pin (Internal pull-down pin)
10 I DFS 22 O AVDD Analog power supply pin.
"L":normal speed, "H":double speed
11 I DEM0 De-emphasis frequency select pin 23 O DZFR Rch zero input detect pin
12 I DEM1 De-emphasis frequency select pin 24 O DZFL Lch zero input detect pin
Note : Allinput pins except internal pull-down pins should not be left floating.
Samsung Electronics 2-1
Reference Information
2-1-2 RIC1 (KS1461 ; RF)
AGCLEVEL
RFAGCO
MROFST
VZOCTL
EQGND
RFEQO
EQVCC
RFRPN
BCATH
PLLGF
AGCC
AGCP
AGCB
MIRRI
RDPF
RFRP
RFCT
AGCI
EQIN
EQG
CB 1
CB 2
CP 1
CP 2
EQF
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
to RF EQ
TUNING BLOCK
AGC-HOLD(OOH) AGC_DET
75 BCAO
ACD 1
MUX BCA
BCD 2 BLOCK
CCD 3 74 BCAI
A
DCD 4 B
RF RF SLM RF
C
MUX & AGC Equalizer
ADVD 5 D
RFRP BCA
BDVD 6
CDVD 7
GAIN_EQ(02H)
DDVD 8
73 RESET
AUTO
RFCT OFSTCTL
CD1 S12 DVD1.2
& 72 OSC
CDRSEL(00H) TE1RES MIRR
DELAY_SEL(OOH) HOLD_CTL(O8H) CD1
PLLCTL DPDMUTE S12
TBAL(O1H) DPD_MUTE(O2H) DVD1
SEOFHOLD DVD2
FLT_CTL(OOH) LDONB
DPDEQ1
RREFBF 9 CAL_ENDB(O2H) FLT_CTL 71 STB
VREF CDRSEL
RREFEQ 10 D DELAY PD,LPF TESEL S/IF
GENERATOR 70 CLOCK
GCA EQ COM AGC-HOLD BLOCK
RREF 11 TBAL
D TEOPST(04H) GAIN_TE3 69 DATA
MUX3 ENV_SEL
PDLIMITRES
D TE1_LIMIT DVCTL_SEL
GCA EQ COM DPD_MUTE
D GAIN_EQ
GAIN_FE 68 RREFDLY
GAIN_ABCD
DPDEQ2 TE_OFST
FE_OFST
FAULTOUT DPD
ABCD_OFST 67 VREFDPD
DELAY_CD
BLOCK
EQ
VREFEQ 12 DELAY_AB
VC AMP GAIN_TE3(02H) PDLIMIT
66 DPDGND
ga_RFSUM
E 13 DELAY_SEL(00H) HOLD_CTL
TE38 PLLCTL ga_PLLDP
ga_PLLDN 65 TE1RES
F 14 GCA
OFSTHOLD 64 PLLCTL
TEOFST(04H) 63 DPDMUTE
TBAL(01H) to DPD
BLOCK 62 FAUL TOUT
CDRSEL(OOH)
GAIN_ABCD(OOH) 61 DPDEQ2
ADVD1 15
60 DPDEQ1
BDVD1 16
D1
CDVD1 17 B1 ABCD
C1 SUM EQIN 59 TE30FST
DDVD1 18
SUB A1 ENV_SEL(02H)
58 BCA
ACD1 19 RF
BCD1 20 MUX GAIN_FE(03H) OFSTHOLD 57 MIRR
MUX
CCD1 21 FE ABCD_OFST(O6H)
FE_0FST(05H) 56 DPDVCC
DCD1 22
OFSTHOLD
55 DFCT2
AVCC 23 CDRSEL(00H) MUX
54 DFCT1
ANALOG LDONB(00H) TESEL(OOH)
VREFA 24 VC AMP 53 DFCTTH1
ENVELOPE FOK DEFECT
ALPC
52 DFCTTH2
FOFST 25
FOFST
51 DVCC
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
OFSTHOLD
VREFLP_BGI
LDODVD
PDVD
LDOCD
PDCD
AGND
FE
FEN
TEN
TE
PDLIMITRES
ABCDN
ABCD
ABCDI
ENVP
ENVB
ENV
DGND
FOKTH
FOKB
DFCT_CP1
DFCT_CP2
CC1
CC2
2-2 Samsung Electronics
PIN NAME I/O FUNCTION PIN NAME I/O FUNCTION PIN NAME I/O FUNCTION PIN NAME I/O FUNCTION
1 ACD I CD optical main beam A AC coupling input port for RF 34 FEN I FE Input port for AMP GAIN setting 65 TE1RES I DPD TE PLL variable bias resistance 96 RDPF - Bias resistance connection port for RF EQ frequency setting
2 BCD I CD optical main beam B AC coupling input port for RF 35 TEN I Input port for TE AMP GAIN setting 66 DPDGND P Power GND input port for DPD TE 97 EQG I RF EQ boost gain control voltage input port
Samsung Electronics
3 CCD I CD optical main beam C AC coupling input port for RF 36 TE O TE AMP output port 67 VREFDPD O CAP connection port for DPD TE center 98 EQF I RF EQ peak frequency control voltage input port
I RF EQ boost, peak frequency gain control port corre-
4 DCD CD optical main beam D AC coupling input port for RF 37 PDLIMTRES - Bias resistance port for PDLIMIT 68 RREFDLY - Bias resistance connection port for delta block
99 PLLGF I sponding to wideband PLL (PLLG. PLLF resistance
5 ADVD I DVD optical main beam A AC coupling input port for RF 38 ABCDN I Input port for ABCD AMP GAIN setting 69 DATA I Data input port internal design)
RF EQ control port (When No. PLLG isn't adjusted,
6 BDVD I DVD optical main beam B AC coupling input port for RF 100 VZOCTL I
39 ABCD O ABCD AMP output port 70 CLOCK I Clock input port apply DC CTL voltage.)
7 CDVD I DVD optical main beam C AC coupling input port for RF 40 ABCDI I ABCD AC coupling input port for SERVO monitor 71 STB I Data enable input port
8 DDVD I DVD optical main beam D AC coupling input port for RF Peak hold time constant setting RC 72 OSC OSC time constant input port for auto offset block
41 ENVP -
connection port for RF envelope detect
9 RREFBF - RF AMP I/O buffer bias resistance connection port 73 RESET I Reset input port for auto offset block (L : RESET)
Bottom hold time constant setting RC
42 ENVB -
10 RREFEQ - RF EQ bias resistance connection port connection port for RF envelope detect 74 BCAI I BCA FILTER1
43 ENV O RF envelope detect output port O
11 RREF - Analog block bias resistance connection port 75 BCAO BCA FILTER2
44 DGND P Power GND input port for digital circuit
12 VREFEQ O CAP connection port for RF EQ center voltage 76 RFCT O RF ripple center voltage output port for mirror
45 FOKTH I Focus OK comparing level input port Bottom hold time constant RC connection port for
13 E I CD optical sub beam E input port for SERVO 77 CB2 -
Focus OK comparator output port RFCT generation
14 F I CD optical sub beam F input port for SERVO 46 FOKB O Peak hold time constant RC connection port for
(L: FOCUS OK) 78 CP2 -
Peak hold time constant connection port SERVO RFCT generation
15 ADVD1 I DVD optical main beam A input port for SERVO 47 DFCT_CP1 -
defect max. time setting 79 RFRP O RF ripple AMP output port for mirror
16 BDVD1 I DVD optical main beam B input port for SERVO Peak hold time constant connection port PLL defect
48 DFCT_CP2 - 80 RFRPN I RF ripple AMP GAIN input port for mirror
I min. time setting
17 CDVD1 DVD optical main beam C input port for SERVO
49 CC1 O Output port of peak detector for defect 81 MROFST I RF ripple offset control port for mirror
18 DDVD1 I DVD optical main beam D input port for SERVO
Bottom hold time constant RC connection port for
50 CC2 I AC coupling input port for defect 82 CB1 -
19 ACD1 I CD optical main beam F input port for SERVO RFCT generation
51 DVCC P Power voltage input port for digital circuit Peak hold time constant RC connection port for
20 BCD1 I CD optical main beam F input port for SERVO 83 CP1 -
RFCT generation
Resistance connection port for PLL defect comparat-
21 CCD1 I CD optical main beam F input port for SERVO 52 DVCTTH2 -
ing level setting 84 MIRRI I Input port for MIRR signal generation
Resistance connection port for SERVO defect com-
22 DCD1 I CD optical main beam F input port for SERVO 53 DFCTTH1 - 85 EQVCC P Power voltage input port for RF EQ
parating level setting
23 AVCC P Power voltage input port for analog part 86 RFEQO O RF EQ output port
54 DFCT1 O Defect output port for SERVO
CAP connection port for analog part
24 VREFA -/O 55 DFCT2 O Defect output port for PLL 87 BCATH I BCA comparating level control port
center voltage, Use at other block
25 FOFST O CAP connection port for focus auto offset (OPEN) 56 DPDVCC P Power voltage input port for DPD TE 88 EQIN I RFAGCO input port for RF EQ
ON/OFF connection port for auto offset block (L : 57 MIRR O Mirror output port 89 RFAGCO O RF AGC AMP output port
26 OFSTHOLD I
auto offset adjustment H : serial offset adjustment)
58 BCA O BCA output port 90 AGCC - AGC time constant CAP connection port
27 VREFLP_BGI I BANDGAP voltage input port for ALPC
59 TE3OFST - Resistance connection port for 3BTE offset 91 AGCI I When AGC is "HOLD", AGC voltage input port
28 LDODVD O DVD optical laser diode driving voltage output port
60 DPDEQ1 O DPD EQ (A+C) output port 92 EQGND P Power GND input port for RF EQ
29 PDDVD I DVD optical laser monitor diode voltage input port
61 DPDEQ2 O DPD EQ (B+D) output port 93 AGCLEVEL I AGC level control voltage input port
30 LDOCD O CD optical laser diode driving voltage output port
62 FAULTOUT O DPD defect waveform output port (MONITOR) -
94 AGCB RF bottom hold time constant RC connection port for RF AGC
31 PDCD I CD optical laser monitor diode voltage input port
63 DPDMUTE I DPD TE MUTE control port (H : MUTE) 95 AGCP - RF peak hold time constant RC connection port for RF AGC
32 AGND P Power GND port for analog part
O 64 PLLCTL I DPD TE PLL variable input port
33 FE FE AMP output port
2-3
Reference Information
2-4
TILTI
TILTO
RSTB
TEST
XI
XO
XOUT
PHI1
TZCA
MIRR
FOKB
DFCT
LOCK
SMON
/PSO
SSTOP
PS1
DIRC
Reference Information
FLKB
VREF TIMING I/O INTERFACE TLKB
ENV GENERATOR BLOCK
LDONB
TZCO
A/D
2-1-3 SIC1 (KS1452 ; Digital Servo)
SME CONVERTER
SQCK
BLOCK SUB CODE
TE SQSI
READ BLOCK
FE SCOR
DAB
CSB
TRACK MWRB
COUT
COUNTER SYSCON MRDB
DSP CORE INTERFACE MDATA[7:0]
FOR BLOCK
FOD SENSE
DIGITAL SERVO
TRD PSB
SLD MDOUT[3:0]
D/A
SPD PLLLOCK
CONVERTER RFD
FBAL BLOCK RPD
TBAL
EFMRTD
DVCTL
PLCK
ROM WIDE RVCO
EFMI
CAPTURE VCTRL
RFI
EFM RANGE PLL EQCTL
ASYDVD ASYMETRY MAGICO
ASYCD FDCTL
EFM INTO_224
PLLHD
EFMOA
Samsung Electronics
PIN NAME I/O FUNCTION PIN NAME I/O FUNCTION PIN NAME I/O FUNCTION PIN NAME I/O FUNCTION
1 MDOUT3 O Mode data3 out controlled by micom 34 FOKB I Focus OK signal input pin 65 FE I Focus error signal input pin 73 SLD O Sled motor drive signal output pin
2 SSTOP/PSO I Limit switch/sled position sensor input pin0 35 FDCTL I PLL frequency detect control input pin 66 ENV I RF envelope input pin 74 SPD O Spindle motor drive signal output pin
Samsung Electronics
3 PS1 I Sled motor position sensor input pin 1 36 LDONB O Laser diode ON signal output pin 67 TILTI I Tilt in (reserved) 75 FOD O Focus actuator drive signal output pin
4 TEST I Test pin (L : normal H : test) 37 DFCT I Defect Detection signal input pin 68 AVDD P Analog block VDD power supply pin 76 TRD O Tracking actuator drive signal output pin
5 COUT O Counter clock 38 MIRR I Mirror signal input pin 69 TILTO O Tilt out (reserved) 77 TZCA I TE signal for tracking zero cross input pin
6 FLKB O Focus servo lock signal output pin 39 PLLHD I PLL hold signal from micom 70 DVCTL O Depth variation control signal output pin 78 MDOUT0 O Mode data 0 out controlled by micom
7 TLKB O Tracking servo lock signal output pin 40 INTO_224 O Servo interrupt monitor pin 71 TBAL O Tracking balance signal output pin 79 MDOUT1 O Mode data 1 out controlled by micom
8 PSB I 0 : 1BIT 1 : 8BIT 41 PVDD P PLL logic block VDD power supply pin 72 FBAL O Focus balance signal output pin 80 MDOUT2 O Mode data 2 out controlled by micom
9 RSTB I System reset signal input pin 42 PLCK O PLCK
10 CSB I Micom chip select pin Frequency lock detect output
43 PLLLOCK O
11 DAB I Micom data/address select pin (H : Lock L : Unlock)
12 MWRB I Micom write clock signal input pin 44 EFMRTD O Latched EFM output signal
13 MRDB I Micom read clock signal input pin 45 PVSS P PLL logic block VSS power supply pin
14 MDATA0 I/O Micom data pin 0 46 RVCO I Resistor pin for VCO GAIN
15 MDATA1 I/O Micom data pin 1 47 RFD I Gain adjust resister for frequence detector
16 MDATA2 I/O Micom data pin 2 48 RPD I Gain adjust resister for phase detector
17