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Compal Confidential
Model Name : JE50-HR/SJV50-HR
Compal Project Name : P5WE0/P5WS0
1 1

File Name : LA-6902P

Compal Confidential
2 2

JE50-HR/SJV50-HR(P5WE0/P5WS0) M/B Schematics Document
Intel Sandy Bridge Processor with DDRIII + Cougar Point PCH
Nvidia N12P GS/GV

3 2010-10-19 3

REV:0.1

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/10/15 Deciphered Date 2011/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JE50-HR/SJV50-HR M/B Schematics
Date: Wednesday, October 27, 2010 Sheet 1 of 61
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A B C D E

Fan Control
page 42

1 1

100MHz PCI-E 2.0x16 5GT/s PER LANE
PEG(DIS) Intel Memory BUS(DDRIII)
Nvidia 133MHz Dual Channel 204pin DDRIII-SO-DIMM X2
N12P GS/GV Sandy Bridge BANK 0, 1, 2, 3 page 11,12
1.5V DDRIII 1066/1333
Processor
page22~30

rPGA989
page 4~10

HDMI(DIS) CRT(DIS) LVDS(DIS) FDI x8 DMI x4 USB 2.0 conn x2 Bluetooth CMOS Camera 3G connector
Conn USB port 9,12 on 3G/B
USB port 0,1 on USB port 13 USB port 10
HDMI Conn. CRT Conn. LVDS Conn. 100MHz 100MHz USB/B page 38 page 38 page 31 page 37
page 33 page 32 page 31 2.7GT/s 1GB/s x4
2 USBx14 3.3V 48MHz 2
LVDS(UMA/OPTIMUS)
Intel
CRT(UMA/OPTIMUS) HD Audio 3.3V 24MHz

TMDS(UMA/OPTIMUS) Cougar Point-M
PCH
PCI-Express x 8 (ARD PCIE2.0 2.5GT/s) 100MHz HDA Codec
SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S) 100MHz 989pin BGA ALC271X/277X
port 2,3 port 1 page 41
port 5 page 13~21 SPI
USB 3.0 conn x1 MINI Card x2 LAN(GbE) &
NEC uPD720200AF1 WLAN, WWAN Card Reader
USB port 12,13
BCM57785
with USB3.0 Conn. page 37 page 35,36 SPI ROM x1 Int. Speaker Phone Jack x 2
page 45
port 0,1 port 2 page 13
page 41 page 41
SATA HDD SATA CDROM
3
Card Reader RJ45 Conn. page Conn. page 34 LPC BUS 3
34
Conn. page 35,36 page 36
33MHz

Sub-board ENE KB930
page 39
LS-6901P
USB 2.0/B 2Port
RTC CKT. USB Port0,1 page 38
page 13 LF-6901P Touch Pad Int.KBD
FPC for USB3.0 page 40 page 40
LS-6904P page 38
Power On/Off CKT. USB 3.0 /B
page 40 1 port as USB3.0
1 port as USB2.0
page 38
BIOS ROM
page 40
DC/DC Interface CKT.
LS-6903P
4 page 43,44 4
3G/B
page 37

Power Circuit DC/DC
page 46~59 LS-6902P + LS-6905P Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/10/15 Deciphered Date 2011/10/15 Title
PWR/B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
Size Document Number Rev
page 40 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JE50-HR/SJV50-HR M/B Schematics 0.4
Date: Wednesday, October 27, 2010 Sheet 2 of 61
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A B C D E

Voltage Rails
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Power Plane Description S1 S3 S5
VIN Adapter power supply (19V) N/A N/A N/A Full ON HIGH HIGH HIGH HIGH ON ON ON ON
BATT+ Battery power supply (12.6V) N/A N/A N/A
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
B+ AC or battery power rail for power circuit. N/A N/A N/A
1 1
+CPU_CORE Core voltage for CPU ON OFF OFF S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
+VGA_CORE Core voltage for GPU ON OFF OFF
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+VGFX_CORE Core voltage for UMA graphic ON OFF OFF
+0.75VS +0.75VP to +0.75VS switched power rail for DDR terminator ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.05VSDGPU +1.0VSPDGPU to +1.0VSDGPU switched power rail for GPU ON OFF OFF
+1.05VS_VTT +1.05VS_VCCPP to +1.05VS_VCCP switched power rail for CPU ON OFF OFF
+1.05VS_PCH +1.05VS_VCCP to +1.05VS_PCH power for PCH ON OFF OFF Board ID / SKU ID Table for AD channel
+1.5V +1.5VP to +1.5V power rail for DDRIII ON ON OFF Vcc 3.3V +/- 5%
+1.5VS +1.5V to +1.5VS switched power rail ON OFF OFF Ra/Rc/Re 100K +/- 5%
+1.5VSDGPU +1.5VS to +1.5VSDGPU switched power rail for GPU ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+1.8VS (+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU ON OFF OFF 0 0 0 V 0 V 0 V EVT
+1.8VSDGPU +1.8VS to +1.8VSDGPU switched power rail for GPU ON OFF OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V EVT2
+3VALW +3VALW always on power rail ON ON ON* 2 18K +/- 5% 0.436 V 0.503 V 0.538 V DVT
+3VALW_EC +3VALW always to KBC ON ON ON* 3 33K +/- 5% 0.712 V 0.819 V 0.875 V PVT
+3V_LAN +3VALW to +3V_LAN power rail for LAN ON ON ON* 4 56K +/- 5% 1.036 V 1.185 V 1.264 V Pre-MP
+3VALW_PCH +3VALW to +3VALW_PCH power rail for PCH (Short Jumper) ON ON ON* 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
2 2
+3VS +3VALW to +3VS power rail ON OFF OFF 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+5VALW +5VALWP to +5VALW power rail ON ON ON* 7 NC 2.500 V 3.300 V 3.300 V
+5VALW_PCH +5VALW to +5VALW_PCH power rail for PCH (Short resister) ON ON ON*
+5VS +5VALW to +5VS switched power rail ON OFF OFF
BOARD ID Table BTO Option Table
+VSB +VSBP to +VSB always on power rail for sequence control ON ON ON*
+RTCVCC RTC power ON ON ON
BTO Item BOM Structure
Board ID PCB Revision
UMA Only UMAO@
0 0.1
UMA with OPTIMUS UMA@
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. 1 0.2
Dis with OPTIMUS DIS@
EC SM Bus1 address EC SM Bus2 address 2 0.3
DIS Only DISO@
3 0.4
Device
OPTIMUS OPT@
Address Device Address 4 1.0
Non-OPTIMUS NOPT@
Smart Battery 0001 011X b 5
3G 3G@
6
Blue Tooth BT@
7
USB2.0 USB20@
PCH SM Bus address USB3.0 USB30@
3 VRAM X76@ 3
Device Address
USB Port Table Connector CONN@
Clock Generator (9LVS3199AKLFT, 1101 0010b Unpop @
RTM890N-631-VB-GRT) 3 External
DDR DIMM0 1001 000Xb
USB 2.0 USB 1.1 Port USB Port LAN Chip A0 version A0@
DDR DIMM2 LAN Chip B0 version B0@
1001 010Xb 0 USB/B (Right Side)
UHCI0 N12P-GS GS@
1 USB/B (Right Side)
3G & BT & USB30 & USB20 Config N12P-GV GV@
2 USB3.0 colay USB2.0 Conn.
3G SKU: 3G@ USB30 SKU: USB30@ OPTMIUS SKU: OPT@ UHCI1
3 USB/B Colay USB3.0
BT SKU: BT@ USB20 SKU: USB20@ Non-OPTMIUS SKU: NOPT@ EHCI1
4
LAN Chip A0 version: A0@ N12P-GS: GS@ UHCI2
5
LAN chip B0 Version: B0@ N12P-GV: GV@
6
BOM Config UHCI3
7
UMA Only: BT@/3G@/USB30@/UMA@/UMAO@/NOPT@/A0@
8 Mini Card 1(WLAN)
OPTIMUS(N12P-GS): BT@/3G@/USB30@/UMA@/DIS@/X76@/OPT@/A0@/GS@ UHCI4
9 3G/B(WWAN)
DIS Only(N12P-GS): BT@/3G@/USB30@/DISO@/DIS@/X76@/NOPT@/A0@/GS@
10 Camera
OPTIMUS(N12P-GV): BT@/3G@/USB30@/UMA@/DIS@/X76@/OPT@/A0@/GV@ EHCI2 UHCI5
11 Mini Card 2(Reserved)
4 DIS Only(N12P-GV): BT@/3G@/USB30@/DISO@/DIS@/X76@/NOPT@/A0@/GV@ 4
12 3G/B(SIM Card)
VRAM P/N : UHCI6
64*16 13 BlueTooth
Samsung : SA000035700
Hynix : SA000032400/SA0000324C0
128*16 Security Classification Compal Secret Data Compal Electronics, Inc.
Samsung : SA00003MQ40 Issued Date 2010/10/15 Deciphered Date 2011/10/15 Title
Hynix : SA00003VS00
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JE50-HR/SJV50-HR M/B Schematics 0.4
Date: Wednesday, October 27, 2010 Sheet 3 of 61
A B C D E
5 4 3 2 1

+1.05VS_VTT
PEG_ICOMPI and PEG_RCOMPO signals should be
ZZZ shorted and routed,

1
DA60000KC00 max length = 500 mils,trace width=4mils
R517
24.9_0402_1% PEG_ICOMPO signals should be routed with - max
JCPU1A
length = 500 mils,trace width=12mils

2
D J22
PEG_COMP spacing =15mils D
PEG_ICOMPI
PEG_ICOMPO J21
15 DMI_CRX_PTX_N0 B27 DMI_RX#[0] H22
PEG_RCOMPO
15 DMI_CRX_PTX_N1 B25 DMI_RX#[1]
15 DMI_CRX_PTX_N2 A25 DMI_RX#[2] PEG_GTX_C_HRX_N15 C46 1 PEG_GTX_HRX_N15
15 DMI_CRX_PTX_N3 B24 DMI_RX#[3] K33 2 DIS@ 0.22U_0402_10V6K
PEG_RX#[0] PEG_GTX_C_HRX_N14 C49 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N14
PEG_RX#[1] M35
PEG_GTX_C_HRX_N13
15 DMI_CRX_PTX_P0 B28 L34 C51 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N13
DMI_RX[0] PEG_RX#[2] PEG_GTX_C_HRX_N12 C53 1 PEG_GTX_HRX_N12
15 DMI_CRX_PTX_P1 B26 J35 2 DIS@ 0.22U_0402_10V6K
DMI_RX[1] PEG_RX#[3] PEG_GTX_C_HRX_N11
2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N11

DMI
15 DMI_CRX_PTX_P2 A24 J32 C60 1 PEG_GTX_HRX_N[0..15] 22
DMI_RX[2] PEG_RX#[4] PEG_GTX_C_HRX_N10 C71 1 PEG_GTX_HRX_N10
15 DMI_CRX_PTX_P3 B23 H34 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P[0..15] 22
DMI_RX[3] PEG_RX#[5] PEG_GTX_C_HRX_N9 C75 1 PEG_GTX_HRX_N9
H31 2 DIS@ 0.22U_0402_10V6K
PEG_RX#[6] PEG_GTX_C_HRX_N8 C82 1 PEG_GTX_HRX_N8
15 DMI_CTX_PRX_N0 G21 G33 2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N[0..15] 22
PEG_GTX_C_HRX_N7
15 DMI_CTX_PRX_N1 E22
DMI_TX#[0] PEG_RX#[7]
G30 C92 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N7 PEG_HTX_C_GRX_P[0..15] 22
DMI_TX#[1] PEG_RX#[8] PEG_GTX_C_HRX_N6 C93 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N6
15 DMI_CTX_PRX_N2 F21 F35
PEG_GTX_C_HRX_N5 PEG_GTX_HRX_N5
DMI_TX#[2] PEG_RX#[9] C102 1
15 DMI_CTX_PRX_N3 D21 E34
PEG_GTX_C_HRX_N4 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N4
DMI_TX#[3] PEG_RX#[10] C111 1
E32
PEG_GTX_C_HRX_N3 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N3
15 DMI_CTX_PRX_P0 PEG_RX#[11] C113 1 2 DIS@ 0.22U_0402_10V6K
G22 DMI_TX[0] D33
PEG_GTX_C_HRX_N2 PEG_GTX_HRX_N2
15 DMI_CTX_PRX_P1 PEG_RX#[12]
D22 D31
PEG_GTX_C_HRX_N1 C125 1 2 DIS@ 0.22U_0402_10V6KPEG_GTX_HRX_N1
DMI_TX[1] PEG_RX#[13] C129 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N0

PCI EXPRESS* - GRAPHICS
15 DMI_CTX_PRX_P2 F20 B33
PEG_GTX_C_HRX_N0
15 DMI_CTX_PRX_P3
DMI_TX[2] PEG_RX#[14] C144 1 2 DIS@ 0.22U_0402_10V6K
C21 DMI_TX[3] C32
PEG_RX#[15]
PEG_GTX_C_HRX_P15 C47 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P15
PEG_RX[0] J33
PEG_GTX_C_HRX_P14 PEG_GTX_HRX_P14
L35 C50 1 2 DIS@ 0.22U_0402_10V6K
PEG_RX[1] PEG_GTX_C_HRX_P13 C52 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P13
PEG_RX[2] K34
PEG_GTX_C_HRX_P12 C56 PEG_GTX_HRX_P12
15 FDI_CTX_PRX_N0 A21 H35 1 2 DIS@ 0.22U_0402_10V6K
FDI0_TX#[0] PEG_GTX_C_HRX_P11 C66 PEG_GTX_HRX_P11
15 FDI_CTX_PRX_N1 H19
PEG_RX[3]
H32 1 2 DIS@ 0.22U_0402_10V6K
FDI0_TX#[1] PEG_RX[4] PEG_GTX_C_HRX_P10 PEG_GTX_HRX_P10
15 FDI_CTX_PRX_N2 E19 G34
PEG_GTX_C_HRX_P9 C68 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P9
FDI0_TX#[2] PEG_RX[5] C81 1
15 FDI_CTX_PRX_N3 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P8

Intel(R) FDI
C F18 FDI0_TX#[3] G31
PEG_GTX_C_HRX_P8 C
15 FDI_CTX_PRX_N4 PEG_RX[6] C86 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P7
B21 FDI1_TX#[0] F33
PEG_GTX_C_HRX_P7
15 FDI_CTX_PRX_N5 PEG_RX[7] C89 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P6
C20 F30
PEG_GTX_C_HRX_P6 C100 1
15 FDI_CTX_PRX_N6 FDI1_TX#[1] PEG_RX[8] 2 DIS@ 0.22U_0402_10V6K
D18 FDI1_TX#[2] PEG_GTX_C_HRX_P5
E35 PEG_GTX_HRX_P5
15 FDI_CTX_PRX_N7 PEG_RX[9] C105 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P4
E17 PEG_GTX_C_HRX_P4
E33 C106 1
FDI1_TX#[3] PEG_RX[10] 2 DIS@ 0.22U_0402_10V6K
PEG_GTX_C_HRX_P3
F32 PEG_GTX_HRX_P3
PEG_RX[11] PEG_GTX_C_HRX_P2 C117 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P2
PEG_RX[12] D34
15 FDI_CTX_PRX_P0 A22 PEG_GTX_C_HRX_P1
E31 C119 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P1
15 FDI_CTX_PRX_P1 FDI0_TX[0] PEG_RX[13] C135 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P0
G19 PEG_GTX_C_HRX_P0
C33
15 FDI_CTX_PRX_P2 FDI0_TX[1] PEG_RX[14] C138 1 2 DIS@ 0.22U_0402_10V6K
E20 FDI0_TX[2] B32
15 FDI_CTX_PRX_P3 PEG_RX[15]
G18 FDI0_TX[3] PEG_HTX_GRX_N15 PEG_HTX_C_GRX_N15
15 FDI_CTX_PRX_P4 B20 PEG_HTX_GRX_N14 C516 1 2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N14
FDI1_TX[0] PEG_TX#[0] M29 C520 1 2 DIS@ 0.22U_0402_10V6K
15 FDI_CTX_PRX_P5 C19 PEG_HTX_GRX_N13 PEG_HTX_C_GRX_N13
FDI1_TX[1] M32 C529 1
15 FDI_CTX_PRX_P6 D19
PEG_TX#[1]
M31PEG_HTX_GRX_N12 2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N12
15 FDI_CTX_PRX_P7 FDI1_TX[2] PEG_TX#[2]
F17 PEG_HTX_GRX_N11 PEG_HTX_C_GRX_N11
+1.05VS_VTT
FDI1_TX[3] PEG_TX#[3] L32
PEG_HTX_GRX_N10 C538 1 1 2 2 DIS@ 0.22U_0402_10V6K
C534 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N10
15 FDI_FSYNC0 PEG_TX#[4] L29
J18 K31PEG_HTX_GRX_N9 C540 1 2 DIS@ 0.22U_0402_10V6KPEG_HTX_C_GRX_N9
15 FDI_FSYNC1