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5 4 3 2 1
Hummingbird1_HR
DIS/UMA/Muxless Schematics Document
D
Sandy Bridge D
Intel PCH
C C
DY :None Installed ANNIE: ONLY FOR ANNIE solution.
PSL: KBC795 PSL circuit for 10mW solution installed.
DIS:DIS installed 10mW: External circuit for 10mW solution installed.
DIS_Muxless :BOTH DIS or Muxless installed 65W: for 65W adaptor installed.
DIS_PX:BOTH DIS or PX installed 90W: for 90W adaptor installed.
DIS_PX_Muxless:DIS or PX or Muxless installed.
Muxless: Muxless installed.(PX4.0)
PX:MUX installed.(PX3.0)
B PX_Muxless:BOTH PX or Muxless installed. B
UMA:UMA installed
UMA_Muxless:BOTH UMA or Muxless installed
UMA_PX_Muxless:UMA or PX or Muxless installed
A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Cover Page
Size Document Number Rev
A3
Hummingbird1_HR -2
Date: Tuesday, April 17, 2012 Sheet 1 of 102
5 4 3 2 1
5 4 3 2 1
SYSTEM DC/DC CPU DC/DC
APL5916KAI 48 NCP6131S52MNR 42~43
Project code : 91.4QP01.001 INPUTS OUTPUTS INPUTS OUTPUTS
PCB P/N : 1D05V_PWR 0D85V_S0 DCBATOUT VCC_CORE
Revision : 2 Hummingbird1_HR Block Diagram SYSTEM DC/DC
UP6128PQDD 45
D
INPUTS OUTPUTS D
DCBATOUT 1D05V_VTT
RAM x 8 RAM x 8
SYSTEM DC/DC
UP6183PQAG 41
Intel CPU
RAM x 8 RAM x 8 INPUTS OUTPUTS
DDRIII 1066/1333 Channel A 5V_AUX_S5
3D3V_AUX_S5
DCBATOUT 5V_S5
Sandy Bridge 3D3V_S5
RAM x 8 RAM x 8
FSB: 1066 MHz
SYSTEM DC/DC
RAM x 8 RAM x 8 UP6165BQKF 46
INPUTS OUTPUTS
1D5V_S3
4,5,6,7,8,9,10,11,12,13 DCBATOUT 0D75V_S0
DDR_VREF_S3
SYSTEM DC/DC
NCP5911MNTBG 44
C
FDIx4x2 C
DMIx4 INPUTS OUTPUTS
DCBATOUT VCC_GFXCORE_PWR
HDMI VGA
HDMI 92
51 Intel PCI-E x1 RT8208BGQW
USB x1 Mini-Card
FPC 802.11a/b/g
INPUTS OUTPUTS
LVDS(Single Channel)
LCD PCH MINI Board
DCBATOUT VGA_CORE
49
Cougar Point SATA x1 M-SATA TI CHARGER
FFC BQ24745RHDR 40
14 USB 2.0/1.1 ports INPUTS OUTPUTS
ETHERNET (10/100/1000Mb) Charger signal Charger Circuit
DCBATOUT BT+
High Definition Audio 26
SATA ports (6) SYSTEM DC/DC
RT9025 47
PCIE ports (8)
Left Side: INPUTS OUTPUTS
USB x 2 LPC I/F
B ACPI 1.1 3D3V_S0 1D8V_S0 B
USB2.0 x 3
Card Reader CardReader SYSTEM DC/DC
FFC USB 2.0 x 1 RT9025-25PSP 93
RTS5129
SD/MMC
Board
17,18,19,20,21,22,23,24,25,26 INPUTS
26 OUTPUTS
1D5V_S3 1V_VGA_S0
CAMERA 49
3D3V_S5 1D8V_VGA_S0
AZALIA
Switches
SPI
SATA x1 HDD INPUTS OUTPUTS
LPC Bus
56 1D5V_S3 1D5V_VGA_S0
3D3V_S0 3D3V_VGA_S0
Internal Digital MIC Azalia Flash ROM LPC debug port
CODEC 4MB 60 71
PCB LAYER
HP1
ALC271X-VB3 KBC L1:Top L4:Signal
SMBus L2:VCC L5:GND
29 L3:Signal L6:Bottom
A
NUVOTON HR PX A
NPCE795P 27
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2CH SPEAKER Title
Thermal
Touch Int. ENE P2800 Block Diagram
Fan Size Document Number Rev
PAD KB 28 A3
69 69 2528 Hummingbird1_HR -2
Date: Tuesday, April 17, 2012 Sheet 2 of 102
5 4 3 2 1
A B C D E
PCH Strapping Huron River Schematic Checklist Rev.0_7 Processor Strapping Huron River Schematic Checklist Rev.0_7
Name Schematics Notes Pin Name Strap Description Configuration (Default value for each bit is Default
SPKR Reboot option at power-up 1 unless specified otherwise) Value
Default Mode: Internal weak Pull-down.
No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-k CFG[2] PCI-Express Static 1: Normal Operation.
- 10-k weak pull-up resistor. Lane Numbers Reversed 15 -> 0, 14 -> 1, ... 1
Lane Reversal 0:
INIT3_3V# Weak internal pull-up. Leave as "No Connect".
Disabled - No Physical Display Port attached to
GNT3#/GPIO55 GNT[3:0]# functionality is not available on Mobile. CFG[4] 1: Embedded DisplayPort.
4 GNT2#/GPIO53 Mobile: Used as GPIO only
Enabled - An external Display Port device is
0 4
GNT1#/GPIO51 Pull-up resistors are not required on these signals. 0: connectd to the EMBEDDED display Port
If pull-ups are used, they should be tied to the Vcc3_3power rail.
CFG[6:5] PCI-Express 11 : x16 - Device 1 functions 1 and 2 disabled
Enable Danbury: Connect to Vcc3_3 with 8.2-k? weak pull-up resistor. Port Bifurcation 10 : x8, x8 - Device 1 function 1 enabled ;
SPI_MOSI function 2 disabled
Straps 11
Left floating, no pull-down required.
Disable Danbury: 01 : Reserved - (Device 1 function 1 disabled ;
function 2 enabled)
00 : x8, x4, x4 - Device 1 functions 1 and 2
Enable Danbury: Connect to +NVRAM_VCCQ with 8.2-kohm enabled
weak pull-up resistor [CRB has it pulled up
NV_ALE with 1-kohm no-stuff resistor] CFG[7] PEG DEFER TRAINING 1: PEG Train immediately following xxRESETB de assertion
1
Leave floating (internal pull-down) 0: PEG Wait for BIOS for training
Disable Danbury:
NC_CLE DMI termination voltage. Weak internal pull-up. Do not pull low.
Low (0) - Flash Descriptor Security will be overridden. Also,
when this signals is sampled on the rising edge of PWROK
then it will also disable Intel ME and its features. Voltage Rails
HAD_DOCK_EN# High (1) - Security measure defined in the Flash Descriptor will be enabled. POWER PLANE VOLTAGE DESCRIPTION
Platform design should provide appropriate pull-up or pull-down depending on ACTIVE IN
/GPIO[33]
3 the desired settings. If a jumper option is used to tie this signal to GND as 5V_S0
3D3V_S0
5V
3.3V 3
required by the functional strap, the signal should be pulled low through a weak 1D8V_S0 1.8V
pull-down in order to avoid asserting HDA_DOCK_EN# inadvertently. 1D5V_S0 1.5V
1D05V_VTT 1.05V
Note: CRB recommends 1-kohm pull-down for FD Override. There is an internal 0D85V_S0 0.95 - 0.85V
pull-up of 20 kohm for DA_DOCK_EN# which is only enabled at boot/reset for 0D75V_S0 0.75V
strapping functions. VCC_CORE 0.35V to 1.5V
VCC_GFXCORE 0.4 to 1.25V S0
1D8V_VGA_S0 1.8V
3D3V_VGA_S0 3.3V CPU Core Rail
HDA_SDO Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#. 1V_VGA_S0 1V Graphics Core Rail
HDA_SYNC Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.
Low (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no 5V_USBX_S3 5V
GPIO15 1D5V_S3 1.5V S3
confidentiality High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher DDR_VREF_S3 0.75V
suite with confidentiality
Note : This is an un-muxed signal.
BT+ 6V-14.1V AC Brick Mode only
This signal has a weak internal pull-down of 20 kohm which is enabled when PWROK is low. DCBATOUT 6V-14.1V
Sampled at rising edge of RSMRST#. 5V_S5 5V All S states
CRB has a 1-kohm pull-up on this signal to +3.3VA rail. 5V_AUX_S5 5V
3D3V_S5 3.3V
3D3V_AUX_S5 3.3V
GPIO8 on PCH is the Integrated Clock Enable strap and is required to be pulled-down
GPIO8 using a 1k +/- 5% resistor. When this signal is sampled high at the rising edge of 3D3V_LAN_S5 3.3V WOL_EN Legacy WOL
RSMRST#, Integrated Clocking is enabled, When sampled low, Buffer Through Mode is
enabled.
2 Default = Do not connect (floating) 3D3V_AUX_KBC 3.3V DSW, Sx ON for supporting Deep Sleep states 2
High(1) = Enables the internal VccVRM to have a clean supply for
GPIO27 analog rails. No need to use on-board filter circuit.
Low (0) = Disables the VccVRM. Need to use on-board filter Powered by Li Coin Cell in G3
circuits for analog rails. 3D3V_AUX_S5 3.3V G3, Sx and +V3ALW in Sx
USB Table
Pair Device
SMBus ADDRESSES
PCIE Routing 0 Touch Panel / 3G SIM
1 USB Ext. port 1 (HS) I 2 C / SMBus Addresses
HURON RIVER ORB
2 Fingerprint Device Ref Des Address Hex Bus
LANE1 Mini Card2(WWAN)
3 BLUETOOTH EC SMBus 1 BAT_SCL/BAT_SDA
LANE2 Mini Card1(WLAN) SATA Table 4 Mini Card2 (WWAN) Battery BAT_SCL/BAT_SDA
CHARGER BAT_SCL/BAT_SDA
LANE3 Card Reader 5 CARD READER
SATA EC SMBus 2
6 X SML1_CLK/SML1_DATA
PCH SML1_CLK/SML1_DATA
LANE4 Onboard LAN Pair Device eDP
7 X SML1_CLK/SML1_DATA
1
1
0 HDD1 8 USB Ext. port 4 / E-SATA /USB CHARGER
LANE5 USB3.0
1 HDD2 9 USB Ext. port 2 PCH SMBus
PCH_SMBDATA/PCH_SMBCLK
Wistron Corporation
SO-DIMMA (SPD) 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
LANE6 Intel GBE LAN 2 N/A 10 EDP CAMERA SO-DIMMB (SPD) PCH_SMBDATA/PCH_SMBCLK Taipei Hsien 221, Taiwan, R.O.C.
Digital Pot PCH_SMBDATA/PCH_SMBCLK
G-Sensor PCH_SMBDATA/PCH_SMBCLK Title
LANE7 Dock 3 N/A 11 Mini Card1 (WLAN) MINI PCH_SMBDATA/PCH_SMBCLK
4 ODD 12 CAMERA PCH_SMBDATA/PCH_SMBCLK Table of Content
Size Document Number Rev
LANE8 New Card 5 ESATA 13 New Card A3
-2
Hummingbird1_HR
Tuesday, April 17, 2012
Date: Sheet 3 of 102
5 4 3 2 1
SSID = CPU
Signal Routing Guideline:
PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils.
PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.
1D05V_VTT
CPU1A 1 OF 9
G3 PEG_IRCOMP_R R401 1 2 24D9R2F-L-GP
PEG_ICOMPI
19 DMI_TXN[3:0] PEG_ICOMPO G1
D Note: DMI_TXN0
DMI_TXN1
M2
P6
DMI_RX#0 PEG_RCOMPO G4 D
Intel DMI supports both Lane DMI_RX#1
DMI_TXN2 P1
Reversal and polarity inversion DMI_TXN3 P10
DMI_RX#2
H22
but only at PCH side. This is DMI_RX#3 PEG_RX#0
19 DMI_TXP[3:0] PEG_RX#1 J21
enabled via a soft strap. DMI_TXP0 N3 B22
DMI_RX0 PEG_RX#2
DMI
DMI
DMI_TXP1 P7 D21
DMI_TXP2 DMI_RX1 PEG_RX#3
P3 A19
SANDYBRIDGE
DMI_TXP3 DMI_RX2 PEG_RX#4
P11 DMI_RX3 PEG_RX#5 D17
19 DMI_RXN[3:0] PEG_RX#6 B14
DMI_RXN0 K1 D13
DMI_RXN1 DMI_TX#0 PEG_RX#7
M8 DMI_TX#1 PEG_RX#8 A11
DMI_RXN2 N4 B10
DMI_RXN3 DMI_TX#2 PEG_RX#9
R2 DMI_TX#3 PEG_RX#10 G8
19 DMI_RXP[3:0] PEG_RX#11 A8
DMI_RXP0 K3 B6
DMI_RXP1 DMI_TX0 PEG_RX#12
M7 DMI_TX1 PEG_RX#13 H8
DMI_RXP2 P4 E5
DMI_RXP3 DMI_TX2 PEG_RX#14
T3 DMI_TX3 PEG_RX#15 K7
PEG_RX0 K22
PEG_RX1 K19
19 FDI_TXN[7:0] PEG_RX2 C21
FDI_TXN0 U7 D19
FDI_TXN1 FDI0_TX#0 PEG_RX3
W11 FDI0_TX#1 PEG_RX4 C19
Note: FDI_TXN2 W1 D16
FDI_TXN3 FDI0_TX#2 PEG_RX5
Intel FDI supports both Lane AA6 FDI0_TX#3 PEG_RX6 C13
FDI_TXN4 W6 D12
Reversal and polarity inversion FDI_TXN5 FDI1_TX#0 PEG_RX7
PCI EXPRESS -- GRAPHICS
V4 FDI1_TX#1 PEG_RX8 C11
but only at PCH side. This is
C FDI_TXN6 Y2 FDI1_TX#2 PEG_RX9 C9 C
Intel(R) FDI
Intel(R) FDI
enabled via a soft strap. FDI_TXN7 AC9 F8
FDI1_TX#3 PEG_RX10
PEG_RX11 C8
19 FDI_TXP[7:0] PEG_RX12 C5
FDI_TXP0 U6 H6
FDI_TXP1 FDI0_TX0 PEG_RX13
W10 FDI0_TX1 PEG_RX14 F6
FDI_TXP2 W3 K6
FDI_TXP3 FDI0_TX2 PEG_RX15
AA7 FDI0_TX3
FDI_TXP4 W7 G22
FDI_TXP5 FDI1_TX0 PEG_TX#0
T4 FDI1_TX1 PEG_TX#1 C23
FDI_TXP6 AA3 D23
FDI_TXP7 FDI1_TX2 PEG_TX#2
AC8 FDI1_TX3 PEG_TX#3 F21
PEG_TX#4 H19
19 FDI_FSYNC0 AA11 FDI0_FSYNC PEG_TX#5 C17
Note: 19 FDI_FSYNC1 AC12 FDI1_FSYNC PEG_TX#6 K15
Lane reversal does not apply to PEG_TX#7 F17
19 FDI_INT U11 F14
FDI sideband signals. FDI_INT PEG_TX#8
A15
PEG_TX#9
19 FDI_LSYNC0 AA10 FDI0_LSYNC PEG_TX#10 J14
19 FDI_LSYNC1 AG8 FDI1_LSYNC PEG_TX#11 H13
PEG_TX#12 M10
PEG_TX#13 F10
PEG_TX#14 D9
PEG_TX#15 J4
1D05V_VTT R402 1 2 24D9R2F-L-GP DP_COMP AF3 EDP_COMPIO
AD2 EDP_ICOMPO PEG_TX0 F22
1 2 10KR2J-3-GP eDP_HPD AG11 EDP_HPD PEG_TX1 A23
R403 D24
PEG_TX2
PEG_TX3 E21
AG4 G19
B AF4
EDP_AUX#
EDP_AUX
PEG_TX4
PEG_TX5 B18 B
Signal Routing Guideline: PEG_TX6 K17
DP
DP
EDP_ICOMPO keep W/S=12/15 mils and routing