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5 4 3 2 1
Calpella Switchable Graphic BLOCK DIAGRAM GPU CORE PWR
MAX8792ETD P44
CHARGER
ISL88731 P38
3/5V SYS PWR DISCHARGER
+3V,+ 5V,+1.5V,+1.05V,+1.1V_VTT
RT8206 P39 P47
D DDR3 PWR CPU CORE PWR D
VT358 P43 ISL62882 P42
CLOCK GENERATOR
SELGO: SLG8SP595V
BCLK: 133MHz
PEG_CLK: 100MHz
DPLL_REF_SSCLK: 120MHz
intel Fan Driver
+1.8V (Linear)
CPU VTT
ARD: 1.05V
CFD: 1.1V
X'TAL
P3
HPA00835RTER P46 VT358 P41
14.318MHz (PWM Type)
P37
DDR SYSTEM MEMORY
CPU VGFX_AXG VTT 1.05V
ISL62881 P45 VT357 P42
Dual Channel Arrandale (SG)
DDR III
800/ 1066 MHz
SO-DIMM 0 THERMAL
SO-DIMM 1 800 MT/s 1066 MT/s PROTECTION P47
P14, 15 rPGA37.5mm)
(37.5mm X
989
PCI-E PCIE
X16 Nvidia GPU MB CRT P23
P4.5.6.7
FDI DMI 2.5GT/s N11M 512MB CRT
N11P 1GB
LVDS Dock P27
Note: HDMI LVDS/CRT
C
HM55 does not support USB 6 & 7 * [Arrandale Only]
X4 DMI interface P16,17,18,19,20,21,22
Switch LVDS
C
HM55 does not support SATA 2 & 3
X'TAL P23
27.0MHz
Graphics Interfaces
FDI DMI P23
INT_CRT * [Arrandale Only]
HDD (SATA) *1
intel INT_LVDS *[Arrandale Only]
Card Reader Docking DVI P33
Connector
P32 SATA0
AU6437 INT_HDMI
USB_P12 P25
SATA *[Arrandale Only] DVI L/S (UMA only)
3.0 GT/s SN75DP139
Ibex Peak_M P24
SATA1
MB USB P31 ODD (SATA)
Mini card SIM card
USB_P1 P39 PCI-Express PCIE-2
P32 PCI-E
2.5GT/s CLKOUT_PEG_4 3G/GPS P28
USB_P10 P28
DB USB Port x 2
USB_P3, 11 P31 USB 2.0 PCIE-6
B
USB mBGA 676 CLKOUT_PEG_1&3
Mini Card B
(27mm X 25mm) RTC
X'TAL WLAN
P9
Bluetooth 32.768KHz PCIE-1 USB_P13 P28
Azalia HDA
P8.9.10.11.12.13 CLKOUT_PEG_B
USB_P4 P39 MDC
P33 Broadcom
SPI LPC
CCD Giga-LAN
USB_P8 P23 BCM57760 P26
X'TAL
Audio CODEC SPI ROM 25MHz
FingerPrint RJ11 CX20672 P30 4MB x1 (Basic ME+Braidwood) Docking SW
USB_P2 P35 P9
TPM PI3L500 P27
EC (NPCE781) P31
SIMM card
Docking
P34
USB_P5 P28 Transformer P27
A
SPI ROM T/P K/B CON. RJ45 Connector A
P35 P35 P33 P27
Docking Speaker Docking Int. D-MIC MIC Jack HP Jack P34
S/PDIF P30 Line in P23 P30 P30
P33 P33
Docking Docking Quanta Computer Inc.
MIC HP
P33 P33
PROJECT : ZQ3
Size Document Number Rev
1A
Block Diagram
Date: Monday, March 29, 2010 Sheet 1 of 47
5 4 3 2 1
1 2 3 4 5 6 7 8
GPU PWR CTRL Option 1 (Default/ VDDR3 before VDDC)
+3.3V VIN VIN +1.5V +1.5V_SUS +1.8V +5V
VDDR3 +3V_D VDDC PG_GPUIO_EN VDDCI PG_1V_EN +1V (DP PLL PWR) PG_1.5V_EN VDDR1 PG_1.5V_EN VDDR4 PG_1.5V_EN BJT dGPU_PWROK MOS
dGPU_VRON dGPU_PWR_EN#
MOS (AO3413) ISL6264 ISL62872 G9334ADJ & MOS MOS (AO4710) MOS (AO6402) AO3413
P22 P44 P45 P47 P43 P43 P22 P22
A A
+3_D (0.5A) +VGPU_CORE (20A) +VGPU_IO (4.5A) +1V (3A) +1.5V_GPU (10A) +1.8V_GPU (3A) +5_GPU
GPU PWR CTRL Option 2 (VDDR3 after VDDR1)
VIN VIN +1.5V +1.5V_SUS +3.3V +1.8V +5V
VDDC PG_GPUIO_EN VDDCI PG_1V_EN +1V (DP PLL PWR) PG_1.5V_EN VDDR1 +1.5V_GPU VDDR3 +3V_D VDDR4 PG_1.5V_EN BJT dGPU_PWROK MOS
dGPU_VRON dGPU_PWR_EN#
ISL6264 ISL62872 G9334ADJ & MOS MOS (AO4710) MOS (AO3413) MOS (AO6402) AO3413
P44 P45 P47 P43 P22 P43 P22 P22
+VGPU_CORE (20A) +VGPU_IO (4.5A) +1V (3A) +1.5V_GPU (10A) +3_D (0.5A) +1.8V_GPU (3A) +5_GPU
B B
Power States Thermal Follow Chart
CONTROL
POWER PLANE VOLTAGE DESCRIPTION SIGNAL ACTIVE IN
VIN +10V~+19V MAIN POWER S0~S5
+RTC_CELL +3V~+3.3V RTC S0~S5 NTC
+3VPCU +3.3V 8051 POWER ALWON S0~S5 Thermal
Protection
+5VPCU +5V CHARGE POWER ALWON S0~S5
+15V +15V LARGE POWER +15V_ALWP S0~S5
3V_LAN_S5 +3.3V LAN POWER AUX_ON
CPU H_ORICHOT# PM_THRMTRIP# SYS_SHDN# 3V/5 V
+5VSUS +5V SUSD
CORE PWR H/W Throttling
CPU WIRE-AND SYS PWR
C C
+3VSUS +3.3V SUSD
+1.5VSUS +1.5V SODIMM POWER SUSON
+0.75V_DDR_VTT +0.9V SODIMM POWER MAINON SML1ALERT#
+5V +5V MAIND PCH FAN Driver FAN
+3V +3.3V MAIND
+1.8V +1.8V MAINON SM-Bus
+1.5V +1.5V PCH POWER MAIND
+1.1V_VTT +1.05V~+1.1V CPU POWER MAINON EC
CPUFAN#
+1.05V +1.05V PCH POWER MAINON
+VCC_CORE 0V~+1.5V CPU CORE POWER VRON
D D
LCDVCC +3.3V LCD Power LVDS_VDDEN
MBAT+ +10V~+17V MAIN BATTERY
Quanta Computer Inc.
+5V_S5 +5V S5_ON
PROJECT : ZQ3
+3V_S5 +3.3V S5D Size Document Number Rev
1A
PWR Status & GPU PWR CRL & THRM
Date: Monday, March 29, 2010 Sheet 2 of 47
1 2 3 4 5 6 7 8
5 4 3 2 1
+1.5V 150mA(20mil)
L51 BKP1608HS181T/1.5A/180ohm_6 +1.5V_CLK U44
CLK Gen(CLK)
C763 C717 C758 C762 1 80mA(20mil)
R556 VDD_DOT +VDDIO_CLK L50 BKP1608HS181T/1.5A/180ohm_6
5 VDD_27 VDD_SRC_I/O 15 +1.05V
0.1u/16V_4 0.1u/16V_4 *585@0_6 17 18
+3V 4.7u/10V_8 0.1u/16V_4 VDD_SRC VDD_CPU_I/O C761 C747 C759 C753
D 24 VDD_CPU D
29 3 C308 may be can save
VDD_REF DOT_96 CLK_BUF_DREFCLKP (10)
L44 BKP1608HS181T/1.5A/180ohm_6 +3V_CLK 4 0.1u/16V_4 10u/10V_8
DOT_96# CLK_BUF_DREFCLKN (10)
CLK_SDATA 31 0.1u/16V_4 10u/10V_8
C700 C718 C749 CLK_SCLK SDA
32 SCL 27M 6 TP91
7 TP90 2/5 modified Place each 0.1uF cap as close as
4.7u/10V_8 0.1u/16V_4 27M_SS
possible to each VDD IO pin. Place
0.1u/16V_4 R588 33_4 CPU_SEL 30 10 the 10uF caps on the VDD_IO plane.
(10) CLK_ICH_14M REF_0/CPU_SEL SRC_1/SATA CLK_BUF_PCIE_3GPLLP (10)
SRC_1#/SATA# 11 CLK_BUF_PCIE_3GPLLN (10)
C752 33p/50V_4 13
SRC_2 CLK_BUF_DREFSSCLKP (10)
SRC_2# 14 CLK_BUF_DREFSSCLKN (10)
1
XTAL_IN 28
Y8 XTAL_IN +3V
14.318MHZ XTAL_OUT 27 16 R603 10K_4
XTAL_OUT *CPU_STOP#
2
C757 2 20
VSS_DOT CPU_1 TP83
33p/50V_4 8 19
VSS_27 CPU_1# TP84
C 9 VSS_SATA CPU_0 23 CLK_BUF_BCLKP (10) C
12 VSS_SRC CPU_0# 22 CLK_BUF_BCLKN (10)
21 VSS_CPU
26 25 CK_PWRGD_R
VSS_REF CKPWRGD/PD#
33 GND
SLG8SP595V
+3V +3V
CPU_CLK select(CLK) SMBus(CLK) CLK Enable(CLK)
+1.05V
R620
R554 1K/F_4
B B
2
R587 2.2K_4
*10K_4 CK_PWRGD_R
3 1 CLK_SDATA CLK_SDATA (14,15,28)
(10,26,28) ICH_SMBDATA
3
Q43
CPU_SEL Q41 2N7002D
2N7002D
(40) VR_PWRGD_CK505# 2 R621
100K/F_4
R576 C733 +3V
10K_4 *10p/50V_4
1
R555
2
2.2K_4
0 1
A
(10,26,28) ICH_SMBCLK 3 1 CLK_SCLK CLK_SCLK (14,15,28) Quanta Computer Inc. A
CPU_SEL CPU0/1=133MHz CPU0/1=100MHz Q42
2N7002D
PROJECT :ZQ3
(default)
Size Document Number Rev
1A
Clock Generator
Date: Monday, March 29, 2010 Sheet 3 of 47
5 4 3 2 1
5 4 3 2 1
Arrandale_1(CPU) AUBURNDALE/CLARKSFIELD PROCESSOR (DMI,PEG,FDI) AUBURNDALE/CLARKSFIELD PROCESSOR (CLK,MISC,JTAG)
Processor Compensation Signals
U36A U36B
B26 R440 49.9/F_4 R497 20/F_4 H_COMP3 AT23
PEG_ICOMPI COMP3
A26 A16 CLK_CPU_BCLKP (11)
PEG_ICOMPO BCLK
MISC
MISC
A24 B27 R494 20/F_4 H_COMP2 AT24 B16 CLK_CPU_BCLKN (11)
(8) DMI_TXN0 DMI_RX#[0] PEG_RCOMPO COMP2 BCLK#
C23 A25 R441 750/F_4
(8) DMI_TXN1 DMI_RX#[1] PEG_RBIAS R145 49.9/F_4 H_COMP1
CLOCKS
(8) DMI_TXN2 B22 PEG_RXN[0..15] (16) G16 AR30 TP70
DMI_RX#[2] PEG_RXN0 COMP1 BCLK_ITP
(8) DMI_TXN3 A21 K35 AT30 TP63
D DMI_RX#[3] PEG_RX#[0] PEG_RXN1 R483 49.9/F_4 H_COMP0 BCLK_ITP# D
J34 AT26
PEG_RX#[1] PEG_RXN2 COMP0
(8) DMI_TXP0 B24 J33 E16 CLK_PCIE_3GPLLP (10)
DMI_RX[0] PEG_RX#[2] PEG_RXN3 PEG_CLK
(8) DMI_TXP1 D23 G35 D16 CLK_PCIE_3GPLLN (10)
DMI_RX[1] PEG_RX#[3] PEG_CLK#
DMI
DMI
B23 G32 PEG_RXN4 TP5 TP_SKT0CC# AH24
(8) DMI_TXP2 DMI_RX[2] PEG_RX#[4] SKTOCC#
A22 F34 PEG_RXN5