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Alumina & Leaded Molded Technology 3
3.1 Introduction
The packaging technologies used to manufacture or assemble three basic types of component
packages are summarized in this chapter.
The package families, described in Chapter 1, provide the functional specialization and diversity
required by device and product applications. Material and construction attributes of individual
family members are provided by the following package technologies: (1) fired ceramic, (2) pressed
ceramic, and (3) molded plastic. Intel's packaging technology using organic substrates will be
discussed in chapters 13, 14, and 15. Cartridge packaging assembly will be discussed in Chapter
16.
Each of the three package families described in this chapter have some similar process steps but,
the packaging materials and the form factors are uniquely different.
The assembly core technology process steps (die attach, wire bond, lid seal, finish) are most
commonly used in the industry today. However, several form factor modifications, driven on one
hand by the advent of "Surface Mount Technology" (Quad Flat Pack packages and Ball Grid
Array) and on the other hand by area array package socketing requirements (Pin Grid Array) are
now the more commonly used form factors for microprocessors.
This chapter will review in detail those core packaging technologies that are common to most of
the standard IC package family types, i.e. DIPs, QFPs & Ceramic PGAs.
3.2 Die Preparation
Intel's die preparation consists of wafer mount and wafer saw process. Intel protects the active
surface of wafers from handling-induced defects by using a contactless wafer mounting process.
The wafer is mounted to a mylar tape to ensure the die is in place during and after sawing process.
The mounted wafer is sawn into singulated die followed by high pressure deionized (DI) water
wash. The wafer wash process is properly characterized to ensure no silicon dust and static charge
build-up which will induce passivation damage. Intel uses 100% wafer saw through process to
prevent die chipping.
3.3 Die Attach
For these packages Intel uses two categories of die attach adhesive materials: (1) adhesives, both
organic and inorganic; and (2) hard solders (gold-silicon eutectic). The choice of die attach
material depends on the specific applications and its compatibility with the particular packaging
technologies to ensure the highest levels of reliability performance. Table 3-1 and Table 3-2
summarize the die attach materials used by package technology.
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Alumina & Leaded Molded Technology
Table 3-1. Die Attach Materials by Package Technology
Package Technology Die Attach Material Type
Pressed Alumina Ceramic Silver-Filled Glass Inorganic Adhesive
(CERDIP)
Laminated Alumina Ceramic Gold-Silicon Eutectic Hard Solder
(PGA, CQFP, Side-Braze) Silver-Filled Cyanate Ester Organic Adhesive
Molded Plastic Silver-Filled Epoxy Organic Adhesive
Table 3-2. Die Attach Material Summary
Silver-Filled Epoxy/
Silver-Filled
Au-Si Cyanate Ester
Glass
Wafer Backside Metallization for Die Required Not Required Not Required
Attach
Wafer Backside Metallization for Not Required Required Required
Ohmic Contact
Thermal Dissipation Good Good Fair
Electrical Conductivity Good Good Fair
Lead Frame Compatibility N/A N/A Good
Substrate Metallization Compatibility
(a) Gold
(b) Silver Good Poor Good
(c) A12O3 Good Good Good
N/A Good N/A
Figure 3-1 through Figure 3-4 are schematic cross-sections through each of the different die attach
systems currently in use at Intel, for example, gold/silicon eutectic, silver-filled glass, and silver
filled organic adhesives, epoxy, and cyanate ester. The components of each system are identified.
Figure 3-1. Gold-Silicon Eutectic
Gold/Silicon Eutectic Alloy
Silicon
}
Silver or Gold Reaction Zone
Thick-Film Metalization (Metallurgical Bond)
Al203
240818-5
A5588-01
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Alumina & Leaded Molded Technology
Figure 3-2. Silver-Filled Glass
Silver-Filled Glass
Silicon
Al203
240818-6
A5589-01
Figure 3-3. Silver-Filled Cyanate Ester
Silver-Filled Cyanate Ester
Silicon
Al203
240818-35 A5590-01
Figure 3-4. Silver-Filled Adhesive
Polymide, Epoxy or
Silicon Cyanate Ester Ag-Filled Adhesive
Silver
Nickel
Copper
240818-7 A5591-01
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3.3.1 Purpose of Each Component
Wafer metallization provides an ohmic contact to the silicon die for the purpose of substrate
biasing for those die attach media that do not readily form an ohmic junction. It provides a readily
wettable surface for gold/silicon hard soldering and prevents premature oxidation (or aging) of the
wafer backside during storage by acting as a diffusion barrier, thus ensuring that die attach integrity
remains uncompromised.
Like the wafer backside, substrate metallization provides a readily wetted surface for hard
soldering. Metallizations used in hermetic package technologies, both gold and silver, are readily
wetted by the liquid solder at die attach temperatures and actually react with the solder to provide a
high-integrity metallurgical bond to the substrate. Both substrate metallizations resist oxidation,
which can impede wetting, and are electrically conductive for those devices that require electrical
contact.
Plastic packages use a plated silver metallization to adhere to organic adhesives, which are
electrically conductive. Silver-filled glass does not require a metallization, though it will adhere
readily to silver.
Die attach media serve several purposes other than the obvious one of attaching the silicon to the
substrate. They also provide a means of making an electrical connection to the die backside for
those devices requiring it, as well as a path for the conduction of heat from the die to the ambient.
For these reasons, the die attach media used at Intel exhibit good thermal and electrical
conductivity.
The incoming quality of die attach materials is monitored through a series of specifications unique
to each of the die attach media. Tests are performed to measure those specific characteristics
necessary to ensure that materials meet the requirements of die attach applications.
3.3.2 Die Attach Process Consideration
From a process design standpoint, it is necessary to understand the limitations of each die attach
process. Every die attach technology used at Intel has its own limitations and merits. The materials
and process must be carefully characterized to ensure good package compatibility, reliability and
manufacturability.
3.3.2.1 Au-Si Eutectic
There are three key considerations to the Au-Si Eutectic process. Foremost is the effect of
processing temperature on die reliability and performance. It is necessary to design the silicon
fabrication processes so that the device can withstand the Au-Si process temperatures during die
attach. Next is the need to have good die backside metallization for high reliability performance.
All wafers used in this process use a gold wafer backside metallization. The third consideration is
the need for an excellent process control.
3.3.2.2 Silver-filled Glass (SFG)
SFG, like Au-Si eutectic, is limited to those devices which can withstand SFG processing
temperature and time. The silicon fabrication processes should be designed to withstand the die
attach process. Because of the organic content (solvent and resin binder) of the SFG paste, its
removal is necessary for good adhesion. The larger the die, the longer is the drying/processing time
for organic content removal.
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Alumina & Leaded Molded Technology
There are also limits to the bond line thickness, both thin and thick, that constrain the process. In
addition, it is imperative to maintain a nearly void-free die attachment. SFG is limited to (1) non-
gold wafer backsides and substrates due to poor adherence to gold, and (2) inert or oxidizing
processing ambients.
Like Au-Si eutectic, SFG requires close process control. Once processed, the SFG material is
stable to extremely high temperatures.
3.3.2.3 Silver-filled Epoxy/Cyanate Ester
There are two significant considerations for epoxy and cyanate ester adhesives: the first is the
upper temperature that the material can tolerate before decomposition of the polymer occurs, which
is approximately 200