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SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO'S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
D
CYGNUS C Sheet 1. COVER
Sheet 2 - 4. DIAGRAM (Block/Power) & ANNOTATIONS
Sheet 5. CLOCK GENERATOR
Sheet 6 - 8. DOTHAN533 / YONAH CPU(TBD)
Sheet 9. THERMAL SENSOR / FAN CONTROL
Sheet 10 - 14. ALVISO-GMCH
CPU :Intel Dothan533 / Yonah(TBD) Sheet15. DDR II SODIMM
Sheet16. DDR TERMINATION
Chip Set :Intel Alviso & ICH6-M Sheet17 - 20. ICH6-M
Sheet21. FWH
Remarks : Mobility Platform Sheet22. LVDS VOLTAGE TRANSLATION LOGIC C
Sheet23. DVI CONTROLLER
Sheet24. RGB SWITCH / SPREAD SPECTRUM
Sheet25. CRT PORT
Sheet26. LCD Connector / BKLT
Model Name : CYGNUS C Sheet27 - 28. CARDBUS / 1394 / MEDIA CARD
Sheet29. MINI PCI
Sheet30- 31. AUDIO CODEC(AD 1986)
PBA Name : MAIN Sheet32. HDD & ODD Connector
Sheet33. MDC MODEM / S-VHS / FAN
PCB Code : BA41-00451A Sheet34. MICOM
Dev. Step : MP Sheet35 - 36. LAN(Broadcom BCM4401)
Sheet37. DOCKING CONNECTOR / Super IO
Revision : 1.0 Sheet38. B'D TO B'D Connector
Sheet39. MAIN DDR POWER B
Sheet40. SWITCHED POWER
T.R. Date : NOV 29 2004 Sheet41. CHARGER
Sheet42. CPU POWER(VCC_CORE)
Sheet43. P1.5V / P2.5V
Sheet44. P1.5V_AUX / VTT
DRAW CHECK APPROVAL Sheet45. TPM / AIR BAG / MOUNT HOLE
Sheet46. USB BOARD
Sheet47. REVISION HISTORY
Sheet48 - 49. REVISION HISTORY
A
SAMSUNG
Owner : SEC Mobile R & D Signature : X ELECTRONICS
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4 3 2 1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO'S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
FAN CPU
PG 9
Mobile Processor DC/DC System DC/DC
IMVP-IV
Dothan(w/533MHz) R 1.3
Smart
D CPU PG ? Charging Battery D
PCIE Graphics Module Thermistor PG ?
MAX6656
& Yonah Circuit Module
PG 9 L2 Cache : 2 MB
PG 6,7,8 478pin
30P DDR II
PSB Thermistor
100P X 2 533 MT/S PG 16 DDR II DC/DC
LCD LVDS Ext. AGP External Graphics
VRM
PEG x16 DDR II PG 15 DC/DC Module
Channel A (Standard)
CRT/TV ATI M24-P (TBD)
PG 22,23,24
SODIMM 0
PG 27
GMCH-M Dual channel DDR II 533/400
DDR II PG 15
Ext. SDVO SDVOB/C Alviso-GM Channel B (Reverse)
SODIMM 1
Chrontel CH7307 1257 FCBGA
ANT
PG 10,11,12,13,14
PG 23 D/T
30P LVDS Internal Graphics
LCD CRT/TV
PCI
Wireless LAN SD/MS PG 29
Direct Media Interface Slot
PG 27
x4/x2, 1.5V
CARDBUS CardBus PG 29
C Mini PCI CONN. R5C841 C
DB400 Clocking PG 28
CRT PG 32 PG 28, 29 EEPROM PG 28
PG 26 PG 5 R5532V002
CK-410M
SSDC 33MHz, 3.3V PCI
PG 5 1394 1394
TV PG 5 CARDBUS Module 6pin 6pin
PG 33
PCIE x1 Lane 0 PG 28 PG 38 (Docking)
SVHS / HDTV USB 0,1,2 ICH6-M BROADCOM
RJ45
PG 33 USB 0,1 ANT 82570EI PG 36
USB4 609 BGA BCM5751M
Bluetooth LCI 82562EZ
PG 38 PG 36 TPM PG 36
USB3
PG 38 Finger Print PCIE x1 Lane 2
PG 31 Azalia/AC97 Primary PG 18,19,20,21 Mini PCIE CONN.
PG 30
PG 30
AUDIO 30P
Audio MDC 130P
Azalia/AC97 Secondary
Azalia RJ11 Modem USB 5 DOCKING DVI + USB 5 + VGA + LAN+PCIE
AMP Codec PG 39
PG 33 (TBD)
B
AD1986 PG 33
B
PG 31
HP & SPDIF.
Line In
MIC-IN
FWH
2P 2P 82802AC PG ?
PG 22 PG 38
Scan EMA
Pri. IDE master PATA KBD
HDD
Pri. IDE slave
PG 32
U-ATA 100
SPKR R
Touch
3.3V LPC, 33MHz 60x2P MICOM PAD
PG 38
Hitachi H8S
PG 35 HD64F2169/2160
KBD PG 38
SPKR L
PG 32
CD-ROM
CD / DVD
A A
SAMSUNG
ELECTRONICS
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SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
Power Diagram
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO'S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
D ALWAYS KBC3_SUSPWR KBC3_PWRON KBC3_VRON D
ADAPTOR
BATTERY ALVISO-GM
P1.5V ICH6-M
P1.5V_AUX PEG
ICH6-M
P1.2V
ALVISO-GM Thermal Sensor MICOM
P3.3V_AUX P3.3V ICH6-M SODIMM R5C592
CK410-M FWH M_PCI
ICH6-M MDC SUPER I/O PCMCIA TPM
P3.3V_ALWAYS LAN BT PEG LEDs EMA(AON)
LCD MDC
C ALVISO-GM C
ICH6-M
P2.5V R5C592
PEG
BRIDGE
ICH6-M PCMCIA HDD
BATTERY P5V_AUX P5V FDD USB M_PCI
CRT PS/2 PEG
DDR Power PIO MICOM FAN CIRCUIT
R5C592 MDC HEATSINK
VDC P1.8V_AUX P1.8V SODIMM (DDR II)
PEG
SODIMM (DDR II)
ALVISO-GM
P0.9V DDR II-Termination
MICOM_P3V DDR II for PEG (TBD)
B B
GFX_
CORE
ATI M24 : P1.0V - P1.2V
VTT nVidia NV4xM/MEP4x : P0.9V - P1.3V
VCC_CORE
Rail
+V*Always +V*AUX +V SUSPWR PWRON VRON
State
DOTHAN533 / YONAH
A Full On ON ON ON ON ON ON A
S3 ON ON OFF ON OFF OFF
S4 ON ON OFF ON OFF OFF SAMSUNG
S5 ON OFF OFF OFF OFF OFF ELECTRONICS
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SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO'S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
D
SCHEMATIC ANNOTATIONS AND BOARD INFORMATION D
PCI Devices Voltage Rails
Devices IDSEL# REQ/GNT# Interrupts
Cardbus AD25 0 A,B,C VDC Primary DC system power supply (7 to 21V)
AD21 3 VCC_CORE Core voltage for DOTHAN (1.308~1.068V)
MiniPCI SLOT1 AD23 2 D,E VTT DOTHAN/ALVISO Processor System Bus(PSB) Termination (1.05V)
USB AD29(internal) - USB2.0 #0 : A MCH-M Core Voltage
USB2.0 #1 : D
USB2.0 #2 : C P0.9V 0.9V switched power rail (off in S3-S5)
Hub to PCI AD30(internal) - - P1.2V 1.2V switched power rail (off in S3-S5)
LPC bridge/IDE/AC97/SMBUS AD31(internal) - B P1.5V 1.5V switched power rail (off in S3-S5)
- A,B P1.5V_AUX 1.5V power rail (off in S4-S5)
Internal MAC AD24(internal) - E P1.8V 1.8V switched power rail (off in S3-S5)
AC Link - - B P1.8V_AUX 1.8V power rail(off in S4-S5)
P2.5V 2.5V switched power rail (off in S3-S5)
MICOM_P3V 3.3V always on power rail for MICOM
P3.3V 3.3V switched power rail (off in S3-S5)
P3.3V_AUX 3.3V power rail (off in S4-S5)
C P5V 5.0V switched power rail (off in S3-S5) C
P5V_AUX 5.0V power rail (off in S4-S5)
CPU Core Voltage Table
2
VID5 VID4 VID3 VID2 VID1 VID0 Voltage VID5 VID4 VID3 VID2 VID1 VID0 Voltage
0 0 0 0 0 0 1.708 V 1 0 0 0 0 0 1.196 V Northwood-B
I C / SMB Address
0 0 0 0 0 1 1.692 V 1 0 0 0 0 1 1.180 V (Interposer B'd) Devices Address Hex Bus
0 0 0 0 1 0 1.676 V 1 0 0 0 1 0 1.164 V
0 0 0 0 1 1 1.660 V 1 0 0 0 1 1 1.148 V ICH6 Master - SMBUS Master
0 0 0 1 0 0 1.644 V 1 0 0 1 0 0 1.132 V EMC6N300(CPU Thermal Sensor) 1001 110X 9Ch Thermal Sensor
0 0 0 1 0 1 1.628 V 1 0 0 1 0 1 1.116 V SODIMM0 1010 0000 A0h -
0 0 0 1 1 0 1.612 V 1 0 0 1 1 0 1.100 V SODIMM1 1010 001X A2h -
-
0 0
- 0 1 1 1 1.596 V 1 0
- 0 1 1 1 1.084 V CK-408 (Clock Generator) 1101 001x D2h Clock, Unused Clock Output Disable
0 0 1 0 0 0 1.580 V 1 0 1 0 0 0 1.068 V
0 0 1 0 0 1 1.564 V 1 0 1 0 0 1 1.052 V
0 0 1 0 1 0 1.548 V 1 0 1 0 1 0 1.036 V
0 0 1 0 1 1 1.532 V 1 0 1 0 1 1 1.020 V
0 0 1 1 0 0 1.516 V 1 0 1 1 0 0 1.004 V
0
0
0
0
1
1
1
1
0
1
1
0
1.500 V
1.484 V
1
1
0
0
1
1
1
1
0
1
1
0
0.988 V
0.972 V USB PORT Assign
0 0 1 1 1 1 1.468 V 1 0 1 1 1 1 0.956 V
0 1 0 0 0 0 1.452 V 1 1 0 0 0 0 0.940 V PORT NUMBER ASSIGNED TO
0 1 0 0 0 1 1.436 V 1 1 0 0 0 1 0.924 V
0 1 0 0 1 0 1.420 V 1 1 0 0 1 0 0.908 V 0 SYSTEM PORT A
0 1 0 0 1 1 1.404 V 1 1 0 0 1 1 0.892 V 1,2 SYSTEM PORT B
B 0 1 0 1 0 0 1.388 V 1 1 0 1 0 0 0.876 V 3 BLUETOOTH OPTION B
0 1 0 1 0 1 1.372 V 1 1 0 1 0 1 0.860 V 4 FINGER PRINT OPTION
Highest Freq. 0 1 0 1 1 0 1.356 V 1 1 0 1 1 0 0.844 V Lowest Freq.
-
0 1 0 1 1 1 1.340 V 1 1 0 1 1 1 0.828 V
0 1 1 0 0 0 1.324 V 1 1 1 0 0 0 0.812 V
0 1 1 0 0 1 1.308 V 1 1 1 0 0 1 0.796 V
0 1 1 0 1 0 1.292 V 1 1 1 0 1 0 0.780 V
0
0
1
1
1
1
0
1
1
0
1
0
1.276 V
1.260 V
1
1
1
1
1
1
0
1
1
0
1
0
0.764 V
0.748 V Deeper Sleep System Power States
0 1 1 1 0 1 1.244 V 1 1 1 1 0 1 0.732 V CHP3_SLPS1* S1, Powered-On-Suspend(POS) : In this state, all clocks(except the 32.768KHz clock) are stopped.
0 1 1 1 1 0 1.228 V 1 1 1 1 1 0 0.716 V The system context is maintained in system DRAM. Power is maintained to PCI, the CPU, memory controller, memory, and all other criticial subsystems.
0 1 1 1 1 1 1.212 V 1 1 1 1 1 1 0.700 V Note that this state does not preclude power being removed from non-essential devices, such as disk drives. During this state, CPU can be selected
for either Deep Sleep or Deeper Sleep.
In Deeper Sleep, CPU voltage reduced in this state to reduce the leakage power.
CHP3_SLPS3* S3, Suspend-To-RAM(STR) : The system context is maintained in system DRAM, but power is shut off to non-critical circuits.
Memory is retained, and refreshes continue. All clocks stop except RTC clock.
CHP3_SLP4S* S4, Suspend-To-Disk(STD) : The Context of the system is maintained on the disk. All power is then shut off to the system except for the logic required to resume.
Externally appears same as S5, but may have different wake events.
CHP3_SLPS5* S5, Soft Off(SOFF) : System context is not maintained. All power is shut off except for the logic required to restart. A full boot is required when waking.
REVISION HISTORY
A A
See rev notes in the changes file for more information.
SAMSUNG
ELECTRONICS
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SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO'S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
D D
MMZ1608S121AT P3.3V
B524
TP10380
1000nF
100nF
100nF
100nF
100nF
100nF
100nF
10nF
10nF
C679
10000nF
C274
C268
C678
C279
C278
C273
C269
C276
C275
6.3V
FSA FSB FSC
HOST CLK CK-410M
BSEL2 BSEL1 BSEL0
ICS954201
0 0 0 266 MHz CY28411ZC TP10388
U504
10K
0 0 1 333 MHz CY28411ZXCT MMZ1608S121AT
100nF
100nF
100nF
21 48 B15
0 1 0 200 MHz 28
VDD_SRC0 VDD_REF
11 C271
VDD_SRC1 VDD_48 10000nF
0 1 1 400 MHz 34
VDD_SRC2 6.3V
R655
1 37
C270
C272
C277
1 0 0 133 MHz 7
VDD_PCI0 VDD_A
VDD_PCI1
1 0 1 100 MHz 42
VDD_CPU VSS_A
38
1 1 0 166 MHz 18-A? 48-C3 R654 TP10381
33 1% 12
CLK3_USB48 FSA_USB48
41 TP10389
1 1 1 RSVD CLK3_BSEL1
16