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D D
DR1 (Roberts) Schematics Document
uFCPGA Mobile Penryn
C
Intel Cantiga-GM + ICH9M C
2008-10-02
REV : A00
B B
DY : Nopop Component
A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number
Cover Page Rev
Custom A00
Roberts
Date: Thursday, October 02, 2008 Sheet 1 of 58
5 4 3 2 1
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CPU DC/DC
Roberts Block Diagram INPUTS
ISL6266A
OUTPUTS
28,29
+PWR_SRC +VCC_CORE
SYSTEM DC/DC
D
Clock Generator Intel Mobile CPU Project code : 91.4AQ01.001 TPS51117 30 D
SLG8SP513VTR 4 Penryn PCB P/N : 48.4AQ01.011 INPUTS OUTPUTS
Socket P 5,6,7
Revision : 08212-1 +PWR_SRC +1.05V_VCCP
SYSTEM DC/DC
MAX17020 27
FSB
INPUTS OUTPUTS
800/1066MHz +5V_ALW2
+3.3V_RTC_LDO
+PWR_SRC +5V_ALW
+3.3V_ALW
Intel
DDRII Slot 0 CRT SYSTEM DC/DC
667/800 14
DDRII 667/800 Channel A Cantiga-GML RGB CRT
(on I/O board)
TPS51116 31
Power SW
AGTL+ CPU I/F 41 INPUTS OUTPUTS
G577BR91U
DDRII Slot 1 DDR Memory I/F LVDS(Dual Channel) LCD +1.8V_SUS
C DDR II 667/800 Channel B 35 +PWR_SRC +0.9V_DDR_VTT C
15
667/800 External Graphics +V_DDR_MCH_REF
8,9,10,11,12,13
PCIE x 1 & USB 2.0 x 1 New Card SYSTEM DC/DC
41
APL5912 32
INPUTS OUTPUTS
DMIx4 C-LINK PCIE x 1 10/100 NIC RJ45
I/O Board
Connector
20
Marvell 88E8040 CONN +1.8V_SUS +1.5V_RUN
SYSTEM DC/DC
Left Side: LDO 34
USB 2.0 x 2
CardReader Intel PCIE 41 USB x 2
INPUTS OUTPUTS
SD/MMC +5V_ALW +5V_RUN
MS/MS Pro/xD
Realtek USB2.0 ICH9-M PCIE x 1 Mini-Card +3.3V_ALW +3.3V_RUN
37
37 RTS5158E 802.11a/b/g
USB 2.0/1.1 ports (12)
21
PCI Express ports (6) MAXIM CHARGER
High Definition Audio USB 2.0 USB 2.0 x 1 CAMERA MAX8731A 26
B
CAMERA Module 41
B
(Option)
SATA ports (4) INPUTS OUTPUTS
Digital Mic Array Azalia LPC I/F +DC_IN
AZALIA +PWR_SRC
USB 2.0 x 1 +PBATT
CODEC ACPI 1.1 Bluetooth 41
MIC IN PCI/PCI BRIDGE
IDT
92HD71B7 16,17,18,19
LPC Bus
Right Side:
PCB LAYER
USB 2.0 x 1
Internal Analog MIC 22 USB x 1 43
L1: Top
L2: VCC
KBC L3: Signal
SATA
SATA
HP1 OP AMP SPI WINBOND
24 L4: Signal
WPCE773L
MAX9789A
23 L5: GND
L6: Bottom
A A
2CH SPEAKER Thermal & Fan
Flash ROM Touch Int.
HDD ODD
2MB 42 PAD KB EMC2102
Wistron Corporation
36 36 25 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
44 44 Taipei Hsien 221, Taiwan, R.O.C.
40
Title
Block Diagram
Size Document Number Rev
Custom A00
Roberts
Date: Thursday, October 02, 2008 Sheet 2 of 58
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A B C D E
ICH9 Integrated pull-up Cantiga chipset and ICH9M I/O controller
ICH9M Functional Strap Definitions
and pull-down Resistors Hub strapping configuration
ICH9 EDS 642879 Rev.1.5 ICH9 EDS 642879 Rev.1.5 Montevina Platform Design guide 22339 Rev.0.5
Signal Usage/When Sampled Comment SIGNAL Resistor Type/Value Pin Name Strap Description Configuration
HDA_SDOUT XOR Chain Entrance/ Allows entrance to XOR Chain testing when TP3 CL_CLK[1:0] PULL-UP 20K CFG[2:0] FSB Frequency Select 000 = FSB1067
PCIE Port Config1 bit1, pulled low. When TP3 not pulled low at rising edge 011 = FSB667
Rising Edge of PWROK. of PWROK, sets bit1 of RPC.PC (Cofig Registers: CL_DATA[1:0] PULL-UP 20K 010 = FSB800
others = Reserved
offset 224h). This signal has weak internal CL_RST0# PULL-UP 20K
4 pull-down. CFG[4:3] Reserved 4
DPRSLPVR/GPIO16 PULL-DOWN 20K CFG8
CFG[15:14]
HDA_SYNC PCIE config1 bit0, This signal has a weak internal pull-down. ENERGY_DETECT PULL-UP 20K CFG[18:17]
Rising Edge of PWROK. Sets bit0 of PRC.PC (Config Registers: Offset
224h). HDA_BIT_CLK PULL-DOWN 20K CFG5 DMI x2 Select 0 = DMI x2
1 = DMI x4 (Default)
HDA_DOCK_EN#/GPIO33 PULL-UP 20K
GNT2#/ PCIE config2 bit2, This signal has a weak internal pull-up. CFG6 iTPM Host Interface 0 = The iTPM Host Interface is enabled (Note 2)
GPIO53 Rising Edge of PWROK. Sets bit2 of PRC.PC2 (Config Registers: Offset HDA_RST# PULL-DOWN 20K 1 = The iTPM Host Interface is disabled (default)
224h). HDA_SDIN[3:0] PULL-DOWN 20K CFG7 Intel Management 0 = Transport Layer Security (TLS) cipher
engine crypto strap suite with no confidentiality
GPIO20 Reserved. This signal should not be pulled high. HDA_SDOUT PULL-DOWN 20K 1 = TLS cipher suite with confidentiality(Default)
GNT1#/ ESI Strap (Server Only) ESI compatible mode is for server platforms only. HDA_SYNC PULL-DOWN 20K CFG9 PCIE Graphics Lane 0 = Reserved Lanes, 15->0, 14->1 ect..
GPIO51 Rising Edge of PWROK. This signal should not be pulled low for desktop 1 = Normal operation (Default): Lane Numbered in
and mobile. GLAN_DOCK# The pull-up or pull-down Order
active when configured
for native GLAN_DOCK# CFG10 PCIE Loopback enable 0 = Enable (Note 3)
GNT3#/ Top-Block Swap Sampled low: Top-Block Swap mode (inverts A16 for 1 = Disable (Default)
GPIO55 override. Rising Edge all cycles targeting FWH BIOS space). functionality and determined
of PWROK. Note: Software will not be able to clear the by LAN controller. CFG[13:12] XOR/ALL 00 = Reserve
10 = XOR mode Enabled
Top-Swap bit until the system is rebooted 01 = ALLZ mode Enable (Note 3)
without GNT3# being pulled down. GNT[3:0]#/GPIO[55,53,51] PULL-UP 20K 11 = Disabled (Default)
GPIO20 PULL-DOWN 20K CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled
GNT0#: Boot BIOS Destination Controllable via Boot BIOS Destination bit 1 = Dynamic ODT Enabled (Default)
SPI_CS1#/ Selection 0:1. (Config Registers: Offset 3410h:bit 11:10). GPIO49 PULL-UP 20K
3 GPIO58 Rising Edge of PWROK. GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC CFG19 DMI Lane Reversal 0 = Normal operation (Default): Lane Numbered in 3
LDA[3:0]#/FHW[3:0]# PULL-UP 20K Order
1 = Reverse Lanes
SPI_MOSI Integrated TPM Enable, Sample low: the Integrated TPM will be disable. LAN_RXD[2:0] PULL-UP 20K DMI x4 mode [MCH->ICH]: (3->0, 2->1, 1->2 and 0->3)
Rising Edge of CLPWROK. Sample high: the MCH TPM enable strap is sampled DMI x2 mode [MCH->ICH]: (3->0, 2->1)
low and the TPM Disable bit is clear, the LDRQ[0] PULL-UP 20K
CFG20 Digital Display Port 0 = Only Digital Display Port or PCIE is
Integrated TPM will be enable. LDRQ[1]/GPIO23 PULL-UP 20K (SDVO/DP/iHDMI) operational (Default)
GPIO49 DMI Termination The signal is required to be low for desktop PME# PULL-UP 20K simulataneously via
and PCIe are
Concurrent with PCIe 1 = Digital display Port the PEG port operating
Voltage. Rising Edge applications and required to be high for mobile
of CLPWROK. applications. PWRBTN# PULL-UP 20K SDVO SDVO Present 0 = No SDVO Card Present (Default)
_CTRLDATA 1 = SDVO Card Present
SATALED# PULL-UP 15K
SATALED# PCI Express Lane Signal has weak internal pull-up. Sets bit 27 L_DDC_DATA Local Flat Panel 0 = LFP Disabled (Default)
Reversal. Rising Edge of MPC.LR (Device 28: Function 0:Offset D8). SPI_CS1#/GPIO58/CLGPIO6 PULL-UP 20K (LFP) Present 1 = LFP Card Present; PCIE disabled
of PWROK. SPI_MOSI PULL-DOWN 20K
NOTE:
No Reboot. If sampled high, the system is strapped to the SPI_MISO PULL-UP 20K
SPKR Rising Edge of PWROK. "No Reboot" mode (ICH9 will disable the TCO Timer 1. All strap signals are sampled with respect to the leading edge of the (G)MCH
system reboot feature). The status is readable SPKR PULL-DOWN 20K Power OK (PWROK) signal.
via the NO REBOOT bit. TACH_[3:0] PULL-UP 20K 2. iTPM can be disabled by a 'Soft-Strap' option in the Flash-decriptor section of
the Firmware. This 'Soft-Strap' is activated only after enabling iTPM via CFG6.
XOR Chain Entrance. This signal should not be pull low unless using TP[3] PULL-UP 20K Only one of the CFG10/CFG12/CFG13 straps can be enabled at any time.
TP3 Rising Edge of PWROK. XOR Chain testing.
USB[11:0][P,N] PULL-DOWN 15K
GPIO33/ Flash Descriptor Sampled low: the Flash Descriptor Security will be
HDA_DOCK Security Override overridden. If high, the security measures will be
2 _EN# Strap. Rising Edge of in effect. This should only be enabled in 2
PWROK. manufacturing environments using an external
pull-up resister.
PCIE Routing USB Table
USB
Pair Device
LANE2 MiniCard WLAN 0 USB1
1 USB2
LANE3 LAN 2 USB3
LANE5 New Card 3 RESERVED
4 MINI CARD
5 RESERVED
1 6 BLUETOOTH 1
7 NEW CARD
8 RESERVED Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
9 RESERVED
Title
10 Card Reader
11 CAMERA Size Document Number
Table of Content Rev
Custom A00
Roberts
Date: Thursday, October 02, 2008 Sheet 3 of 58
5 4 3 2 1
SSID = CLOCK NEWCARD_CLKREQ#
MINI1_CLKREQ#
R193 1
R195 1
2 10KR2J-3-GP
2 10KR2J-3-GP
+3.3V_RUN
NEWCARD_CLKREQ#
CLK_PCIE_NEW
3D3V_S0_CK505 3D3V_S0_CK505_IO CLK_PCIE_NEW#
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
+3.3V_RUN
SC22P50V2JN-4GP
3D3V_S0_CK505_IO CLK_XTAL_IN
1
1
1
C463
C464
EC57
X3
1 R204 CLK_XTAL_OUT
D
2 1 2
DY DY D
SC1U10V3KX-3GP
0R0603-PAD
SC10U6D3V5MX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
2
2
2
X-14D31818M-37GP
1
1
1
1
1
1
1
1
1
C229
C226
C210
C239
C209
C215
C237
16
46
62
23
19
27
43
52
33
56
4
9
C462 C461 U54
DY SC12P50V2JN-3GP SC12P50V2JN-3GP
VDD96_IO
VDDPLL3_IO
VDDSRC_IO
VDDSRC_IO
VDDSRC_IO
VDDCPU_IO
VDDSRC
VDDCPU
VDDREF