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PCB STACK UP
TE3 BLOCK DIAGRAM CPU CORE LAYER 1: TOP
DDRIII-SODIMM1 LAYER 2: GND1
PG 15 NB CORE LAYER 3: IN1
DDR III 1066 MHZ CPU_CLK
HOST 200MHz
AMD S1g4 (1.0~1.2V) LAYER 4: IN2
CLOCK GENERATOR PCIE 100MHz LAYER 5: VCC
DDRIII-SODIMM2 NBGFX_CLK
D ICS9LPRS476AKLFT LAYER 6: BOT D
PG 15 USB 48MHz +2.5V
NBGPP_CLK SLG8SP628VTR
RTM880N-795 REF 14MHz +1.5V
SBLINK_CLK
PG 2
(638 S1g4 socket) +1.2V
PG 3,4,5 Daughter Board
HT_LINK MMB Board
HDMI PCI-E, 1X (port2) AR8152M(10/100) RJ45
PG 23 PG 29
HDMI +1.5VSUS
SMDDR Audio & USB Board
LVDS LVDS(2ch) RX881/RS880MN/RS880MC PCI-E, 1X (port0) VTERM
PG 24 Mini Card I (WIFI)
USB2.0 (P7)
21mm X 21mm, 528pin BGA
PG 25 Touch Pad Board
CRT LVDS HDMI 3V/5V (with FP & w/o FP)

CRT Side port
DDR3
C
PG 24 FRAME BUFFER
C

Graphics PCI-E X16 PG 6,7,8,9 PG 6
PG 16,17,18,19,20,21,22
A_LINK (X4) LED Board


SYSTEM MDC Board
CHARGER
SBSRC_CLK
SB820
SATA - HDD1 SATA0
PG 27
USB2.0 (P9) USB2.0 I/O Ports X1
USB2.0 (P0) CCD (M/B) PG 26
PG 24
SATA - ODD SATA3
USB2.0 (P5) USB2.0 I/O Ports X1
USB2.0 (P3) Card reader
PG 27 (Daughter Board)
B
PG 30 B

21mm X 21mm, 528pin BGA
E - SATA SATA2
4.5W(Ext)
PG 26 USB2.0 (P13) 4.3W(Int) USB2.0 (P2) Bluetooth USB2.0 (P6) MINI CARD II (3G)
PG 32 PG 25


Azalia
PG 13,14,15,16,17 Azalia Audio Codec
CX20583 PG 28
LPC




PORT-A




PORT-B
MDC CONN
EC
PG 28
WPCE775
A A
PG 31
MDC
SPI Board HP MIC INT. INT.
JACK MIC SPEAKER Quanta Computer Inc.
Flash Touch
FAN
ROM Keyboard Pad
PG 28 PG 28 PG 28 PG 28 PROJECT : TE3
RJ11 Size Document Number Rev
PG 3 PG 32 PG 32 PG 32 BLOCK DIAGRAM 1A
NB4
Date: Tuesday, March 02, 2010 Sheet 1 of 43
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CLOCK GENERATOR CLOCKS name Discrete Clock pin function

NBGFX_CLKP RP48 STUFF to NB for VGA reference clock
NBGFX_CLKN
+1.1V L26 +1.1V_CLKVDDIO
HCB1608KF-181T15_1.5A EXT_GFX_CLKP RP47 STUFF to Park-S3 external reference clock -Discrete only
EXT_GFX_CLKN
C326 C345 C559 C324 C332 C556
10U/6.3V_8X 0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X
SBLINK_CLKP to NB for AC-LINK reference clock
SBLINK_CLKN RP43 STUFF
D D


600 ohm, 0.5A +3V_CLKVDD EMI
CLK_VGA_27M_SS R213,R215
+3V L28 +3V_CLKVDD CLK_VGA_27M_NSS STUFF To Park-S3 27Mhz - Discrete only
HCB1608KF-181T15_1.5A

C346 C340 C553 C561 C341 C325 C336 C323 C337 C555
10U/6.3V_8X 2.2U/6.3V_6X 0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X

Need check the net name for the short pad

R238 *261/F_4
U9

+3V_CLKVDD 4 50 CLK_CPU_BCLKP_R RP11 4 3 *short_4P2R
VDDDOT CPUK8_0T T63 CLK_CPU_BCLKP {3}
16 49 CLK_CPU_BCLKN_R 2 1 to CPU
VDDSRC CPUK8_0C T62 CLK_CPU_BCLKN {3}
26
VDDATIG
Place very 35
VDDSB
40 30 CLKP_NBGFX_R RP3 4 3 *short_4P2R CLKP_NBGFX {8} to NB
close to 48
VDD_SATA ATIG0T
29 CLKN_NBGFX_R 2 1
VDDCPU ATIG0C CLKN_NBGFX {8}
C/G 55
VDDHTT ATIG1T
28 CLK_PCIE_VGAP_R RP4 4 3 *0X2 CLK_PCIE_VGAP
+3V_CLKVDD 56 27 CLK_PCIE_VGAN_R 2 1
VDDREF ATIG1C CLK_PCIE_VGAN TO VGA CARD
L27 +3V_CLK_VDDA 63
HCB1608KF-181T15_1.5A VDD48
C352 37 CLK_SBLINKP_R RP8 4 3 *short_4P2R
SB_SRC0T CLKP_SBLINK {8}
C353 11 36 CLK_SBLINKN_R 2 1 EXTERNAL MODE to NB-AC-LINK
VDDSRC_IO SB_SRC0C CLKN_SBLINK {8}
2.2U/6.3V_6X 0.1U/10V_4X 17 32 CLK_SBSRCP_R RP2 4 3 *short_4P2R
VDDSRC_IO SB_SRC1T CLK_SBSRCP {10}
25 31 CLK_SBSRCN_R 2 1 EXTERNAL MODE to SB
VDDATIG_IO SB_SRC1C CLK_SBSRCN {10}
34
+1.1V_CLKVDDIO VDDSB_IO
47
C VDDCPU_IO 22 CLKP_NBGPP_R RP5 1 2 *0X2 C
SRC0T CLKP_NBGPP {8}
21 CLKN_NBGPP_R 3 4 Reserve ONLY
SRC0C CLKN_NBGPP {8}
1 20
C356 33P/50V_4N CG_XIN 7 GND48 SRC1T 19
GNDDOT SRC1C CLK_PCIE_WLANP_R RP6
10 15 4 3 *short_4P2R CLK_PCIE_WLANP {25}
GNDSRC SRC2T
2




18 14 CLK_PCIE_WLANN_R 2 1 to WLAN
GNDSRC SRC2C CLK_PCIE_WLANN {25}
Y2 CLK_PCIE_3G_R RP7 3 *short_4P2R
14.318MHZ_30
24
33 GNDATIG QFN64 SRC3T
13
12 CLK_PCIE_3G#_R
4
2 1
CLK_PCIE_3G {25}
GNDSB SRC3C CLK_PCIE_LAN_R RP9
CLK_PCIE_3G# {25} to 3G
43 9 4 3 *short_4P2R
1




GNDSATA SRC4T CLK_PCIE_LAN {29}
C357 33P/50V_4N CG_XOUT 46 8 CLK_PCIE_LAN#_R 2 1 to LAN
GNDCPU SRC4C CLK_PCIE_LAN# {29}
52 6 CLK_VGA_27M_SS R213 *0_4 27M_CLK
GNDHTT SRC7T/27M_SS CLK_VGA_27M_NSS R216 0_4 27M_CLK
60 5 XTAL_27M_TCK to VGA
GNDREF SRC7C/27M
42 T64
SRC6T/SATAT 41
SRC6C/SATAC 27Mhz for Dis only
CG_XIN 61
CG_XOUT X1
62
X2 NBHT_REFCLKP_R RP10
54 4 3 *short_4P2R NBHT_REFCLKP {8}
HTT0T/66M 53 NBHT_REFCLKN_R 2 1
HTT0C/66M NBHT_REFCLKN {8}
{11,15} PCLK_SMB 2
SMBCLK
{11,15} PDAT_SMB 3
SMBDAT
64 CLK48MUSB
B2A R220 *33/F_4
D3A
48MHz_0 CLK_48M_USB {11}
R223 33/F_4
48M_CARD {30}
CLK_PD# 51 EMI
PD# 59 SEL_HT66
REF0/SEL_HTT66 SEL_SATA
58
REF1/SEL_SATA SEL_27 R232 158/F_4
T140 23 57 EXT_NB_OSC {8}
CLKREQ4# *CLKREQ0# REF2/SEL_27
38
CLKREQ3# *CLKREQ4# R245 90.9/F_4 XTAL_27M_TCK 48M_CARD
39
CLKREQ2# *CLKREQ3#
44
*CLKREQ2# C390
B2A For EMI
T141 45
*CLKREQ1# C338
TGND


*10P/50V_4
B +3V B2A 15P/50V_4C
B
B2A
C347 15P/50V_4C CLK_48M_USB RTM880N-796_QFN64
65




R234 8.2K_4 CLK_PD#

R218 8.2K_4 CLKREQ2# WLAN
PCIE_CLK_RQ5# {25}
R212 8.2K_4 CLKREQ3# 3G
PCIE_CLK_REQ4# {25}
C339 *10P/50V_4 27M_CLK
R209 8.2K_4 CLKREQ4# LAN
PCIE_CLK_REQ3# {29}




Power Down Mode
+3V_CLKVDD 0--> Power Down
1--> Normal




R246 R436 R244
* default *8.2K_4 *8.2K_4 8.2K_4

66 MHz 3.3V single ended HTT clock SEL_27
1 SEL_HT66
SEL_HTT66 SEL_SATA
0* 100 MHz differential HTT clock

A 100 MHz non-spreading differential SRC clock R247 A
SEL_SATA 1 8.2K_4 R233 R231
8.2K_4 *8.2K_4
0* 100 MHz spreading differential SRC clock

SEL_27 1* 27MHz non-spreading singled clock

0 100 MHz spreading differential SRC clock Quanta Computer Inc.
PROJECT : TE3
Size Document Number Rev
1A
NB4
Clock Generator
Date: Thursday, March 04, 2010 Sheet 2 of 43
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PBY201209T-221Y-N_2A
S1G4 +2.5V +CPUVDDA
L25
+1.1V_VLDT C320 CPU_LDT_RST# 300/F_4 R423
+1.1V C319 LS0805-100M-N C305 C291 C301 CPU_PWRGD 300/F_4 R424
*100U/6.3V_3528P_E35b 4.7U/6.3V_6X 4.7U/6.3V_6X 0.22U/6.3V_4X 3300P/50V_4X CPU_LDT_REQ#_CPU 300/F_4 R197 +1.5V
R133 *short_6 CPU_LDT_STOP# *300/F_4 R195

R140 *short_6 +1.1V_VLDT +CPUVDDA B2A
U16D
U16A W/S= 15 mil/20mil
+CPUVDDA F8 M11 S1G4
+1.1V_VLDT +1.1V_VLDT 10U/6.3V_8X CLK_CPU_BCLKP_CR418 169/F_4CLK_CPU_BCLKN_C +CPUVDDA VDDA1 VSS
C126 10U/6.3V_8X D1
VLDT_A0
HT LINK VLDT_B0
AE2 C264 F9
VDDA2 RSVD11
W18
C254 10U/6.3V_8X +1.1V_VLDT D2 AE3 +1.1V_VLDT 0.22U/6.3V_4X C116
+1.1V_VLDT VLDT_A1 VLDT_B1 +1.1V_VLDT 180P/50V_4N CLK_CPU_BCLKP_C CPU_SVC_R
C242 0.22U/6.3V_4X D3 AE4 C118 C550 3900P/25V_4X A9 A6
VLDT_A2 VLDT_B2 {2} CLK_CPU_BCLKP CLKIN_H SVC
C114 180P/50V_4N +1.1V_VLDT D4 AE5 +1.1V_VLDT {2} CLK_CPU_BCLKN C549 3900P/25V_4X CLK_CPU_BCLKN_C A8 A4 CPU_SVD_R
VLDT_A3 VLDT_B3 CLKIN_L SVD
HT_CADINP0 E3 AD1 HT_CADOUTP0 CPU_LDT_RST# B7
HT_CADINN0 L0_CADIN_H0 L0_CADOUT_H0 HT_CADOUTN0 {8,10} CPU_LDT_RST# CPU_PWRGD RESET_L
E2 AC1 {10} CPU_PWRGD A7
HT_CADINP1 L0_CADIN_L0 L0_CADOUT_L0 HT_CADOUTP1 CPU_LDT_STOP#F10 PWROK CPU_THERMTRIP_L#
E1 AC2 AF6
D HT_CADINN1 L0_CADIN_H1 L0_CADOUT_H1 HT_CADOUTN1 {8,10} CPU_LDT_STOP# CPU_LDT_REQ#_CPU C6 LDTSTOP_L THERMTRIP_L CPU_PROCHOT_L# D
SI Change from AMD request F1 AC3 AC7