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ZZZ0 ZZZ1 ZZZ2 ZZZ3 ZZZ4 ZZZ5 PCB DAZ0I200101

MB DA60000KP10
PCB LA-7071P LS-7071P LS-7074P LS-7075P LA-7076P USB IO/B DA60000KQ10
M/B M/B USB IO/B HDD/B LED/B TP/B
DAZ@ DA@ DA@ DA@ DA@ DA@ HDD/B DA400011R10
LED/B DA400011T10
TP/B DA400013910
1 1




Compal Confidential
2
P1VE6 LA7071P Schematics Document 2




AMD Ontario Processor with DDRIII + Hudson M1

11.6" M/B

3

2011-03-17 3




Rev : 1.0



4 4




Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/11/09 Deciphered Date 2012/11/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P1VE6 Schematics
Date: Thursday, March 17, 2011 Sheet 1 of 37
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Compal Confidential
Model Name : P1VE6 Brazos Platform
File Name : LA-7071P
HDMI
1 AMD Memory Bus (DDRIII) 1

RGB
Dual Channel 204 Pin DDRIII SO-DIMM x2
LVDS Ontario FT1
APU 1.5V DDRIII 800/1066 BANK 0, 1, 2, 3
6.4G/8.5G
BGA 413-Ball Page 7 , 8
100M/133M
19mm X 19mm
Page 4,5,6


HDMI Conn. D-Sub Conn. LVDS Conn. UMI x4
Page 10 Page 11 Page 9
Gen.1 USB Conn.x2 USB Conn.x1 Camera Bluetooth Card Reader
(Left Side) (Right Side) RTS 5138
2.5GT/s Port 5 Port 7
Port 0 , 1 Port 2
per Lane IO/B Page 25 Page 9 Page 20
Port 6 Page 19
2
Fan Circuit 2

PWM Page 27 USB 3.3V 48MHz
PCI-Express X3 AMD
Hudson M1 HD Audio 3.3V 24MHz
100MHz PCIE Gen1 2.5GT/S FCH SATA 3G Card
Gen1 1.5GT/S ,Gen2 3GT/S 100MHz
Port 1 Port 3 Port 2 BGA 605-Ball Port 3, 9
23mm X 23mm Page 20
WWAN WLAN LAN(10/100) Page 12 ~ 16
JMINI1 JMINI2
AR8158 SIM Card
Media processor Wireless Card HDD
Port 1 Port 3 Port 2
Page 20 Page 21 Page 18
(2.5") Port 4
LPC Port 0 Page 20
Page 22
33MHz
3 3


RJ-45 WLAN
Page 18
Port 8
ENE KB930 Page 21
Page 26 Small Board

IO/B HDD/B HDA Codec+AMP
LS-7071P LS-7074P
CX20584
Page 17


RTC Ckt. LED/B TP BTN/B
Page 12 LS-7072P LS-7073P
BIOS ROM HP Jack x1
MIC Jack x1
4 2MB 4

Power Button Page 27 IO/B
Page 23


Security Classification Compal Secret Data Compal Electronics, Inc.
DC/DC Interface Ckt. Issued Date 2010/11/09 Deciphered Date 2012/11/09 Title

Page 28 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P1VE6 Schematics
Date: Thursday, March 17, 2011 Sheet 2 of 37
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Voltage Rails FCH Hudson-M1 Brazos FCH Hudson-M1
Power Plane Description S1 S3 S5 USB Port List PCIE Port List SATA Port List
VIN Adapter power supply (19V) N/A N/A N/A USB1.1 PCIE0 SATA0 HDD
B+ AC or battery power rail for power circuit. N/A N/A N/A
Port0 NC PCIE1 SATA1 NC




APU
+APU_CORE Core voltage for CPU (0.7-1.2V) ON OFF OFF
NC
+APU_CORE_NB 1.0V switched power rail ON OFF OFF Port1 NC PCIE2 SATA2 NC
1 1
+1.5V 1.5V power rail for CPU VDDIO and DDRIII ON ON OFF
USB2.0 PCIE3 SATA3 NC
+0.75VS 0.75VS switched power rail for DDR terminator ON OFF OFF
+1.05VS 1.05V switched power rail for NB VDDC & VGA ON OFF OFF Port0 Left conn PCIE0 NC SATA4 NC
+1.1VS 1.1VS switched power rail ON OFF OFF
Port1 Left conn PCIE1 WWAN SATA5 NC




FCH
+1.8VS 1.8V switched power rail ON OFF OFF
+3VALW 3.3V always on power rail ON ON ON* Port2 Right conn PCIE2 LAN
+1.1VALW 1.1V always on power rail ON ON ON*
Port3 WWAN PCIE3 WLAN
+3VS 3.3V switched power rail ON OFF OFF
+1.5VS 1.5VS switched power rail ON OFF OFF Port4 SIM
+5VALW 5V always on power rail ON ON ON*
Port5 USB Camera
+5VS 5V switched power rail ON OFF OFF
+VSB VSB always on power rail ON ON ON* Port6 CardReader
+RTCBATT RTC power ON ON ON
Port7 BT
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Port8 WiMax

2 Port9 WWAN 2
EC SM Bus1 address EC SM Bus2 address
Port10 NC
Device Address HEX Device Address HEX
Smart Battery 0001-011xb 16H SB-TSI 1001-100xb 98H
Port11 NC
Port12 NC
Port13 NC

SM Bus Controller 0 (FCH_SMB1 ~ FCH_SMB4, SMB_ALERT#) Board ID / SKU ID Table for AD channel
Vcc +3VALW
Device Address HEX
Ra 100K +/- 5%
APU SIC/SID (FCH_SMB3) Board ID Rb V AD_BID min V AD_BID typ V AD_BID max PCB Revision
H_THERMTRIP# (FCH_ALERT#) 0 0 0 V 0 V 0 V
* 0.1
1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V 0.2
2 18K +/- 5% 0.436 V 0.503 V 0.538 V
3 33K +/- 5% 0.712 V 0.819 V 0.875 V
3
SM Bus Controller 1 (FCH_SMB0) 4 56K +/- 5% 1.036 V 1.185 V 1.264 V 3


5 100K +/- 5% 1.453 V 1.650 V 1.759 V
Device Address HEX
6 200K +/- 5% 1.935 V 2.200 V 2.341 V
DDR DIMM1 (FCH_SMB0) 1001-000xb 90 7 NC 2.500 V 3.300 V 3.300 V

SMBUS Control Table
BOM Structure Source BATT DIMM MINI Card LCD DDC ROM HDMI DDC ROM APU
EC_SMB_CK1 KB930
EC_SMB_DA1 V
HDMI@ : HDMI function
EC_SMB_CK2 KB930
BT@ : BT function EC_SMB_DA2 V
CONN@ : Connetors
HDMI_DATA APU FT1
45@ : 45 Level HDMI_CLK V
3G@ : 3G function
EDID_DATA APU FT1
N3G@ : None 3G function EDID_CLK V
4 4
CMBS@ : Combo Jack POPO noise Solution
FCH_SMDAT0 FCH M1
NCMBS@: None Combo Jack POPO noise Solution FCH_SMCLK0 V V

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/11/09 Deciphered Date 2012/11/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P1VE6 Schematics
Date: Thursday, March 17, 2011 Sheet 3 of 37
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APU C50 P/N change to SA00004KD50 R9 R352 Display
Tock 2010/12/30
mount @ LVDS
SA00004KD50 *
U1B @ mount eDP
APU_SVD
+1.8VS C1 .1U_0402_16V7K HDMI_TX2P_C DP_ZVSS R1 2 150_0402_1%




DISPLAYPORT 1
<10> HDMI_TX2P 1 2 A8 TDP1_TXP0 DP_ZVSS H3 1
@ C6 .1U_0402_16V7K HDMI_TX2N_C




DP MISC
1 <10> HDMI_TX2N 1 2 B8
TDP1_TXN0
DP_BLON G2 APU_ENBKL <26>
C433 C2 1 2 .1U_0402_16V7K HDMI_TX1P_C B9 H2
<10> HDMI_TX1P TDP1_TXP1 DP_DIGON APU_ENVDD <9>
100P_0402_50V8J C3 1 2 .1U_0402_16V7K HDMI_TX1N_C A9 H1
D APU_SVC 2 <10> HDMI_TX1N TDP1_TXN1 DP_VARY_BL APU_BLPWM <9> D
R3 1 2 1K_0402_5%
R4 1 2 1K_0402_5% APU_SVD C7 1 2 .1U_0402_16V7K HDMI_TX0P_C D10
<10> HDMI_TX0P HDMI_TX0N_C TDP1_TXP2 HDMI_CLK
C8 1 2 .1U_0402_16V7K C10 B2
<10> HDMI_TX0N TDP1_TXN2 TDP1_AUXP HDMI_CLK <10>
C2 HDMI_DATA HDMI_DATA <10>
R8 TEST_25_L APU_SVC HDMI_CLKP_C TDP1_AUXN
1 2 510_0402_1% <10> HDMI_CLKP
C4 1 2 .1U_0402_16V7K A10 8/25 Pull-up 100k(@ R352) to +3VS
R6 TEST36 HDMI_CLKN_C TDP1_TXP3
1 2 1K_0402_5% <10> HDMI_CLKN
C5 1 2 .1U_0402_16V7K B10 C1 HDMI_DET <10>
@ 1
TDP1_TXN3 TDP1_HPD on LTDP0_HPD for eDP
+3VS B5 A3 EDID_CLK
<9> LVDS_A2 LTDP0_TXP0 LTDP0_AUXP EDID_CLK <9>
C432 EDID_DATA R352 1 @ 2 100K_0402_5%




DISPLAYPORT 0
<9> LVDS_A2# A5 LTDP0_TXN0 LTDP0_AUXN B3 EDID_DATA <9> +3VS
R10 1 2 10K_0402_5% HDMI_DATA 100P_0402_50V8J
R11 HDMI_CLK 2 LTDP0_HPD
1 2 10K_0402_5% <9> LVDS_A1 D6 LTDP0_TXP1 LTDP0_HPD D3 R9 1 2 100K_0402_5%
Reserve C432, C433, C434, C435 <9> LVDS_A1# C6
LTDP0_TXN1
Michael 2010/11/18 C12 eDP@
DAC_RED DAC_RED <11>
R13 1 2 1K_0402_5% APU_PROCHOT# A6 D13 R12 1 2 150_0402_1% R389 1 2 0_0402_5% DMIC_CLK
APU_ALERT#_R APU_SID <9> LVDS_A0 LTDP0_TXP2 DAC_REDB DMIC_CLK <9,17>
R14 1 2 1K_0402_5% B6 A12
<9> LVDS_A0# LTDP0_TXN2 DAC_GREEN DAC_GRN <11>
R16 1 2 1K_0402_5% APU_SIC B12 R15 1 2 150_0402_1%
APU_SID DAC_GREENB
R17 1 2 1K_0402_5% @ D8 A13 Reserve R389 for eDP function




VGA DAC
1 <9> LVDS_ACLK LTDP0_TXP3 DAC_BLUE DAC_BLU <11>
C8 B13 R18 1 2 150_0402_1% Tock 2010/12/30
<9> LVDS_ACLK# LTDP0_TXN3 DAC_BLUEB
C435
Change R10, R11 to RP1 100P_0402_50V8J <12> APU_CLK V2 E1 CRT_HSYNC <11>
2 CLKIN_H DAC_HSYNC
Michael 2010/12/23 <12> APU_CLK# V1
CLKIN_L DAC_VSYNC
E2 CRT_VSYNC <11>




CLK
<12> DISP_CLK D2 DISP_CLKIN_H DAC_SCL F2 CRT_DDC_CLK <11>
<12> DISP_CLK# D1 DISP_CLKIN_L DAC_SDA D4 CRT_DDC_DATA <11>
C405 1 2 100P_0402_50V8J LDT_RST# J1 D12 DAC_ZVSS R19 1 2 499_0402_1%
<36> APU_SVC SVC DAC_ZVSS
Power Circuit <36> APU_SVD
J2
SVD




SER
10/05 Add 100p(C405) on LDT_RST# APU_SIC TEST4
R1

APU_SID
P3 SIC TEST5 R2 10/01 Remove T1,T3~T7,T11,T12,T31,T32
APU_SIC
9/9 Change R24 from @ to mount R26 from mount to @ P4 SID TEST6 R6
T5
TEST14 TEST15 R20
9/15 Change R24 from mount to @ <12> LDT_RST# T3 E4 1 2 1K_0402_5%
C @ RESET_L TEST15 C
1 <12> APU_PWRGD T4 K4




CTRL
PWROK TEST16
L1
C434 APU_PROCHOT# TEST17 TEST18 R21
U1 L2 1 2 1K_0402_5%
APU_PROCHOT# APU_THERMTRIP# U2 PROCHOT_L TEST18 TEST19 R22
100P_0402_50V8J M2 1 2 1K_0402_5%




TEST
@ 2 R24 1 @ APU_ALERT#_R T2 THERMTRIP_L TEST19 TEST25_H
1 <14> APU_ALERT#_FCH 2 0_0402_5% ALERT_L TEST25_H K1 R25 1 2 510_0402_1%
R26 1 @ 2 0_0402_5% K2 TEST_25_L
<26> APU_ALERT#_EC TEST25_L
C429 APU_TDI N2 L5
APU_TDO TDI TEST28_H
100P_0402_50V8J Connection to EC, FCH input need to pull-down N1
TDO TEST28_L
M5
2 APU_TCK TEST31
P1 TCK TEST31 M21 PAD T8




JTAG
Add C429 for APU_PROCHOT# APU_TMS P2 J18 TEST33_H C9 1 2 0.1U_0402_16V4Z R28 1 2 51_0402_1%
APU_TRST# TMS TEST33_H TEST33_L C10 1
Michael 2010/11/18 M4 TRST_L TEST33_L J19 2 0.1U_0402_16V4Z R29 1 2 51_0402_1%
APU_DBRDY M3 U15
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