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5 4 3 2 1
TERESA20 Main BD. R2.0 BLOCK DIAGRAM
BATTERY CLOCK GEN.
1 TYPE ICS9LPR363CGLF-T
3 X 2 PAGE 5
D D
Merom CPU FAN + Thermal sensor
PAGE 4
478B uFCPGA
PAGE 2,3 DISCHARGER CIRCUIT
PAGE 37
FSB 800 MHz
LVDS
Power On Sequence
PAGE 12
PAGE 40
CRT CRESTLINE DDRII
DDR2 667MHz DC/BATT IN
PAGE 13
965GM SO-DIMM X 2 PAGE 41
PAGE 14,15,16
1299 FCBGA
CPU VCORE
PAGE 6,7,8,9,10,11
C C
DMI *4 MiniCard PAGE 80
WLAN Conn. SYSTEM PWR
PCIE *4 PAGE 26
SPEAK Azalia PAGE 81
MDC
PAGE 22
PAGE 35 ICH8-M New Card
AUDIO AMP
Conn
PAGE 25
ALC660 POWER
G1420
PCI*2
PAGE 22 PAGE 21 LPC 10/100 LAN
RTL8100CL VCORE
652 BGA PAGE 80
PAGE 34,35
Head EXT PAGE 17,18,19,20
SYSTEM
MIC PAGE 81
Phone Card
B PAGE 22 PAGE 22 CardBus Reader IO_1.5VS_1.05VS B
RICOH R5C847 PAGE 33 PAGE 82
PAGE 43, 44
SATA Bus
IO_DDR_VTT
IDE Bus
PAGE 83
CardBus
T/P IO_1.25VS
PAGE 44 PAGE 84
USB2.0 Bus USB X3
PAGE 30 SHUTDOWN
PAGE 87
KB EC PAGE 36
PAGE 29 CHARGER
INSTANT KEY
ITE8511 PAGE 88
PAGE 38 SATA DETECT
PAGE 90
LED Control HDD
PAGE 30,38
PAGE 28 LOAD SWITCH
PAGE 91
PAGE 29,30
A A
ODD
PROTECT
ISA ROM Slave PAGE 92
PAGE 24 PAGE 28 Title : BLOCK DIAGRAM
ASUSALPHATeK COMPUTER INC. Engineer: Julian Kuo
Size Project Name Rev
Custom TERESA20 2.0
Date: Thursday, July 05, 2007 Sheet 1 of 66
5 4 3 2 1
PDF "pdfFactory Pro" www.ahasoft.com.tw/FinePrint/
5 4 3 2 1
H_D#[63:0]
6 H_D#[63:0]
H_A#[35:3]
6 H_A#[35:3]
D D
H_REQ#[4:0]
6 H_REQ#[4:0]
1 T0218 TPC26T
1 T0219 TPC26T
U0201A U0201B
H_A#3 J4 H1 H_D#0 E22 Y22 H_D#32
A[3]# ADS# H_ADS# 6 D[0]# D[32]#
ADDR GROUP 0
H_A#4 L5 E2 H_D#1 F24 AB24 H_D#33
A[4]# BNR# H_BNR# 6 D[1]# D[33]#
H_A#5 L4 G5 H_D#2 E26 V24 H_D#34
A[5]# BPRI# H_BPRI# 6 D[2]# D[34]#
H_A#6 K5 H_D#3 G22 V26 H_D#35
A[6]# D[3]# D[35]#
DATA GRP 0
H_A#7 M3 H5 H_D#4 F23 V23 H_D#36
A[7]# DEFER# H_DEFER# 6 D[4]# D[36]#
H_A#8 N2 F21 H_D#5 G25 T22 H_D#37
A[8]# DRDY# H_DRDY# 6 D[5]# D[37]#
H_A#9 J1 E1 H_D#6 E25 U25 H_D#38
A[9]# DBSY# H_DBSY# 6 D[6]# D[38]#
H_A#10 N3 H_D#7 E23 U23 H_D#39
H_A#11 A[10]# H_D#8 D[7]# D[39]# H_D#40
P5 F1 H_BR0# 6 K24 Y25
DATA GRP 2
H_A#12 A[11]# BR0# H_D#9 D[8]# D[40]# H_D#41
P2 G24 W22
A[12]# D[9]# D[41]#
CONTROL
H_A#13 L2 D20 H_IERR# R0209 56Ohm +VCCP_CPU H_D#10 J24 Y23 H_D#42
H_A#14 A[13]# IERR# H_D#11 D[10]# D[42]# H_D#43
P4 B3 H_INIT# 17 J23 W24
H_A#15 A[14]# INIT# H_D#12 D[11]# D[43]# H_D#44
P1 H22 W25
H_A#16 A[15]# H_D#13 D[12]# D[44]# H_D#45
R1 H4 H_LOCK# 6 F26 AA23
A[16]# LOCK# H_D#14 D[13]# D[45]# H_D#46
6 H_ADSTB#0 M1 K22 AA24
ADSTB[0]# H_D#15 D[14]# D[46]# H_D#47
C1 H_CPURST# 6 H23 AB25
H_REQ#0 RESET# D[15]# D[47]#
K3 F3 H_RS#0 6 6 H_DSTBN#0 J26 Y26 H_DSTBN#2 6
H_REQ#1 REQ[0]# RS[0]# DSTBN[0]# DSTBN[2]#
H2 F4 H_RS#1 6 6 H_DSTBP#0 H26 AA26 H_DSTBP#2 6
H_REQ#2 REQ[1]# RS[1]# DSTBP[0]# DSTBP[2]#
K2 G3 H_RS#2 6 6 H_DINV#0 H25 U22 H_DINV#2 6
H_REQ#3 REQ[2]# RS[2]# DINV[0]# DINV[2]#
J3 G2 H_TRDY# 6
H_REQ#4 REQ[3]# TRDY#
C L1 C
REQ[4]# H_D#16 H_D#48
G6 H_HIT# 6 N22 AE24
H_A#17 HIT# H_D#17 D[16]# D[48]# H_D#49
Y2 E4 H_HITM# 6 K25 AD24
H_A#18 A[17]# HITM# H_D#18 D[17]# D[49]# H_D#50
U5 P26 AA21
H_A#19 A[18]# T0222 TPC26T H_D#19 D[18]# D[50]# H_D#51
R3 AD4 1 R23 AB22
A[19]# BPM[0]# D[19]# D[51]#
ADDR GROUP 1
H_A#20 W6 AD3 XDP_BPM#1 H_D#20 L23 AB21 H_D#52
A[20]# BPM[1]# D[20]# D[52]#
DATA GRP 1
H_A#21 U4 AD1 1 T0223 TPC26T H_D#21 M24 AC26 H_D#53
A[21]# BPM[2]# D[21]# D[53]#
XDP/ITP SIGNALS
H_A#22 Y5 AC4 1 T0224 TPC26T H_D#22 L22 AD20 H_D#54
H_A#23 A[22]# BPM[3]# T0225 TPC26T H_D#23 D[22]# D[54]# H_D#55
U1 AC2 1 M23 AE22
H_A#24 A[23]# PRDY# H_PREQ# H_D#24 D[23]# D[55]# H_D#56
R4 AC1 P25 AF23
H_A#25 A[24]# PREQ# H_TCK T0233 TPC26T H_D#25 D[24]# D[56]# H_D#57
T5 AC5 1 P23 AC25
H_A#26 A[25]# TCK H_TDI T0232 TPC26T +VCCP_CPU H_D#26 D[25]# D[57]# H_D#58 Comp0,2 connect with Zo=27.4 ohm,
T3 AA6 1 P22 AE21
DATA GRP 3
H_A#27 A[26]# TDI H_TDO T0231 TPC26T H_D#27 D[26]# D[58]# H_D#59 make trace length shorter than 0.5".
W2 AB3 1 T24 AD21
H_A#28 A[27]# TDO H_TMS T0230 TPC26T H_D#28 D[27]# D[59]# H_D#60
W5 AB5 1 R24 AC22 Comp 1,3 connect with Z0=55 ohm,
H_A#29 A[28]# TMS H_TRST# T0229 TPC26T H_D#29 D[28]# D[60]# H_D#61
Y4 AB6 1 L25 AD23 make trace length shorter than 0.5".
A[29]# TRST# D[29]# D[61]#
2
H_A#30 U2 C20 CPU_DBR# H_D#30 T25 AF22 H_D#62
H_A#31 A[30]# DBR# R0215 H_D#31 D[30]# D[62]# H_D#63
V4 N25 AC23
H_A#32 A[31]# 1KOhm D[31]# D[63]#
W3 6 H_DSTBN#1 L26 AE25 H_DSTBN#3 6
H_A#33 A[32]# 1% DSTBN[1]# DSTBN[3]#
AA4
A[33]#
THERMAL 6 H_DSTBP#1 M26
DSTBP[1]# DSTBP[3]#
AF24 H_DSTBP#3 6
H_A#34 AB2 N24 AC20
6 H_DINV#1 H_DINV#3 6
1
H_A#35 A[34]# H_PROCHOT_S# DINV[1]# DINV[3]#
AA3 D21
A[35]# PROCHOT# GTL_REF H_COMP0 R0211 27.4Ohm 1%
6 H_ADSTB#1 V1 A24 CPU_THRM_DA 4 AD26 R26 1 2
T0220 ADSTB[1]# THRMDA R0217 2 @ 1% 1 1KOhm test1 GTLREF COMP[0] H_COMP1 R0212 54.9Ohm 1%
1
THRMDC
B25 CPU_THRM_DC 4 C23
TEST1 MISC COMP[1]
U26 1 2
2
TPC26T A6 R0218 2 @ 1% 1 1KOhm test2 D25 AA1 H_COMP2 R0213 1 2 27.4Ohm 1%
17 H_A20M# A20M# TEST2 COMP[2]
1
ICH
ICH
A5 C7 C0201 R0216 TPC26T T0228 1 C24 Y1 H_COMP3 R0214 1 2 54.9Ohm 1%
17 H_FERR# FERR# THERMTRIP# PM_THRMTRIP# 4,17 TEST3 COMP[3]
C4 0.1UF/10V 2KOhm TPC26T T0205 1 AF26
17 H_IGNNE# IGNNE# TEST4
T0221 1 X7R 1% TPC26T T0206 1 AF1 E5 H_DPRSTP# 7,17,50
2
T0226 TPC26T TPC26T T0238 TEST5 DPRSTP# GND
17 H_STPCLK# TPC26T D5 1 1 A26 B5 H_DPSLP# 17
1
STPCLK# TEST6 DPSLP#
17 H_INTR C6
LINT0
H CLK DPWR#
D24 H_DPWR# 6
17 H_NMI B4 A22 CLK_CPU_BCLK 5 5 CPU_BSEL0 B22 D6 H_PWRGD 17
B LINT1 BCLK[0] GND GND GND BSEL[0] PWRGOOD B
17 H_SMI# A3 A21 CLK_CPU_BCLK# 5 5 CPU_BSEL1 B23 D7 H_CPUSLP# 6
SMI# BCLK[1] BSEL[1] SLP#
5 CPU_BSEL2 C21 AE6 PM_PSI# 50
TPC26T T0208 BSEL[2] PSI#
1 M4
TPC26T T0209 RSVD1 T0227 TPC26T Zo=55 ohm, 0.5" max SOCKET478B
1 N5 1
TPC26T T0210 RSVD2 for GTLREF TPC26T T0239 test1
1 T2 1
TPC26T T0211 RSVD3 TPC26T T0240 test2
1 V3 1
RSVD4
RESERVED
TPC26T T0212 1 B2 H_COMP0 1 T0234 TPC26T
TPC26T T0213 RSVD5 H_COMP1 T0235 TPC26T
1 C3
RSVD6 07/03/26 Add test point T0228 on TEST3---Feng 1
TPC26T T0214 1 D2 H_COMP2 1 T0236 TPC26T
TPC26T T0215 RSVD7 H_COMP3 T0237 TPC26T
1 D22 1
TPC26T T0216 RSVD8
1 D3
TPC26T T0217 RSVD9
1 F6 Default Strapping When Not Used
RSVD10
+VCCP_CPU