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Block diagrams CDR 3rd gen. 6. GB 33
6. Block diagrams
CDR MAIN BOARD BLOCK DIAGRAM
7330
D3V3
CDL4009
UCOIL, VCOIL, WCOIL, U+, U-, V+, V-, W+, W-, HALL+, HALL- HALL HALL U, HALL V, HALL W
+5VA
LOADER ASSY MOTOR 7703 D5V
FORWARD SENSE CIRCUIT 7126C 7050A, 7050B DRIVER MOTO1 FLASH
D5VS
7119, 7120 BA6856FP L5V 1500
FSW 7300 ADDRESS ROM L-5V
+5V
BUS POWER
CDM3800 7126D CDR60 DATA
-8VA
A-8V
PART
-8V
FSR SAA7392
SYST CLK BUS +12V
TURN 1330 GENERATOR 7702 +9SRVPWR
TO MACE2 (PCS) OFFTRACK MOTOR/TACHO +12VA VDC2, VDC1, VFTD
TABLE FSON
FSOF RDGAIN FSCLR FSWS FSRS 7008 INTERFACE CDR60PLL DRAM L12V
M EFMTIM3 LWRT CDR60LWRT
FROM MACE2 P12V
LWRT MODULATOR 12VPWR
LO9805
LLP CONTROL FS30V
D3V3
DECODER EBU 7701
POR E5V
EPONRC A1 - A20 D16 - D31
WPONRC EFMDATA EFM ENCODER
TIMING DOBM-CDR 7704
LDON MODULATOR
I/O SHIFT N EFMDATA, EFMCLK EBU-IN1
BIASC
N-1, N+1
RESET
ERON REG ERROR D3V3
RECORDING
EFMCLK EFM CLOCK CORRECTION I2S I2S BUS MC33464
I2S1 MASTER
1000 CDRW GENERATOR AND MEMORY I/O RESET
ALS I2C PROCESSOR 7710 F934
ASTROBE
FSA ATIPSYNC
AINTON DP4 ERASEC PERASE PWRITE
WOBBLE RESET D5V
PROCESSOR SUB- SUBCODE BUS MC33464
7016 WOBBLE
CODE D5V
I/O
IE I-ERASE XDAC CD TEXT SYS-RESET
PWD M62364 BIT
DEMODULATOR
DAC DAC DETECTOR I2C BUS
EPONRC
IW I-WRITE PWB
PWD DAC HF DATA RESET SUB - CPU INTERFACE INT-COPY-ANA
CAPTURE
PWD
DAC 7801 NOT FOR CDR950/951
DELTAP HIN SRSTN CDR60CS MRDN
MWRN 7401
WPONRC S2V9 LASDACDI ALE DIGITAL EXT-ANA-IN
DAC 12 7360
LDON
I-READ PRCOARSE LASDACCK
LASDACLD
POT CD-ANA-OUT
IR BIASC BIT HFS0 DS1807
HF AMP
PRFINE S2V9 SHIFT
FILTER
DAC REGISTER
RECORDING SEL-HP-OUT NOT FOR CDR570/930
MODULATOR
CDRW
PW PWB
S2V9
DASP 1410
DAC MCF5244 7407 7408
PWMIN 7405 ANA-OUT
FS LASER P CAHF
DALPHA
+ MIN/MAX
CONTR
S2V9
DAC
FROM CDM3800
(PDAR) DIGITAL AUDIO
PWMAX
SIGNAL
ANALOG
FS30V PROCESSOR IN
CD-ANA-OUT
7406
NMUTE
7207
SYS-CLK-11W 7409
PDAR 2 CODEC
I 2C
ANALOG
I C BUS UDA1341TS OUT 1400
ERON ALS
I2S BUS
+ CAHF TO CDR60
(HF DATA CAPTURE)
RECORDING ASTROBE
AINTON
DALPHA OFFTRACK
EEPROM
M24C08
I2S2 / I2S4
ADC / DAC
DATA L3 BUS
PHOTO 7010 BUS
DIODES
AEGER I2C
LLP
EBU-IN2
EXT-DIG-IN
B1 B2 TZA1020 ATIPSYNC
DIG-OUT-C
CDR60INT EBU-OUT1
C3 C4 DIODE RECORDING ALPHA ALPHA0
C1LF - C4LF PW 7270 EXT-OPT-IN
STAGE DETECTOR EBU-IN3
C1 C2
2 BETA A1, A2, CALF
A1LF, A2LF DETECTOR
B1LF, B2LF
DIODE OPC PORT CDR775 ONLY
A1 A2 MUTE, ATT, DEEMP SYS-RESET
STAGE 7050C REGISTERS
S2V9
1 ERON
WOBBLE DSA-CD
BALANCE BE-RESET
S2V9
GAP TLN, MIRN LASER
NORMA- FEN, REN I2S BUS-CD
REF CONTROL
RAD+, RAD- LIZER I2S1-MS I2S3
RADIAL FOC+, FOC-
RECORDING DOBM-CD
FOCUS EBU-IN4
1708
+/- RE 8051 DSA-CDR
I V CPU SYS-CLK-16W (16.9344 Mhz)
XTRIM
REGISTERS
CDR60PLL
TO CDR60
PORT
1707
7215A
7225 FTCH, FTCL TRACK RAM ROM 33.8688 MHz
SLEDGE 1220 PCS PRE-AMP COUNTER
SIN+, SIN- NE532D
COS+, COS- FROM FORWARD
SENSE CIRCUIT
M SL+, SL-
FSR, FSW
SPECIAL FUNCTION
REGISTERS 7802 7208 7209
PCS
FLASH 7706A
REFSIN, SINPHI, REFCOS, COSPHI RAM DEMUX
POWER 7240 EPROM
DRIVER RAD /2 SYS-CLK-8W (8.4672 Mhz)
BA5938FM
FOCUS VRA, VFO, VSL SERVO
MACE2 74F74D
SAA7399 ADDRESS
CONTROLS SYS-CLK-BE
TRAY SLEDGE BUS (8.4672 Mhz)
M 1200
TR+, TR- TRAY TRAYIN, TRAYOUT
PORT 5
ADC
CLOCK
TRAY TRAYSW TRAYSWF
AGC TEST DEBUG
GEN
PORT 4 REF
SWITCH
CL06532018_025.eps
290200
Electrical diagrams and PWB's CDR 3rd gen. 7. GB 34
7. Electrical diagrams and PWB's
CDR-Mainboard Version 4228.5
CDR MAIN BOARD - CIRCUIT DIAGRAM 1 : AEGER, EFMTIM, FORWARD SENSE CIRCUIT TESTPOINTS
1 2 3 4 5 6 7 8 9 10 11 12 13 14
ACTUATOR BUS ACTUATOR BUS {RAD+,FOC+,FOC-,RAD-} 1000 G1 F110 C11
2001 F1 F113 C12
CAHF CAHF
2002 D2 F115 C12
I2CBUS I2CBUS {I2CSDA,I2CSCL} 2007 H4 F133 B7
2008 I4 F138 B8
DALPHA DALPHA 2009 H4 F140 B10
2010 G4 F142 B9
FSA
F147 2011 C2 F143 B6
L5V L5V {FSW,FSR} 2012 E3 F145 C3
2013 B5 F146 C8
A