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01
Intel
JE5.1 Block Diagram
Prescott
A
478 PIN mPGA MBX-126 A
D D R VRAM System bus
533MHz
16M B X 4
R/G/B ATI
CRT
RADEON 9200 NORTH BRIDGE DRAM SIGNAL
LVDS SIGNAL AGP bus
LCD (M9+X) DDR 266
ATI RS200M+ DDR CLOCK SO-DIMM 1/2
TV SIGNAL
AVOUT
PCI bus
B B
TI-PPCI7420B Mini PCI Realtek NEC RTC
TIBQ3285LF
(SN0307009B) (Wirless LAN) RTL8100CL UPD720101
South Bridge
ALI 1535+
USB 2.0
Memory PCMCIA RJ45 USB*3
SECONDARY IDE BUS
PRIMARY IDE BUS
Stick Slot0 1394
AC LINK1 AC LINK2
XBUS
C
ALC203 MDC C
PCU
LPT
NS PC87570
CDROM HDD
EXT.MIC. TPA0312 RJ11
TOUCH INT.K/B BIOS
DC JACK PAD
EXT.SPKR. INT.SPKR.
MAIN POWER BOARD T/P SWITCH POWER SWITCH Power LED
PWS-39 T/P BOARD Bettery LED K/B LED
D
SWX-169 Power SW BOARD D
BATTERY
SWX-168
QUANTA
COMPUTER
S ize D o c u m e n t N u mb e r R ev
Level 1 environment-related substances should NEVER be used. JE 5.1 M ain B oard 1A
Molding resin, ink, paint and covered wiring material should be procured from the supplier approved as a Sony's green partner.
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02
Page List
01 Block Diagram
A
02 Page List A
03 Prescott CPU-1
04 Prescott CPU-2
05 RS200M-AGTL+
06 RS200M-DDR I/F
07 RS200M-PCI & AGP I/F
08 RS200M-VIDEO I/F & CLKGEN
09 SYSTEM CONFIGURATION
10 DDR Terminator
11 DDR SODIMMx2
12 CRT PORT/TV
13 ALI M1535+ (PCI,ISA)-1/2
B 14 ALI M1535+ (IDE)-2/2 B
15 USB2.0 Controller (NEC-uPD720101)
16 ATI M9+ 1/3
17 ATI M9+ 2/3
18 ATI M9+ 3/3
19 VGA DDR VRAMX2 1/2
20 VGA DDR VRAMX2 2/2
21 AGP SSC
22 TI7420-A (CARDBUS+1394+MS)
23 TI7420-B (CARDBUS+1394+MS)
24 Cardbus slot
25 LAN interface RTL8100CL
C C
26 MiniPCI & MDC
27 RTC/POWER GOOD LOGIC
28 IDE/HDD/LPT Connector
29 PCU NS 87570
30 Int. Keyboard/Bios/FAN
31 VCORE POWER 1
32 MAX1546(VCORE POWER 2)
33 MAX1632(5V/3V/12V)
34 MAX1844(2.5V/1.8V/1.25V )
35 MAX1844(VCC1.5)
36 Load Switch
D D
QUANTA
T itle
COMPUTER
COVER PAGE
S ize D o c u m e n t N u mb e r R ev
Level 1 environment-related substances should NEVER be used. B 1A
Molding resin, ink, paint and covered wiring material should be procured from the supplier approved as a Sony's green partner.
JE5.1 Main Board
D a t e : T u e s d a y , A u g u st 3 1 , 2 0 0 4 S heet 2 of 36
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5 H A [3 ..3 1]
H A [3 .. 31] U 1A
Z I F _ S OCK E T 4 7 9
C1
1 2
V C C3
U2 *T C 7 S H 0 8FU V CORE
03
5
H A3 K2 C6 -H A20M 0 .1 U
H A4 A#3 A20M - H FE RR D1 -A 2 0 M
K4 B6 1 -A 2 0 M 13
H A5 L6 A#4 FERR W5 - HC P UI NIT -H A20M 2 1 4 - S MI R1 1 2 2 00
H A6 A#5 INIT IN TR K GA 2 0 V C ORE
K1 D1 I N T R 13 2 K GA 2 0 29
A#6 LINT0 R2
H A7 L3 E5 N MI
N M I 13 *RB 5 00 - S T P CL K 1 2 2 00 R P1
H A8 A#7 LINT1 - IG NNE HT E S T 1
M6 B2 - I G N N E 13 1 2
3
A#8 IGNNE R4 0 R3
H A9 L2 B5 - S MI
- S MI 14
- SLP 1 2 2 00 HT E S T 9 3 4
2
HA 10 A#9 SMI - SLP C2
M3 AB26 -S L P 14 2 1 5 6
A#10 SLP R5
HA 11 M4 Y4 - S T P CL K
- S T P CL K 14
P W R GD_CP U 1 2 2 00 HT E S T 1 0 7 8
HA 12 A#11 STPCLK 0 .1 U
A N1 A
1
A#12 R6
HA 13 M1 G1 -HA DS
-HA DS 5
- IE RR 1 2 1K 56X4
HA 14 A#13 ADS - HA _ S T B 0 V CC3 R P2
N2 L5 - HA _ S T B 0 5
HA 15 A#14 ADSTB0 - HA _ S T B 1 4 . 7 U / 1 0 V /Y 5 V V C C3 - TRIP R7
N4 R5 - HA _ S T B 1 5 1 2 5 6 _1% -H A20M 1 2
HA 16 A#15 ADSTB1 - H B NR C6 NMI
N5 G2 - H B NR 5 1 2 3 4
2
A#16 BNR R8
HA 17 T1 H5 - HDB S Y
- HDB S Y 5
- H B R E Q0 1 2 5 1 .1_1% - IG NNE 5 6 C3
2
HA 18 A#17 DBSY - HDE FE R IN TR
R2 E2 - HDE FE R 5 1 2 7 8
A#18 DEFER R15 R9
HA 19 P3 H2 -HDRDY
-HDRDY 5
CLOSE TO CPU -CP UR ST 1 2 5 6 0_1% 0 .1 U
1
HA 20 A#19 DRDY - HHIT 0 .1 U C7 2 0 0 x4
P4 F3 -HHIT 5 1K
A#20 HIT R 10
HA 21 R3 E3 -HHI TM
-HHITM 5
I T P _ CL K + 1 2 1K R P3
HA 22 A#21 HITM - H TRDY U3 HT E S T 8
T2 J6 - H TRDY 5 1 2
1
5
HA 23 A#22 TRDY -HB P RI HT E S T 3
U1 D2 -HB P RI 5 3 4
2
HA 24 A#23 BPRI - H B R E Q0 D2 -CP UINIT HT E S T 2 C4
P6 H6 - H B R E Q0 5 1 - C P U I N I T 13 5 6
HA 25 A#24 BR0 -HL OCK - HCP UINIT I T P _ CL K - R 12
U3 G4 -HL OCK 5 2 4
1 1 2 1K 7 8
HA 26 A#25 LOCK - RC 0 .1 U
T4 2 -RC 29
1
A#26 R 13
HA 27 V2 J1 -HRE Q0
-HRE Q0 5 R B 500 T DI 1 2 1 50 56X4
HA 28 A#27 REQ0 -HRE Q1 T C 7 S H 0 8FU R P4
R6 K5 -HRE Q1 5
3
A#28 REQ1 R 14
HA 29 W1 J4 -HRE Q2
-HRE Q2 5
DB R ESET 1 2 1 50 1 2
HA 30 A#29 REQ2 -HRE Q3 HT E S T 4
T5 J3 -HRE Q3 5 3 4
2
A#30 REQ3 R18 *0 R 16
HA 31 U4 H3 -HRE Q4
-HRE Q4 5 29 - P R O C H O T
-P ROCHOT 1 2 5 6 0_1% HT E S T 5 5 6 C5
T57 A#31 REQ4 HT E S T 0
V3 2 1 7 8
T58 A#32 R 17
W2 F1 -HRS 0
-HRS 0 5
- H FE RR 1 2 5 6 _1% 0 .1 U
1
T60 A#33 RS0 -HRS 1 56X4
Y1 G5 -HRS 1 5
T62 A#34 RS1 -HRS 2 T DO R430 1 2 7 5 _1%
AB1 F4 -HRS 2 5
HD[0 ..6 3 ] A#35 RS2
5 H D[0 ..6 3 ]
TMS R431 1 2 39
H D0 B21 F21 -H D _STBP0 V CORE
D#0 DSTBP0 -H D _STBP0 5
H D1 B22 E22 - H D _ S T B N0 TCK R432 1 2 27
D#1 DSTBN0 - H D _ S T B N0 5
H D2 A23 J23 -H D _STBP1 - HCP UINIT R 4 99 1 2 1K
D#2 DSTBP1 -H D _STBP1 5
B H D3 A25 K22 - H D _ S T B N1 -T RS T R433 1 2 6 80 I T P CL K 1 R 5 00 1 2 1K B
D#3 DSTBN1 - H D _ S T B N1 5
H D4 C21 P23 -H D _STBP2 I T P CL K 0 R 5 01 1 2 1K
D#4 DSTBP2 -H D _STBP2 5
H D5 D22 R22 - H D _ S T B N2
D#5 DSTBN2 - H D _ S T B N2 5
H D6 B24 W23 -H D _STBP3
D#6 DSTBP3 -H D _STBP3 5
H D7 C23 W22 - H D _ S T B N3
D#7 DSTBN3 - H D _ S T B N3 5
H D8 C24
H D9 D#8
B25
HD 10 D#9
G22
HD 11 D#10 CP UCLK + CP UCLK + R 19 3 3_1%
H21 AF22 CP UCLK + 8
HD 12 D#11 BCLK0 CP UCLK - CP UCLK - R 20 3 3_1%
C26 AF23 CP UCLK - 8
HD 13 D#12 BCLK1
D23
HD 14 D#13 I T P _ CL K -
J21 AD26 Close to CPU
HD 15 D#14 ITP_CLK1 I T P _ CL K + V CORE
D25 AC26
HD 16 D#15 ITP_CLK0
H22
HD 17 D#16 - IE RR C8 *1 8P
E24 AC3
HD 18 D#17 IERR T96
G23 V6 1 2
D#18 MCERR C9 0 .1 U C 10
HD 19 F23 1 2 1 2 1 0 U / 6 .3 V C 11 1 2 1 0 U / 6 .3 V
HD 20 D#19 DB R ESET
F24 AE25
D#20 DBRESET C 12 0 .1 U C 13
HD 21 E25 1 2 1 2 1 0 U / 6 .3 V C 14 1 2 1 0 U / 6 .3 V
HD 22 D#21 -CP UR ST
F26 AB25 -CP URST 5
D#22 RESET C 15 0 .1 U C 16
HD 23 D26 1 2 1 2 1 0 U / 6 .3 V C 17 1 2 1 0 U / 6 .3 V
HD 24 D#23 PW RGD _C PU
L21 AB23 P W R G D _ C P U 27
D#24 PWRGOOD C 18 0 .1 U C 19
HD 25 G26 1 2 1 2 1 0 U / 6 .3 V C 20 1 2 1 0 U / 6 .3 V
HD 26 D#25 T108
H24 AF26
HD 27 D#26 SKTOCC C 21 0 .1 U C 22 2 1 0 U / 6 .3 V C 23 2 1 0 U / 6 .3 V
M21 1 2 1 1
HD 28 D#27
L22
D#28 CP U_ COM P0 R2 1
HD 29 J24 L24 CP U_ COM P0 1 2 4 3_1% C 24 1 2 0 .1 U C 25 1 2 1 0 U / 6 .3 V C 26 1 2 1 0 U / 6 .3 V
D#29 COMP0 CP U_ COM P1 R2 2
HD 30 K23 P1 CP U_ COM P1 1 2 4 3_1%
D#30 COMP1 C 27 0 .1 U C 28
HD 31 H25 Close to CPU 1 2 1 2 1 0 U / 6 .3 V C 29 1 2 1 0 U / 6 .3 V
C HD 32 D#31 T117 C
M23 J26
D#32 DEP0 T119 C 30 0 .1 U C 31
HD 33 N22 K25