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GD1 Block Diagram CPU 1
MEROM
478 PIN (micro FC-PGA) P3,4 14.318MHz
A A
FSB 667 MHz(166X4)
FSB 800 MHz(200X4)
CLOCK GEN
S-Video SVideo Out S-Video
P10 UNBUFFERED ICS9LPR363
DDRII 533/667 DDRII SODIMM
Crestline P2
32MVRAM 32bits P11
LVDS LCD LVDS
P34
ATI M64 P7 1299 Ball (micro FCBGA)
29mm x 29mm 35mm x 35mm
UNBUFFERED
32bits R/G/B CRT R/G/B DDRII 533/667 DDRII SODIMM
32MVRAM P10
P34 P5-9 P11
PCIE 16Lanes
P31-35
B B
DMI(2X, 4X)
PCI-E Mini Azalia Link
PCIE
Intel 3945/Kedron
P17
ICH8-M
ALC262 MDC Module
P19
676 BGA P16
Express Card PCIE 31mm x 31mm
P16 Max.9789A
P20
RJ11
LAN PCIE
C RTL8101E P12-15 C
P28 MIC. Jack Audio Jack INT.SPKR.
3.3V LPC,33MHZ
PCI BUS
USB 2.0
USB 2.0
IDE-PATA
SATA0
RJ45
(10/100)
Card Reader/1394 ODD HDD
TI8402 P23,24
USB Port1P22 BluetoothP24 P21 P21 PCU
WPC8763LP18
USB Port2P22 Camera P22
D MS Pro(Duo)
P24
USB Port3P28 Fingerprint
P16
INT.K/B BIOSP18
QUANTA D
1394
Felica P22
P22
Title
COMPUTER
P23
SD
P24 TOUCH PAD Block Diagram
Size Document Number Rev
1.Level 1 Environment-related Substances Should NEVER be Used. B 1A
2.Purchase ink, paint, wire rods, and Molding resins only from the business Partners that Sony approves as Green Partners.
GD1 Main Board
Date: Tuesday, November 14, 2006 Sheet 1 of 35
1 2 3 4 5
1 2 3 4 5 6 7 8
C1 30P 58
U1
X1
CPUT_L0 52 R_HCLK_CPU RP1 3 4 10X2 HCLK_CPU (3) 2
2
R_HCLK_CPU#
Y1 ICS9PR363BGLF CPUC_L0 51 1 2 HCLK_CPU# (3)
14.318MHZ/20pF/20PPM 49 R_HCLK_MCH RP4 3 4 10X2
CPUT_L1F HCLK_MCH (5)
R256 0_4 57 48 R_HCLK_MCH# 1 2 HCLK_MCH# (5)
1
X2 CPUC_L1F Check level M64=1.2V; M72/74=1.8V
C2 30P 62 44 R_CLK_PCIE_VGA RP5 1 2 E@22X2
(14) PM_STPCPU# CPU_STOP# CPUITPT_L2/PCIET_L8 CLK_PCIE_VGA (31)
63 43 R_CLK_PCIE_VGA# 3 4
(14) PM_STPPCI# PCI/PCIEX_STOP# CPUITPC_L2/PCIEC_L8 CLK_PCIE_VGA# (31)
A R6 E@121/F_4 A
(11,14,16,17) PCLK_SMB 54 SCLK VGA_27MHZ (32)
(11,14,16,17) PDAT_SMB 55 SDATA
17 R_DREFSSCLK RP6 1 2 I@22X2
27FIX/LCD_SSCGT/PCIET_L0 DREFSSCLK (5)
0824 Eric_check EVT MB 18 R_DREFSSCLK# 3 4 R7
27SS/LCD_SSCGC/PCIEC_L0 DREFSSCLK# (5)
CLK8402_48 R558 12.1/F_4 [email protected]/F_4
(23) CLK8402_48
CLKUSB_48 R559 12.1/F_4 R2 E@22_4
(14) CLKUSB_48 VGA_27MHZ# (32)
CPUBSEL0 R8 2.2K/F_4 R_48M 12
R3 10K_4 CPU_BSEL1 FSA/USB_48MHZ R_CLK_PCIE_SATA RP2
VCC3 16 FSB/TEST_MODE SATACLKT_L 26 1 2 22X2 CLK_PCIE_SATA (12)
R25 10K_4 CPU_BSEL2 61 27 R_CLK_PCIE_SATA# 3 4
FSC/REF1/TEST_SEL SATACLKC_L CLK_PCIE_SATA# (12)
14M_ICH
(14) 14M_ICH
R4 22_4 R_14M_ICH 60 19 R_CLK_PCIE_EXPRESS RP3 3 4 22X2
REF0 PCIET_L1 CLK_PCIE_EXPRESS (16)
20 R_CLK_PCIE_EXPRESS# 1 2
PCIEC_L1 CLK_PCIE_EXPRESS# (16)
L14 0_6 CLK_VDD
VCC3
C15 C3 C5 C7 C9 22 R_CLK_PCIE_LAN RP48 3 4 22X2
PCIET_L2 CLK_PCIE_LAN (28)
1 23 R_CLK_PCIE_LAN# 1 2
VDDPCI PCIEC_L2 CLK_PCIE_LAN# (28)
10U/6.3V_8 0.1U_4 0.1U_4 0.1U_4 0.1U_4 7 VDDPC1 R_CLK_PCIE_MCH RP7
11 VDD48 PCIET_L3 24 3 4 22X2 CLK_PCIE_MCH (5) Signal 965GM 965PM
25 R_CLK_PCIE_MCH# 1 2
PCIEC_L3 CLK_PCIE_MCH# (5)
VGA_27MHZ R6 NI 121
C14 56 30 R_CLK_PCIE_MINI RP8 3 4 22X2
VDDREF PCIET_L4 CLK_PCIE_MINI (17)
C13 C10 C11 C12 21 31 R_CLK_PCIE_MINI# 1 2 R7 NI 71.5
VDDPCIEX PCIEC_L4 CLK_PCIE_MINI# (17)
28 VDDPCIEX
1U/6.3V_6 0.1U_4 0.1U_4 0.1U_4 0.1U_4 42 36 R_CLK_PCIE_ICH RP9 1 2 22X2 VGA_27MHZ# R2 NI 22
VDDPCIEX PCIET_L5 CLK_PCIE_ICH (13)
50 35 R_CLK_PCIE_ICH# 3 4
B VDDCPU PCIEC_L5 CLK_PCIE_ICH# (13) B
CLK_PCIE_VGA RP5 NI 22X2
1030 ADD L2 363VREF 47 39
L1 0_6 VREF PCIET_L6
VCC3 45 VDDA PCIEC_L6 38 DREFSSCLK RP6 22X2 NI
C4 C16
PEREQ1#/PCIET_L7 41 DREFCLK RP10 22X2 NI
10U/6.3V_8 0.1U_4 40 PCIE_REQ2#
PEREQ2#/PCIEC_L7 PCIE_REQ2# (16)
10 32 PCIE_REQ3#
(14) CLKEN VTTPWR_GD/PD# *PEREQ3# PCIE_REQ3# (17)
33 PCIE_REQ4#
*PEREQ4# PCIE_REQ4# (5)
1 2 R_DREFCLK 14
(5) DREFCLK PCIET_L9/DOTT_96MHZ
3 4 R_DREFCLK# 15
(5) DREFCLK# PCIEC_L9/DOTC_96MHZL
34 64 R_PCLK_Debug R15 22_4 PCLK_Debug
*PWRSAVE# **REQ_SEL/PCICLK0 PCLK_Debug (17)
RP10 I@22X2 1003 Eric_delete test pad
37 GND PCICLK1 3
VCC3 2 4 R_PCLK_CardBus R17 22_4 PCLK_CardBus
GND PCICLK2 PCLK_CardBus (23)
6 GND
13 5 R72 10K_4 PIN 5 PIN 9
GND *SELPCIEX0_LCD#/PCICLK3
29 GND R494 R26 PIN 14/15 PIN 17/18
53 8 R_PCLK_ICH R19 22_4 PCLK_ICH
GND ITP_EN/PCICLK_F4 PCLK_ICH (13)
R14 59 9 R_PCLK_PCU R18 22_4 PCLK_PCU LO (10K) PCIEX9 27MHZ
GND *SELLCD_27#/PCICLK_F5 PCLK_PCU (18)
1K/F_4 46 GNDA LO (10K)
0824 Eric_Change 33ohm to 22ohm and add R72 PL HI (NC) DOT96 LCD
363VREF * Internal pull up to VDD
**Internal pull down to GND LO (10K) PCIEX9 PCIEX0
C HI (NC) C
HI (NC) DOT96 PCIEX0
R12 C80
220/F_4 0.1U_4
ITP_EN(PIN8)
LOW : PIN43/44 SRC
R27 *1K_4 R_PCLK_Debug R21 10K_4 HIGH : PIN43,44 CPUITP
VCCP VCC3
PCIE_REQ2# R575 10K_4
CPUBSEL0 R29 1K/F_4 PCIE_REQ3# R22 10K_4
(3) CPUBSEL0 MCH_BSEL0 (5)
PCIE_REQ4# R23 10K_4 PCIE_REQ1# PCIE_L0 PCIE_L6
R138 *1K_4
PCIE_REQ2# PCIE_L1 PCIE_L8
R_PCLK_PCU R24 10K_4
FSC FSB FSA Spread R_PCLK_ICH R26 10K_4 PCIE_REQ3# PCIE_L2 PCIE_L4
BSEL2 BSEL1 BSEL0 CPU SRC PCI REF USB DOT % PCIE_REQ4# PCIE_L3 PCIE_L5 PCIE_L7
0 0 0 266.66 100 33.33 14.318 48 96 0.5 Down CLK8402_48 C81 *15P_4
0 0 1 133.33 100 33.33 14.318 48 96 0.5 Down 14M_ICH C17 *10P_4
0 1 0 200.00 100 33.33 14.318 48 96 0.5 Down PCLK_Debug C18 *15P_4
*
D
0 1 1 166.66 100 33.33 14.318 48 96 0.5 Down PCLK_CardBus C19 *15P_4 QUANTA D
1 0 0 333.33 100 33.33 14.318 48 96 0.5 Down CLKUSB_48
PCLK_PCU
C20
C21
*15P_4
*15P_4 Title
COMPUTER
1 0 1 100.00 100 33.33 14.318 48 96 0.5 Down
PCLK_ICH C22 *15P_4
CLOCK GENERATOR
1 1 0 400.00 100 33.33 14.318 48 96 0.5 Down Size Document Number Rev
1 1 1 0.5 Down 1.Level 1 Environment-related Substances Should NEVER be Used. B 1A
200.00 100 33.33 14.318 48 96 2.Purchase ink, paint, wire rods, and Molding resins only from the business Partners that Sony approves as Green Partners.
GD1 Main Board
Date: Wednesday, November 15, 2006 Sheet 2 of 35
1 2 3 4 5 6 7 8
5 4 3 2 1
(5) H_A#[35..3]
H_A#3 J4
U2A
A[3]# ADS# H1 H_ADS# (5)
VCCP (5) H_D#[63..0] H_D#[63..0] (5)
3
ADDR GROUP 0
H_A#4 L5 E2 U2B
A[4]# BNR# H_BNR# (5)
H_A#5 L4 G5 H_D#0 E22 Y22 H_D#32
A[5]# BPRI# H_BPRI# (5) D[0]# D[32]#
H_A#6 K5 H_D#1 F24 AB24 H_D#33
H_A#7 A[6]# H_D#2 D[1]# D[33]# H_D#34
M3 A[7]# DEFER# H5 H_DEFER# (5) E26 D[2]# D[34]# V24
H_A#8 N2 F21 R30 H_D#3 G22 V26 H_D#35
A[8]# DRDY# H_DRDY# (5) D[3]# D[35]#
DATA GRP 0
DATA GRP 0
H_A#9 J1 E1 56_4 H_D#4 F23 V23 H_D#36
A[9]# DBSY# H_DBSY# (5) D[4]# D[36]#
H_A#10 N3 H_D#5 G25 T22 H_D#37
H_A#11 A[10]# H_D#6 D[5]# D[37]# H_D#38
P5 A[11]# BR0# F1 H_BREQ# (5) E25 D[6]# D[38]# U25
H_A#12 P2 H_D#7 E23 U23 H_D#39
A[12]# D[7]# D[39]#
CONTROL
H_A#13 L2 D20 H_IERR# H_D#8 K24 Y25 H_D#40
DATA GRP 2
H_A#14 A[13]# IERR# H_D#9 D[8]# D[40]# H_D#41
D P4 A[14]# INIT# B3 H_INIT# (12) G24 D[9]# D[41]# W22 D
H_A#15 P1 H_D#10 J24 Y23 H_D#42
H_A#16 A[15]# H_D#11 D[10]# D[42]# H_D#43
R1 A[16]# LOCK# H4 H_LOCK# (5) J23 D[11]# D[43]# W24
M1 H_D#12 H22 W25 H_D#44
(5) H_ADSTB#0 ADSTB[0]# H_CPURST# (5) D[12]# D[44]#
C1 H_D#13 F26 AA23 H_D#45
RESET# H_RS#0 H_D#14 D[13]# D[45]# H_D#46
(5) H_REQ#0 K3 REQ[0]# RS[0]# F3 K22 D[14]# D[46]# AA24
H2 F4 H_RS#1 H_D#15 H23 AB25 H_D#47
(5) H_REQ#1 REQ[1]# RS[1]# D[15]# D[47]#
K2 G3 H_RS#2 J26 Y26
(5) H_REQ#2 REQ[2]# RS[2]# H_RS#[2..0] (5) (5) H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 (5)
(5) H_REQ#3 J3 REQ[3]# TRDY# G2 H_TRDY# (5) (5) H_DSTBP#0 H26 DSTBP[0]# DSTBP[2]# AA26 H_DSTBP#2 (5)
(5) H_REQ#4 L1 REQ[4]# (5) H_DINV#0 H25 DINV[0]# DINV[2]# U22 H_DINV#2 (5)
HIT# G6 H_HIT# (5) (5) H_D#[63..0] H_D#[63..0] (5)
H_A#17 Y2 E4
A[17]# HITM# H_HITM# (5)
H_A#18 U5 H_D#16 N22 AE24 H_D#48
H_A#19 A[18]# T2 H_D#17 D[16]# D[48]# H_D#49
R3 A[19]# BPM[0]# AD4 K25 D[17]# D[49]# AD24
ADDR GROUP 1
H_A#20 W6 AD3 T3 H_D#18 P26 AA21 H_D#50
H_A#21 A[20]# BPM[1]# T1 H_D#19 D[18]# D[50]# H_D#51
XDP/ITP SIGNALS
U4 A[21]# BPM[2]# AD1 R23 D[19]# D[51]# AB22
H_A#22 Y5 AC4 T4 H_D#20 L23 AB21 H_D#52 Layout note:
A[22]# BPM[3]# D[20]# D[52]#
DATA GRP 1
H_A#23 U1 AC2 T5 0920 Eric_Check list V1.301 H_D#21 M24 AC26 H_D#53 Comp0,2 connect with