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System Module UG3

NSM­1

Block Diagram of Baseband

(Version 2.1 Edit 98) for layout version 9.1

Original 10/98

UG3MA/A3­1

System Module UG3

NSM­1

Block Diagram of COBBA, CCONT and MAD

Original 10/98

UG3MA/A3­2

System Module UG3

NSM­1

Circuit Diagram of Power Supply (Version 2.31

Edit 299) for layout version 10.4

Original 10/98

UG3MA/A3­3

System Module UG3

NSM­1

Circuit Diagram of SIM Connector (Version 2.31

Edit 99) for layout version 10.4

Original 10/98

UG3MA/A3­4

System Module UG3

NSM­1

Circuit Diagram of CPU Block (Version 2.31

Edit 203) for layout version 10.4

Original 10/98

UG3MA/A3­5

System Module UG3

NSM­1

Circuit Diagram of Audio

(Version 2.31 Edit 155) for layout version 10.4

Original 10/98

UG3MA/A3­6

System Module UG3

NSM­1

Circuit Diagram of IR Module (Version 2.31

Edit 128) for layout version 10.4

Original 10/98

UG3MA/A3­7

System Module UG3

NSM­1

RF Block Diagram

BAND SELECT

193 MHz

73 MHz

60 MHz 120 MHz

BAND SELECT

480 MHz

1950 ­ 2073 MHz

CRFU3

SUMMA

GSM 120 MHz PCN 240 MHz

GSM PA

GSM 120 MHz

PCN 240 MHz

PCN PA

Original 10/98

UG3MA/A3­8

System Module UG3

NSM­1

Circuit Diagram of RF Block (Version

2.31 Edit 309) for layout version 10.4

Original 10/98

UG3MA/A3­9

System Module UG3

NSM­1

Circuit Diagram of UIF

(Version 2.31 Edit 126) for layout version 10.4

Original 10/98

UG3MA/A3­10

System Module UG3

NSM­1

Layout Diagram of UG3MA ­ Top (Version 10.4)

Layout Diagram of UG3MA ­ Bottom (Version 10.4)

Original 10/98

UG3MA/A3­11

System Module UG3
testpoint ref J101 J104 J108 J220 J223 J225 J226 J227 J228 J235 J251 J256 J500 name FBUS_TX CCONTCSX (CCONT chip select) CHRG_CTRL V5V CCONTINT (charger, RTC interrupt) EXTSYSRESETX VCXOPWR PURX (power on reset) SLEEPCLK (32kHz clock) ROM1SELX AGND COBBADAX Control voltage for UHF VCO module G600 condition active state active state charger connected active state interrupt power on power on power up/down power on active state pcb ground active state channel 60 channel 1 channel 124 dc­level pulsed DC (0V72.8V) pulse active 0V, non­active 2.8V pulsed DC (0V/2.8V) nominal 5.0V (min 4.8V, max 5.2V) pulse active 2.8V, non­active 0V reset state 0V, normal state 2.8V active state 2.8V, non­active 0V reset state 0V, normal state 2.8V pulsed DC (0V/2.8V) pulse active 0V, non­active 2.8V 0V pulse active 0V, non­active 2.8V 2.25 +/­ 0.25 V > 0.8 V < 3.7 V typ. 2.0 ­2.2 V min 0.5 / max 4.0 V 2.8 V min 2.7 / max 2.85 V ­95 dBm @ X540 (ext. RF connector ) RXC at level of full calibrated gain ­95 dBm @ X540 (ext. RF connector ) RXC at level of full calibrated gain typ ca. 1.0 ­ 1.1 V pulsed min. 0.7 / max. 1.4 V ac­level

NSM­1

J504 J508 J534&J536

Control voltage for VHF VCO circuit VSYN_2 ( regulated supply for PLLS ) 13 MHz IF output to N250

typ. 50 mVpp balanced voltage at 13 MHz

J538

13 MHz output from Z620 to N620

typ. ca. 1.5 V pulsed

typ. ca 600 uVrms

J542 J554 J556 J558 J560

VHF VCO output ( 232 MHz ) TXC ( TX power control voltage ) TXP ( TX enable ) TXQP ( other half of balanced Q­signal ) TXIP ( other half of balanced I­signal )

­ @level 19 typ. ca. 0.6 V pulse @level 5 typ ca. 1.8 V pulse 2.8 V logic level pulse, ( max. 0.8 V "0" / min 2.0 V "1" ) 0.8 V pulsed 0.8 V pulsed

typ. 400 mVpp. > 100 mVpp required

400 mVpp 400 mVpp

Original 10/98

UG3MA/A3­12