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5 4 3 2 1
CPU DC/DC
Spears Intel UMA Block Diagram 2007/08/29 ISL6262A
INPUTS OUTPUTS
Project code : 91.4W001.001 DCBATOUT VCC_CORE
Intel CPU
D
PCB P/N : 07211 D
CLK GEN Merom 4M
ICS9LPRS365 FSB:667MHz/800MHz
Revision : -1 SYSTEM DC/DC
4 5,6,7 TPS5117
RGB CRT CRT 17 INPUTS OUTPUTS
Host BUS 1D05V_S0
DCBATOUT
533/667MHz 1D8V_S3
LVDS LCD 18
DDRII Slot 0 DDRII 667 Channel A SYSTEM DC/DC
533/667 14 Crestline-GM S-Vedio TPS51120
16
SVIDEO
AGTL+ CPU I/F DDR I/F (Upsell)
INPUTS OUTPUTS
DDRII Slot 1 INTEGRATED GRAHPICS
15
DDR II 667 Channel B
533/667 LVDS, CRT I/F 8,9,10,11,12,13
PCIE x 16 SiI 1392 23 HDMI DCBATOUT
5V_AUX_S5
5V_S5
SDVO 16
(Upsell) (Upsell) 3D3V_S5
C C
Power SW
DMI I/F 28 SYSTEM DC/DC
TI TPS2231
100MHz TPS51100
INPUTS OUTPUTS
1394 1394 25,26
26 PCIE x 1 & USB 2.0 x 1 1D8V_S3 0D9V_S3
INTEL AZALIA
New Card 28
Ricoh PCI
R5C833
SD/SDIO/MMC 10/100 NIC SYSTEM DC/DC
MS/MS Pro/xD
26
CardReader ICH8-M PCIE x 1
Marvell 88E8040 27 RJ45 CONN 28
LDO
10 USB 2.0/1.1 ports Mini-Card X2 INPUTS OUTPUTS
PCIE PCIE x 2 & USB 2.0 x 1
802.11a/b/g 29
ETHERNET (10/100/1000Mb) 30
BT/UWB/Robson 3D3V 2D5V
High Definition Audio
PCIE x 1 & USB 2.0 x 1 Mini-Card X1 1D8V 1D5V_S0
30
RJ11 CONN MDC MODEM ATA 66/100
AZALIA WWAN(Upsell)
31 31
(Option) (Option)
B ACPI 1.1 USB 2.0 USB 2.0 x 1 CAMERA SYSTEM DC/DC B
Digital Mic Array 24 LDO
LPC I/F (Option)
Azalia PCI/PCI BRIDGE LPC Bus
INPUTS OUTPUTS
MIC IN Lift Side: USB x 2
CODEC 19,20,21,22 USB 2.0 x 1 DCBATOUT 3D3V_AUX_S5
Right Side: 24
HP1 1D5V_S0
USB x 1
Sigmatel SPI USB x 1(Upsell)
STAC 9228 KBC
HP2 MAXIM CHARGER
Winbond WPC8763L
MAX8731A
SATA
PATA
34
32
Internal Analog MIC INPUTS OUTPUTS
AD+
BAT+
DCBATOUT
2CH Thermal
SPEAKER OP AMP Capacity Touch Int. S/W Flash ROM
HDD ODD & Fan
MAX9789A 33 24 24 Button37 Pad 37 KB37 CIR 1MB 35
G792 36
A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
DS2 System Block Diagram
Size Document Number Rev
A3
Spears-Intel -1
Date: Wednesday, September 12, 2007 Sheet 1 of 47
5 4 3 2 1
5 4 3 2 1
TI TPS51120
CPU_CORE 3D3V/5V
ISL6262A 1D5V_S0
Input Signal Output Signal
VID Setting Output Signal 5V_S5
VID0 VCNTL
VID0(I / 3.3V) VRPWRGD 1D5V_S0
VROK() 3V/5V_EN FOR VOUT(O)
D VID1 51120_EN2 3.3V 1D8V_S3 D
VID1(I / 3.3V) CPUCORE_ON(Pull High 3D3V) VIN
PGOUT1(OD / 5V)
VID2 51120_EN1 FOR
VID2(I / 3.3V) 5.0V PGOUT2(OD / 3D3V) PM_SLP_S3# CPUCORE_ON
EN POK
VID3
VID3(I / 3.3V)
Output Power
VID4
VID4(I / 3.3V) VCC_CORE_S0(Imax=35A) APL5915
VCC_CORE_PWR(O)
VID5 DCBATOUT
VID5(I / 3.3V) VIN
5V_AUX_S5 2D5V_S0
Input Signal
Input Power Output Power
CPUCORE_ON 3D3V_S0 2D5V_S0
EN (I / 3.3V) INPUT OUT
3D3V_AUX_S5
DCBATOUT
Voltage Sense VIN G9131
5V_S5 (6A)
VCC_SENSE 5V(O)
VSEN(I / Vcore) 5V_AUX_S5 1D25V_S0
C
V5FILT(I / 5V) C
VSS_SENSE
RGND(I / Vcore) 3D3V_S5 (5A) 5V_S5
3D3V(O) VCNTL
1D5V_S0
VOUT(O)
Input Power 1D8V_S3
VIN
DCBATOUT
VCC(I)
PM_SLP_S3# CPUCORE_ON
EN POK
5V_S0
VCC(I)
Adapter
3D3V_S0 G971
VCC(I) Input Signal Output Signal Charger_MAX8731A
AD_IN
AD_OFF (I) (O)
Input Signal Output Signal
CHARGE_OFF MAX8731_LDO
CLS (I / 3.3V) LDO (O / 5.4V)
Input Power Output Power
AD_JK AD+
VCC(I) VCC(O) XTAL2/PB4 (O/5V)
BAT+SENSE
B
5V_AUX_S5 BATT (I / 3.3V) B
VCC(I) XTAL1/PB3 (O/5V)
TI TPS51100 BT_SCL
SCL (IO / 5V)
0.9V/DDR_VREF_S3 BT_SDA
SDA (IO / 5V)
TPS51117_1D8V_S3 Output Power
Input Signal DCBATOUT
PM_SLP_S4# VCC (O)
S5
PM_SLP_S3#
S3 Input Signal Output Signal BT+
PM_SLP_S4# VCC (O)
EN_PSV(I / 5V) CPUCORE_ON AC_IN
PGOUT(OD / 5V) PB0/MOSI/AIN0
Output Power
0D9V_DDR_VTT 5V_S5 Input Power Output Power Input Power
VCC(O) VCC 1D8V_S3 AD+
Input Power 1D8V_PWR DCIN (I)
DCBATOUT
VIN
DCBATOUT DDR_VREF_S3
VCC(I) VCC(O) TPS51117_1D05V
5V_S5
A VCC(I) A
Input Signal Output Signal
PM_SLP_S3#
EN_PSV(I / 5V) CPUCORE_ON
PGOUT(OD / 5V) Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
5V_S5 Input Power Output Power Title
VCC 1D05V_S0 (15A)
1D05V_PWR Power Block Diagram
DCBATOUT Size Document Number Rev
VIN A3
DS2-Intel -1
Date: Wednesday, September 12, 2007 Sheet 2 of 47
5 4 3 2 1
A B C D E
INTEL ICH8-M STRAP PIN 20,22 +RTCVCC +RTCVCC
5,6,7,8,10,11,12,20,22,34,43,47 1D05V_S0 1D05V_S0
8,11,22,45 1D25V_S0 1D25V_S0
Signal Usage/When Sampled Comment XOR Chain Entrance Strap 27 1D2V_LAN_S5 1D2V_LAN_S5
HDA_SDOUT XOR Chain Entrance/ Allows entrance to XOR Chain testing when TP3 ICH_RSVD
tp3 AZ_DOUT_ICH Description
28 1D5V_NEW_S0 1D5V_NEW_S0
PCIE Port Config 1 bit1, pulled low at rising edge of PWROK.When TP3 not 0 0 RSVD
4 Rising Edge of PWROK pulled low at rising edge of PWROK,sets bit1 of 0
1
1
0
Enter XOR Chain
Normal Operation(default)
6,11,20,21,22,28,29,30,45 1D5V_S0 1D5V_S0 4
RPC.PC(Config Registers:offset 224h) 1 1 Set PCIE port cofig bit1
8,11,12,14,15,44,45,46,47 1D8V_S3 1D8V_S3
HDA_SYNC PCIE Port Config 1 bit0, Sets bit0 of RPC.PC(Config Registers:Offset 224h)
Rising Edge of PWROK. 27,28 2D5V_LAN_S5 2D5V_LAN_S5
GNT2# PCIE Port Config 2 bit0, Sets bit2 of RPC.PC(Config Registers:Offset 224h)
Rising Edge of PWROK.
20,31,34,35,36,38,39,40,47 3D3V_AUX_S5 3D3V_AUX_S5
GPIO20 Reserved Weak Internal PULL-DOWN.NOTE:This signal should 27,28 3D3V_LAN_S5 3D3V_LAN_S5
not be pull HIGH.
4,8,10,11,14,15,16,17,18,19,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,40,41,43,45,46,47 3D3V_S0 3D3V_S0
Sampled low:Top-Block Swap mode(inverts A16 for all A16 swap override strap
GNT3# Top-Block Swap Override. cycles targeting FWH BIOS space). 19,21,22,27,28,31,35,38,40,46,47 3D3V_S5 3D3V_S5
Rising Edge of PWROK. Note: Software will not be able to clear the PCI_GNT#3 low = A16 swap override enable
Top-Swap bit until the system is rebooted high = default 18,39,40,47 5V_AUX_S5 5V_AUX_S5
without GNT3# being pulled down. BOOT BIOS Strap
PCI_GNT#0 SPI_CS#1 BOOT BIOS Location
GNT0# Boot BIOS Destination Controllable via Boot BIOS Destination bit 16,17,18,22,24,33,35,36,37,41,45,46,47 5V_S0 5V_S0
SPI_CS1# Selection. (Config Registers:Offset 3410h:bit 11:10). 0 1 SPI
Rising Edge of PWROK. GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC. 1 0 PCI 22,24,29,30,31,35,38,40,43,44,45,46,47 5V_S5 5V_S5
1 1 LPC(Default)
Integrated VccSus1_05 38,39,47 AD+ AD+
VccSus1_5 and VccCL1_5 Enables integrated VccSus1_05,VccSus1_5 and integrated VccSus1_05,VccSus1_5,VccCL1_5
INTVRMEN VRM Enable/Disable.Always VccCL1_5 VRM when sampled high 18,39,40,41,42,43,44,46,47 DCBATOUT DCBATOUT
SM_INTVRMEN High=Enable Low=Disable
sampled.
14,15,45,47 DDR_VREF_S0 DDR_VREF_S0
3 Integrated VccLAN1_05 Enables integrated VccLAN1_05,VccCL1_05 VRM
integrated VccLan1_05VccCL1_05
8,14,15,45 DDR_VREF_S3 DDR_VREF_S3
3
LAN100_SLP VccCL1_05 VRM enable when sampled high LAN100_SLP High=Enable Low=Disable
/Disable. Always sampled.
18 +LCDVDD +LCDVDD
SATALED# PCIE LAN REVERSAL.Rising This signal has weak internal pull-up. DEFAULE HIGH
Edge of PWROK. set bit27 of MPC.LR(Device28:Function0:Offset D8) 6,7,42 VCC_CORE_S0 VCC_CORE_S0
If sampled high, the system is strapped to the No Reboot Strap
SPKR No Reboot. "No Reboot" mode(ICH8M will disable the TCO Timer SPKR LOW = Defaule
Rising Edge of PWROK. system reboot feature). The status is readable
via the NO REBOOT bit.(Offset:3410h:bit5)
High=No Reboot
TP3 XOR Chain Entrance. This signal should not be pull low unless using
Rising Edge of PWROK. XOR Chain testing.
GPIO33/
Internal Pull-Up.If sampled low,the Flash Descriptor
Flash Descriptor Security Security will be overidden.if high,the Security
INTEL ICH8-M INTEGRATED
HDA_DOCK_EN# Override Strap
Rising Edge of PWROK.
measures defined in the Flash Descriptor will be in
effect.
8.2K PULL HIGH PULL-UPS and PULL-DOWNS
This should only be used in manufacturing
environments
SIGNAL Resistor Type/Value
HDA_BIT_CLK PULL-DOWN 20K
HDA_RST# NONE
2 HDA_SDIN[3:0] PULL-DOWN 20K 2
HDA_SDOUT PULL-DOWN 20K
HDA_SYNC PULL-DOWN 20K
INTEL CRESTLINE STRAP PIN GNT[3:0] PULL-UP 20K
CFG Strap LOW 0 HIGH 1 GPIO[20] PULL-DOWN 20K
CFG 5 LDA[3:0]#/FHW[3:0]# PULL-UP 20K
DMI X 2 DMI X 4
CFG 8 LAN_RXD[2:0] PULL-UP 20K
Low Power PCI Express Normal Low Power mode
CFG 9 LDRQ[0] PULL-UP 20K
PCI Express Graphics Lane Reversal Normal Mode(Lanes
Lane Reversal number in order) LDRQ[1]/GPIO23 PULL-UP 20K
CFG 16
FSB Dynamic ODT Disabled Enabled PME# PULL-UP 20K
CFG 19
DMI Lane Reserved Normal Operation Reserved Lane PWRBTN# PULL-UP 20K
CFG 20 Only PCIE or SDVO PCIE and SDVO are
Concurrent SDVO/PCIE is operation operation simultaneous SATALED# PULL-UP 20K
SDVO_CTRL_DATA NO SDVO Card SDVO Card Present SPI_CS1# PULL-UP 20K
Present
SDVO Present SPI_CLK PULL-UP 20K
CFG 12 XOR/ALL-Z SPI_MOSI PULL-UP 20K
1 CFG 13
LL(00) Reserved
1
SPI_MISO PULL-UP 20K
LH(01) XOR Mode Enabled Wistron Corporation
HL(10) All Z Mode Enabled TACH_[3:0] PULL-UP 20K 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
HH(11) Normal Operation Taipei Hsien 221, Taiwan, R.O.C.
SPKR PULL-DOWN 20K
Title
TP[3] PULL-UP 20K
Table of Content
USB[9:0][P,N] PULL-DOWN 15K Size Document Number Rev
A3
CL_RST# TBD DS2-Intel -1
Date: Wednesday, September 12, 2007 Sheet 3 of 47
3D3V_S0 5 3D3V_S0_CK505 4 3 2 1
2 1 3D3V_S0_CK505 3D3V_S0_CK505_IO
R127 0R0603-PAD
1
1
1
1
1
1
1
C222 C219 C527 C549 C523 C529 C537
SC1U10V3KX-3GP
SC10U6D3V5KX-1GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2
2
2
2
2
2
2
X3
CLK_XTAL_IN 1 2 CLK_XTAL_OUT
X-14D31818M-37GP
1
1
D C214 C211
D
SC15P50V2JN-2-GP SC15P50V2JN-2-GP
2
2