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5 4 3 2 1
A3E CONTEXT CPU
01_BLOCK DIAGRAM
DOTHAN
PAGE 3,4
02_REVISION LIST
03_DOYHAN CPU(1)
D
04_DOTHAN CPU(2) FSB D
05_THERMAL SENSOR,FAN 533MHz
06_ALVISO GMCH(1)
LVDS
07_ALVISO PCIE(2)
PAGE 16
08_ALVISO DDR SLOT(3)
09_ALVISO POWER(4) MCH-M DDR DDR
CRT SO-DIMM
10_ALVISO GND(5)
11_GMCH STRAPPING/LVDS TRANS PAGE 15
Alviso
PAGE 17,18,19
12_ICH6M_SATA,LPC,IDE(1)
TV OUT PAGE 6,7,8,9,10
13_ICH6M_USB,PCI/E,PMIO(2)
14_ICH6M_PWR,GND(3) PAGE 15 DMI interface PCMCIA
PAGE 30
15_CRT&TV OUT CONN
16_LVDS&INVERTER(CAMERA,WLAN)
17_DDR_SODIMM
PCI 33MHz R5C841 1394
PAGE 30 31
C 18_DDR_DATA TERMINATION C
19_DDR_ADDRESS TERMINATION
LPC 33MHz PAGE 29,30,31
FWH
20_CLOCK GEN ICS954213 ICH6-M CARD READER
Azalia
PAGE 22 PAGE 31
21_KBC M38857
22_FWH,SIO,SIR MINI-PCI
23_AZALIA ALC880 802.11 a/b/g
SIR SUPER I/O PAGE 26
24_AMPLIFIER 2 CHANNEL PAGE 12,13,14
25_MIC,LINE-IN JACK PAGE 22
PAGE 22 IDE
26_MINI-PCI 10/100 LAN
27_LAN_RTL8100CL AUDIO DJ KEY RTL8100CL
28_RJ11/45,MDC,PRN PAGE 35 PAGE 27,28
KBC 38857 HDD AUDIO DJ/SW/TP
29_PCI CARDBUS R5C841
PAGE 35
30_PCI PCMCIA SOCKET A INSTANT KEY PAGE 32
PAGE 21
31_PCI IEEE1394A,3IN1 CON PAGE 35
FAN + SENSOR
B 32_HDD CONNECTOR B
PAGE 5
33_Q/SW,CD-ROM CONNECTOR
CD ROM
34_USB CONNECTOR AZALIA CODEC CLOCK GEN
35_DJ BOARD/SW/TP PAGE 33
ICS954213
PAGE 23,24,25 PAGE 20
36_STARTUP CIRCUIT(1)
37_STARTUP CIRCUIT(2)
Startup Circuit
38_VCORE
MDC Header USB 2.0 PAGE 36,37
39_SYSTEM(3V,5V) X4
40_2.5V,1.5V,1.8V,1.05V PAGE 27
PAGE 34 Power On Sequence
41_VCCA,DDR(1.25VS)
PAGE 46
42_PIC/BAT CONN/PWOK/THERM PT
43_CHARGE
Power Flowchart
44_BATLOW/SD#
PAGE 47
45_LOAD SWITCH
A 46_POWER ON SEQUENCE A
System Resource
47_SYSTEM RESOURCE
PAGE 48
48_Power Flowchart
49_EE HISTORY
Title : BLOCK DIAGRAM
50_PWR HISTORY
ASUSTeK COMPUTER INC
Engineer: Quan-Tai Lin
Size Project Name Rev
Custom A3E 2.2
Date: Thursday, May 05, 2005 Sheet 1 of 51
5 4 3 2 1
A B C D E
POWER INTERFACE IMPEDENCE PCB STACK-UP
REVISION LIST SIGNALS TYPE POWER PCB THICKNESS: 1.6 mm
Single-Ended
R1.0 2005/01/10
PM_PSI# O +VCCP 27.4 OHM WIDTH
L1 TOP
1 VR_VID[5:0] O +VCCP TOP/BOT 18 mils 1
L2 GND
VRON O +3.3V
L3 IN1
PM_DPRSLPVR O +3.3V 37.5 OHM WIDTH
L4 IN2
CPU_STP# O +3.3V TOP/BOT 11 mils
IN1/IN2 9.5 mils L5 GND
RST_BTN# O +3.3V
L6 BOT
CLK_EN# I +3.3V
DELAY_VR_PWRGD I +3.3V
OTP_RESET# I +3.3V
PAGE 38
SHUT_DOWN# I +3.3V 50 OHM WIDTH
SIGNAL IN: VR_VID[0..5]
BAT_LEARN I +3.3V TOP/BOT 6 mils PM_DPRSLPVR
BAT_LLOW#_OC I +3.3V IN1/IN2 5 mils STP_CPU#
PM_PSI#
CPU_VRON
2
BAT_IN#_OC I +3.3V 55 OHM WIDTH MCH_OK 2
CHG_EN# I +3.3V TOP/BOT 5.5 mils OUT: DELAY_VR_PWRGD
CHG_FULL_OC I +3.3V IN1/IN2 4.5 mils CLK_PWR_GD#
CHG_LED_UP I +3.3V 75 OHM WIDTH POWER IN: AC_BAT_SYS
+5VO
SMCLK_BAT1 IO +3.3V TOP/BOT 4 mils +3VO
SMDATA_BAT1 IO +3.3V IN1/IN3 3.5 mils
OUT: +VCORE
SUSB# O +3.3V Differential
SUSC# O +3.3V
PAGE 39
1.8V_PWRGD I +3.3V
SIGNAL IN: SUSC#_PWR
1.5VS_PWRGD I +3.3V VSUS_ON
VSUS_ON O +3.3V 85 OHM WIDTH/SPACE
POWER IN: AC_BAT_SYS
ACIN_OC I +3.3V TOP/BOT 5.5 mils/ 4 mils
3 ACIN# I AC_BAT_SYS IN1/IN2 4.5 mils/ 4 mils 3
OUT: +12VO
+3VO
+3VA PWR +3.3V 90 OHM WIDTH/SPACE +5VO
+5VA PWR +5V TOP/BOT 5.5 mils/ 5 mils
+5VLCM PWR +5VLCM IN1/IN2 4.5 mils/ 5 mils PAGE 40
A/D_DOCK_IN PWR DC 100 OHM WIDTH/SPACE SIGNAL IN: SUSB#_PWR
SUSC#_PWR
CPU_VRON
AC_BAT_SYS PWR DC TOP/BOT 6 mils/ 11 mils
IN1/IN2 5 mils/ 12 mils POWER IN: AC_BAT_SYS
+5VO
110 OHM WIDTH/SPACE OUT: +1.8V
+1.5VS
TOP/BOT 5 mils/ 13 mils +2.5VS
IN1/IN2 4 mils/ 12 mils +VCC_GMCH_CORE
POWER PLANE +5VALWAYS
+3VALWAYS
+VCCP
POWER VOLTAGE CURRENT
4 +VCORE 0.7 - 1.77V 27A PCI INTERFACE 4
+VCCP 1.05 - 1.2V 3.95A
PCI_REQ# PAGE 41
+VCC_GMCH 1.05V 4.12A SIGNAL IN: SUSB#_PWR
+0.9VS 1.25V 0.85A MINIPCI PCI_REQ#3
+1.5VS 1.5V 4.33A 10/100 PCI_REQ#2 POWER IN: +3V
+1.8V
+1.5V 1.5V 300 mA CB&1394 PCI_REQ#1
+1.5VSUS 1.5V 270 mA
IDSEL OUT: +0.9VS
+2.5V 2.5V 6.68A
+2.5VS 2.5V 0.3 A MINIPCI PCI_AD19
+3VS 3.3V 1.732A 10/100 PCI_AD16
+3V 3.3V 1.515A CB&1394 PCI_AD17
5
+3VSUS 3.3V 540 mA 5
+5VS 5V 4.1A
+5V 5V 0.5A Title : REVISION LIST
+5VSUS 5V 0.5A Engineer: Quan-Tai Lin
ASUSTeK COMPUTER INC
+12V 12V 0.25A Size Project Name Rev
+12VS 12V 0.25A Custom A3E 2.2
Date: Thursday, May 05, 2005 Sheet 2 of 51
A B C D E
5 4 3 2 1
H_D#[0..63] 6
U37B 1 T26 TPC28t
6 H_A#[16..3]
H_A#16 AA2 N2 U37A
A[16]# ADS# H_ADS# 6
H_A#15 Y3 A10 1 T206 H_D#15 C25 Y25 H_D#47
H_A#14 A[15]# PRDY# TPC28t R431 56Ohm / H_D#14 D[15]# D[47]# H_D#46
AA3 A[14]# PREQ# B10 +VCCP E23 D[14]# D[46]# AA26
H_A#13 U1 r0402 H_D#13 B23 Y23 H_D#45
H_A#12 A[13]# H_D#12 D[13]# D[45]# H_D#44
Y1 A[12]# BNR# L1 H_BNR# 6 C26 D[12]# D[44]# V26
H_A#11 Y4 J3 H_D#11 E24 U25 H_D#43
H_BPRI# 6
ADDRESS GROUP 0
D H_A#10 A[11]# BPRI# H_D#10 D[11]# D[43]# H_D#42 D
W2 A[10]# D24 D[10]# D[42]# V24
DATA GROUP 0
H_A#9 H_D#9 H_D#41
2
T4 A[9]# B24 D[9]# D[41]# U26
H_A#8 W1 A7 TPC28t
1 T204 H_D#8 C20 AA23 H_D#40
DATA GROUP
H_A#7 A[8]# DBR# H_D#7 D[8]# D[40]# H_D#39
V2 A[7]# B20 D[7]# D[39]# R23
H_A#6 R3 H_D#6 A21 R26 H_D#38
H_A#5 A[6]# H_D#5 D[6]# D[38]# H_D#37
V3 A[5]# B26 D[5]# D[37]# R24
H_A#4 U4 L4 H_D#4 A24 V23 H_D#36
A[4]# DEFER# H_DEFER# 6 D[4]# D[36]#
H_A#3 P4 H2 H_D#3 B21 U23 H_D#35
A[3]# DRDY# H_DRDY# 6 D[3]# D[35]#
U3 M2 H_D#2 A22 T25 H_D#34
6 H_ADSTB#0 ADSTB[0]# DBSY# H_DBSY# 6 D[2]# D[34]#
H_REQ#4 T1 H_D#1 A25 AA24 H_D#33
H_REQ#3 REQ[4]# H_D#0 D[1]# D[33]# H_D#32
P1 REQ[3]# A19 D[0]# D[32]# Y26
H_REQ#2 T2 D25 T24
REQ[2]# 6 H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 6
H_REQ#1 P3 C23 W25
REQ[1]# 6 H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 6
H_REQ#0 R2 C22 W24
REQ[0]# 6 H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 6
N4 H_BR0# 6
CONTROL
BR0# H_D#31 H_D#63
6 H_REQ#[4..0] K25 D[31]# D[63]# AF26
H_D#30 N25 AF22 H_D#62
H_IERR# R390 56Ohm H_D#29 D[30]# D[62]# H_D#61
IERR# A4 +VCCP H26 D[29]# D[61]# AF25
r0402 H_D#28 M25 AD21 H_D#60
6 H_A#[31..17] D[28]# D[60]#
H_A#31 AF1 H_D#27 N24 AE21 H_D#59
H_A#30 A[31]# H_D#26 D[27]# D[59]# H_D#58
AE1 B5 H_INIT# 12 L26 AF20
3
A[30]# INIT# D[26]# D[58]#
DATA GROUP 1
H_A#29 AF3 H_D#25 J25 AD24 H_D#57
H_A#28 A[29]# H_D#24 D[25]# D[57]# H_D#56
DATA GROUP
AD6 M23 AF23
ADDRESS GROUP 1
H_A#27 A[28]# H_D#23 D[24]# D[56]# H_D#55
AE2 A[27]# LOCK# J2 H_LOCK# 6 J23 D[23]# D[55]# AE22
H_A#26 AD5 H_D#22 G24 AD23 H_D#54
H_A#25 A[26]# TPC28t T16 H_D#21 D[22]# D[54]# H_D#53
AC6 A[25]# 1 F25 D[21]# D[53]# AC25
H_A#24 AB4 H_D#20 H24 AC22 H_D#52
H_A#23 A[24]# R80 H_D#19 D[20]# D[52]# H_D#51
AD2 A[23]# 2 1 54.9Ohm / +VCCP M26 D[19]# D[51]# AC20
C H_A#22 AE4 1% H_D#18 L23 AB24 H_D#50 C
H_A#21 A[22]# H_D#17 D[18]# D[50]# H_D#49
AD3 A[21]# RESET# B11 H_CPURST# 6 G25 D[17]# D[49]# AC23
H_A#20 AC3 L2 H_RS#2 H_D#16 H23 AB25 H_D#48
H_A#19 A[20]# RS[2]# H_RS#1 D[16]# D[48]#
AC7 A[19]# RS[1]# K1 6 H_DINV#1 J26 DINV[1]# DINV[3]# AD20 H_DINV#3 6
H_A#18 AC4 H1 H_RS#0 K24 AE24
A[18]# RS[0]# 6 H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 6
H_A#17 AF4 L24 AE25
A[17]# H_RS#[0..2] 6 6 H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 6
6 H_ADSTB#1 AE5 ADSTB[1]# TRDY# M3 H_TRDY# 6
SOCKET479P
HIT# K3 H_HIT# 6
6 H_DPWR# C19 DPWR# HITM# K4 H_HITM# 6 Layout note:
SOCKET479P
COMP0 and COMP2 need to be Zo=27.4ohm traces.
Best estimate is 18mil wide trace for outer layers and
U37C 14mil if on internal layer. See RDDP of Banias.
20 CLK_CPU_BCLK B15 BCLK[0]
B14
Traces should be shorter than 0.5". Refer to latest CS layout
HOSTCLK
20 CLK_CPU_BCLK# BCLK[1]
R440 2 r0402 1 49.9Ohm 1% A16 AB1 H_COMP3 R38 2 1 54.9Ohm 1%
R439 2 r0402 1 49.9Ohm 1% ITP_CLK[0] COMP[3] H_COMP2 R37 27.4Ohm
A15 ITP_CLK[1] COMP[2] AB2 1 2 COMP1, COMP3 should be routed as Zo=55ohm
P26 H_COMP1 R462 2 1 54.9Ohm 1%
COMP[1] H_COMP0 R461 27.4Ohm traces shorter than 0.5"
12 H_A20M# C2 A20M# COMP[0] P25 1 2
GND D3
12 H_FERR# FERR#
LEGACY CPU
12 H_IGNNE# A3 IGNNE#
12 H_DPSLP# B7 DPSLP# BPM[3]# C9
A6 A9 GND
6,12 H_CPUSLP# SLP# BPM[2]#
TPC28t T227
1 D1 B8 +VCCP
12 H_INTR LINT0 BPM[1]#
12 H_NMI D4 LINT1 BPM[0]# C8
12 H_SMI# B4 SMI#
2
TPC28t T226 C6
B 12 H_STPCLK# STPCLK# B
1 R463 FSB 400MHz -> 1.8V
E4 AC1 1KOhm FSB 533MHz -> 1.5V
12 H_PWRGD PWRGOOD GTLREF[3] 1%
GTLREF[2] G1 H_DPRSTP# 12 120mA / 20mil
TPC28t T79 1 H_VID5 H4 E26 r0402
H_VID4 VID[5] GTLREF[1] GTL_REF0 +1.8VS_VCCA
1
G4 VID[4] GTLREF[0] AD26 CPU_VCCA123
H_VID3 G3 <500 mil (55 Ohm)
VID[3]
2
Dothan FSB533 H_VID2 F3 T/B trace 5.5 , Space 25
VID[2]
1
H_VID1 F2 r0402 R464 C461
Min Typ Max VID[1]
H_VID0 E2 VID[0] TEST1 C5 TEST1 1 2 R39 1KOhm / 2KOhm 0.1UF
CPU_VCCA0
+1.8VS_PROC
VCCA 1.425V 1.5V 1.575V F23 TEST2 1 2 R97 1KOhm / 1% c0402
TEST2
1
1
1