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SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO'S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.




Table of Contents D




Sheet 1. COVER
HAINAN Sheet 2 - 7. DIAGRAM (Block/Power) & ANNOTATIONS
Sheet 8. CLOCK GENERATOR
Sheet 9 - 11. YONAH667 / MEROM CPU(TBD)
Sheet 12. THERMAL SENSOR / FAN CONTROL
Sheet 13 - 17. CALISTOGA-GMCH
Sheet18. DDR II SODIMM
CPU :Intel Yonah -2M Sheet19. DDR TERMINATION
Sheet20 - 23. ICH7-M
Chip Set :Intel Calistoga & ICH7-M Sheet24. FWH
Sheet25. LVDS CONNECTOR
Remarks : Mobility Platform Sheet26. VIDEO SWITCHING LOGIC C

Sheet 27. CRT CONNECTOR
Sheet 28. DVI TRANSMITTER
Sheet 29 - 30. R5C843 CARDBUS CONTROLLER
Sheet 31. EXPRESS & PCMCIA CONNECTOR
Model Name : HAINAN Sheet 32. MINI PCI EXPRESS & DMB & IR
Sheet 33 - 35. AUDIO
PBA Name : MAIN Sheet 36. HDD ODD CONNECTOR
Sheet 37. MICOM
PCB Code : BA41-00574A Sheet 38. SUPER I/O & FAN CONTROLLER
Sheet 39 - 40. LAN CONTROLLER
Dev. Step : PR Sheet 41. RJ45, RJ11, LED LOGIC
Sheet 42. SUB BOARD CONNECTOR
Revision : 1.0 Sheet 43. CHARGER
Sheet 44. P3.3V_LAN & P5V_AUX B

T.R. Date : 2005.11.28 Sheet 45. P1.5V & VCCP
Sheet 46. DDR2 POWER
Sheet 47. CPU VRM (SEMTECH)
Sheet 48. MICOM RESET & SWITCHED POWER
Sheet 49. DISCHARGING LOGIC
DRAW CHECK APPROVAL Sheet 50. DOCKING CONNECTOR
Sheet 51. EXT GFx CONNECTOR
Sheet 52 - 55. SUB BOARD
KI IM SS BAIK KK BIN

A


SAMSUNG
Owner : SEC Mobile R & D Signature : X ELECTRONICS




4 3 2 1
4 3 2 1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO'S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.




D SCHEMATIC ANNOTATIONS AND BOARD INFORMATION D



PCI Devices Crystal / Oscillator
Devices IDSEL# REQ/GNT# Interrupts TYPE FREQUENCY DEVICE USAGE
Cardbus AD25 0 E,F,G Crystal 32.768KHz ICH7-M Real Time Clock
LAN AD21 1 G Crystal 10MHz MICOM HD64F2169/2160
Crystal 14.318MHz CLOCK-Generator CK-410M
USB AD29(internal) - USB2.0 #0 : A Crystal 24.576MHz Cardbus Controller 1394
USB2.0 #1 : D Crystal 25MHz LAN Intel LAN
USB2.0 #2 : C
Hub to PCI AD30(internal) - -
LPC bridge/IDE/AC97/SMBUS AD31(internal) - B
Internal MAC AD24(internal) - E
AC Link - - B


CPU Core Voltage Table IMVP-6
Voltage Rails
VDC Primary DC system power supply (7 to 21V) Active/Deeper Sleep
VCC_CORE Core voltage for DOTHAN (1.308~1.068V) Active Mode Deeper Sleep/Extended Deeper Sleep
C Dual Mode Region Dual Mode Region C
VTT DOTHAN/ALVISO Processor System Bus(PSB) Termination (1.05V)
MCH-M Core Voltage
VID(6:0) Voltage VID(6:0) Voltage VID(6:0) Voltage
P0.9V 0.9V switched power rail (off in S3-S5)
P1.2V 1.2V switched power rail (off in S3-S5) 0 0 0 0 0 0 0 1.5000 V 0 1 0 1 0 0 0 1.0000 V 1 0 1 0 0 0 1 0.4875 V
P1.5V 1.5V switched power rail (off in S3-S5) 0 0 0 0 0 0 1 1.4875 V 0 1 0 1 0 0 1 0.9875 V 1 0 1 0 0 1 0 0.4750 V
P1.5V_AUX 1.5V power rail (off in S4-S5) 0 0 0 0 0 1 0 1.4750 V 0 1 0 1 0 1 0 0.9750 V 1 0 1 0 0 1 1 0.4625 V
P1.8V 1.8V switched power rail (off in S3-S5) 0 0 0 0 0 1 1 1.4625 V 0 1 0 1 0 1 1 0.9625 V 1 0 1 0 1 0 0 0.4500 V
P1.8V_AUX 1.8V power rail(off in S4-S5) 0 0 0 0 1 0 0 1.4500 V 0 1 0 1 1 0 0 0.9500 V 1 0 1 0 1 0 1 0.4375 V
P2.5V 2.5V switched power rail (off in S3-S5) 0 0 0 0 1 0 1 1.4375 V 0 1 0 1 1 0 1 0.9375 V 1 0 1 0 1 1 0 0.4250 V
0 0 0 0 1 1 0 1.4250 V 0 1 0 1 1 1 0 0.9250 V 1 0 1 0 1 1 1 0.4125 V
MICOM_P3V 3.3V always on power rail for MICOM 0 0 0 0 1 1 1 1.4125 V 0 1 0 1 1 1 1 0.9125 V 1 0 1 1 0 0 0 0.4000 V
P3.3V 3.3V switched power rail (off in S3-S5) 0 0 0 1 0 0 0 1.4000 V 0 1 1 0 0 0 0 0.9000 V 1 0 1 1 0 0 1 0.3875 V
P3.3V_AUX 3.3V power rail (off in S4-S5) 0 0 0 1 0 0 1 1.3875 V 0 1 1 0 0 0 1 0.8875 V 1 0 1 1 0 1 0 0.3750 V
P3.3V_DTV 3.3V power rail (off in S4-S5) 0 0 0 1 0 1 0 1.3750 V 0 1 1 0 0 1 0 0.8750 V 1 0 1 1 0 1 1 0.3625 V
0 0 0 1 0 1 1 1.3625 V 0 1 1 0 0 1 1 0.8625 V 1 0 1 1 1 0 0 0.3500 V
P5V 5.0V switched power rail (off in S3-S5) 0 0 0 1 1 0 0 1.3500 V 0 1 1 0 1 0 0 0.8500 V 1 0 1 1 1 0 1 0.3375 V
P5V_AUX 5.0V power rail (off in S4-S5) 0 0 0 1 1 0 1 1.3375 V 0 1 1 0 1 0 1 0.8375 V 1 0 1 1 1 1 0 0.3250 V
0 0 0 1 1 1 0 1.3250 V 0 1 1 0 1 1 0 0.8250 V 1 0 1 1 1 1 1 0.3125 V
0 0 0 1 1 1 1 1.3125 V 0 1 1 0 1 1 1 0.8125 V 1 1 0 0 0 0 0 0.3000 V
P3.3V_ALWS 3.3V power rail (Always On)
0 0 1 0 0 0 0 1.3000 V 0 1 1 1 0 0 0 0.8000 V 1 1 0 0 0 0 1 0.2875 V
P2.5V_ALWS 2.5V power rail (Always On)
0 0 1 0 0 0 1 1.2875 V 0 1 1 1 0 0 1 0.7875 V 1 1 0 0 0 1 0 0.2750 V
P1.2V_ALWS 1.2V power rail (Always On) 0 0 1 0 0 1 0 1.2750 V 0 1 1 1 0 1 0 0.7750 V 1 1 0 0 0 1 1 0.2625 V
0 0 1 0 0 1 1 1.2625 V 0 1 1 1 0 1 1 0.7625 V 1 1 0 0 1 0 0 0.2500 V
2 0 0 1 0 1 0 0 1.2500 V 0 1 1 1 1 0 0 0.7500 V 1 1 0 0 1 0 1 0.2375 V
0 0 1 0 1 0 1 1.2375 V 0 1 1 1 1 0 1 0.7375 V 1 1 0 0 1 1 0 0.2250 V
I C / SMB Address 0
0
0 1
1
0 1 1 0 1.2250 V 0
0
1 1
1
1 1 1 0 0.7250 V 1
1
1 0
0
0 1 1 1 0.2125 V
0 0 1 1 1 1.2125 V 1 1 1 1 1 0.7125 V 1 1 0 0 0
1 0.2000 V
Devices Address Hex Bus
B 0 0 1 1 0 0 0 1.2000 V 1 0 0 0 0 0 0 0.7000 V 1 1 0 1 0 0 1 0.1875 V B
0 0 1 1 0 0 1 1.1875 V 1 0 0 0 0 0 1 0.6875 V 1 1 0 1 0 1 0 0.1750 V
ICH7 Master - SMBUS Master 0 0 1 1 0 1 0 1.1750 V 1 0 0 0 0 1 0 0.6750 V 1 1 0 1 0 1 1 0.1625 V
EMC6N300(CPU Thermal Sensor) 1001 110X 9Ch Thermal Sensor 0 0 1 1 0 1 1 1.1625 V 1 0 0 0 0 1 1 0.6625 V 1 1 0 1 1 0 0 0.1500 V
SODIMM0 1010 0000 A0h - 0 0 1 1 1 0 0 1.1500 V 1 0 0 0 1 0 0 0.6500 V 1 1 0 1 1 0 1 0.1375 V
SODIMM1 1010 001X A4h - 0 0 1 1 1 0 1 1.1375 V 1 0 0 0 1 0 1 0.6375 V 1 1 0 1 1 1 0 0.1250 V
CK-408 (Clock Generator) 1101 001x D2h Clock, Unused Clock Output Disable 0 0 1 1 1 1 0 1.1250 V 1 0 0 0 1 1 0 0.6250 V 1 1 0 1 1 1 1 0.1125 V
0 0 1 1 1 1 1 1.1125 V 1 0 0 0 1 1 1 0.6125 V 1 1 1 0 0 0 0 0.1000 V
0 1 0 0 0 0 0 1.1000 V 1 0 0 1 0 0 0 0.6000 V 1 1 1 0 0 0 1 0.0875 V
0 1 0 0 0 0 1 1.0875 V 1 0 0 1 0 0 1 0.5875 V 1 1 1 0 0 1 0 0.0750 V
0 1 0 0 0 1 0 1.0750 V 1 0 0 1 0 1 0 0.5750 V 1 1 1 0 0 1 1 0.0625 V
0 1 0 0 0 1 1 1.0625 V 1 0 0 1 0 1 1 0.5625 V 1 1 1 0 1 0 0 0.0500 V
USB PORT Assign 0
0
1
1
0
0
0
0
1
1
0
0
0
1
1.0500 V
1.0375 V
1
1
0
0
0
0
1
1
1
1
0
0
0
1
0.5500 V
0.5375 V
1
1
1
1
1
1
0
0
1
1
0
1
1
0
0.0375 V
0.0250 V
0 1 0 0 1 1 0 1.0250 V 1 0 0 1 1 1 0 0.5250 V 1 1 1 0 1 1 1 0.0125 V
PORT NUMBER ASSIGNED TO 0 1 0 0 1 1 1 1.0125 V 1 0 0 1 1 1 1 0.5125 V 1 1 1 1 0 0
1 0 0.0000 V
1 0
1 1 0 0 0 0 0.5000 V 1 1 1 1 0 0 1 0.0000 V
0,1 SYSTEM PORT A, B 1 1 1 1 0 1 0 0.0000 V
2 SYSTEM PORT C Deeper Slp 1 1 1 1 0 1 1 0.0000 V
3 DMB Active 1 1 1 1 1 0 0 0.0000 V
4 BLUETOOTH DPRSLPVR 0 DPRSLPVR 1 1 1 1 1 1 0 1 0.0000 V
5 DOCKING STATION DPRSTP* 0 1 1 1 1 1 1 0 0.0000 V
6 MINI PCIE EXPRESS CARD DPRSTP* 1 1 1 1 1 1 1 1 0.0000 V
7 EXPRESS CARD PSI2* 0 or 1 PSI2* 0 or 1
*"1111111" : 0V power good asserted.

System Power States
A CHP3_SLPS1* S1, Powered-On-Suspend(POS) : In this state, all clocks(except the 32.768KHz clock) are stopped. *Yonah Processor (2.33 GHz / 800 MHz : TBD)
A
The system context is maintained in system DRAM. Power is maintained to PCI, the CPU, memory controller, memory, and all other criticial subsystems.
Note that this state does not preclude power being removed from non-essential devices, such as disk drives. During this state, CPU can be selected
for either Deep Sleep or Deeper Sleep.
In Deeper Sleep, CPU voltage reduced in this state to reduce the leakage power. SAMSUNG
CHP3_SLPS3* S3, Suspend-To-RAM(STR) : The system context is maintained in system DRAM, but power is shut off to non-critical circuits. ELECTRONICS
Memory is retained, and refreshes continue. All clocks stop except RTC clock.
CHP3_SLP4S* S4, Suspend-To-Disk(STD) : The Context of the system is maintained on the disk. All power is then shut off to the system except for the logic required to resume.
Externally appears same as S5, but may have different wake events.
CHP3_SLPS5* S5, Soft Off(SOFF) : System context is not maintained. All power is shut off except for the logic required to restart. A full boot is required when waking.


4 3 2 1
4 3 2 1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO'S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS PCI4_FCTSEL1(PIN34) PIN 43, 44 PIN 47, 48
EXCEPT AS AUTHORIZED BY SAMSUNG.
0 DOT96 LCD96/100

1 27MHZ SRC0
FSA FSB FSC
D HOST CLK D
CPU BSEL0 BSEL1 BSEL2
B31 P3.3V
0 0 0 266 MHz MMZ1608S121AT
0 0 1 333 MHz




10000nF
0 1 0 200 MHz




6.3V
100nF

100nF

100nF

100nF
R236 2.2




10nF

10nF
MMZ1608S121AT B30




100nF
0 1 1 400 MHz MMZ1608S121AT
R237 2.2 B23
1 0 0 133 MHz R217 2.2 TP130




C765

C862




C290

C291

C287
C292
C260




100nF
1 0 1 100 MHz SILEGO : SLG84452
TP121




C261
1 1 0 166 MHz R282 2.2




1%

1%
C252 FOR EMI
1 1 1 RSVD U19 10000nF C289 C288
6.3V 100nF 10000nF PLACE THESE BEAD AS CLOSE AS POSSIBLE TO PIN




C262
ICS954305D 6.3V




10K

10K
12 18 TP119
30 VDDCPU VDDREF 40 TP120
VDDPCI_1 VDD48
36 7 TP129
R769 2K 1% 49 VDDPCI_2 VDDA
CPU1_BSEL0 VDDSRC_1 TP122




R264
54 14 R239 33 5%




R216
10-C3
VDDSRC_2 CPU0 TP123 CLK0_HCLK0
65
VDDSRC_3 CPU0*
13 R240 33 5% 10-C3
CLK0_HCLK0*
30-B? R261 33 5% TP42 1
CLK3_FM48 VDDSRC_4 TP124
CPU1
11 R238 33 5% 13-B2
CLK0_HCLK1
21-B? R262 33 5% TP106 41 10 R241 33 5% TP131 13-C2
CLK3_USB48 45
48M_FSA CPU1* CLK0_HCLK1*
CPU1_BSEL1 TP107 FSB_TEST_MODE
CPU1_BSEL2
10-B3 10-D4 14-A3 R212 10K 1% 23
REF0_FSC_TEST_SEL CPU2_ITP_SRC_10
6
C 10-C3 10-D4 14-A3
CPU2*_ITP_SRC_10* 5 C
24
CHP3_CPUSTP* CPU_STP* TP125
CHP3_PCISTP*
21-C? 25
PCI_STP* CLKREQ1*
46 R218 10K 1%
21-C? TP126
26 R767 10K 1%
TP108 CLKREQ2*
R252 100