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8 7 6 5 4 3 2 1
CK ENG
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD APPD
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. REV ZONE ECN DESCRIPTION OF CHANGE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ. DATE DATE
C 399027 PRODUCTION RELEASED 09/09/05 ?
D D
PDF
TABLE_TABLEOFCONTENTS_HEAD
CSA CONTENTS SYNC MASTER DATE PDF
TABLE_TABLEOFCONTENTS_HEAD
CSA CONTENTS SYNC MASTER DATE
1 1 Table Of Contents N/A N/A 41 52 DDR2 SO-DIMM Slot B N/A N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
2 2 Board Information N/A N/A 42 55 M11 Frame Buffer Constraints N/A N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
3 3 System Block Diagram N/A N/A 43 56 I2 AGP Interface N/A N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
4 4 Power Block Diagram N/A N/A 44 57 GPU (M11) AGP Interface N/A N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
5 5 Revision History N/A N/A 45 58 GPU VCore Supply N/A N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
6 6 Q16C Pin Swaps N/A N/A 46 59 GPU (M11) Core Power N/A N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
7 7 Functional Test Points N/A N/A 47 60 GPU (M11) I/O Power N/A N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
8 8 I2C Connections N/A N/A 48 61 GPU (M11) Frame Buffer I/F N/A N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
9 9 JTAG Connections N/A N/A 49 62 GPU Frame Buffer A N/A N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
10 10 Power Synonyms N/A N/A 50 63 GPU Frame Buffer B N/A N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
11 11 Signal Synonyms N/A N/A 51 64 GPU (M11) GPIOs/Straps N/A N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
12 12 Power Inputs N/A N/A 52 65 GPU (M11) Clocks/Misc N/A N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
13 13 Battery Charger N/A N/A 53 66 GPU (M11) DVI/DAC Outputs N/A N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
14 14 12.8V PBUS/PMU Supplies N/A N/A 54 67 Lower TMDS Transmitter N/A N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
15 15 5V/3.3V Supplies N/A N/A 55 68 Upper TMDS Transmitter N/A N/A
C
C TABLE_TABLEOFCONTENTS_ITEM
16 16 1.8V/1.5V Supplies N/A N/A
TABLE_TABLEOFCONTENTS_ITEM
56 69 Internal Display Conns N/A N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
17 17 2.5V Supply N/A N/A 57 70 External Display Conns N/A N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
18 19 Vesta Power & Misc N/A N/A 58 71 BootROM N/A N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
19 21 I2 Power N/A N/A 59 72 I2 PCI Interface N/A N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
20 22 I2 Power Supplies N/A N/A 60 73 Q85 Airport/BT Connector N/A N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
21 23 I2 Supplemental N/A N/A 61 74 Cardbus N/A N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
22 24 I2 Miscellaneous N/A N/A 62 75 NEC USB2 N/A N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
23 25 PCI Clock Buffer N/A N/A 63 81 I2 UATA Interface N/A N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
24 26 LEDs/Reset/Debug N/A N/A 64 82 HDD/ODD Connectors N/A N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
25 27 Power Management Unit (PMU05) N/A N/A 65 84 I2 Ethernet Interface N/A N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
26 29 Power Sequencing N/A N/A 66 85 Vesta Ethernet PHY N/A N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
27 30 Fan Controller N/A N/A 67 86 Ethernet Connector N/A N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
28 31 ALS Support N/A N/A 68 88 I2 FireWire Interface N/A N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
29 32 Sudden Motion Sensor N/A N/A 69 89 Vesta FireWire PHY N/A N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
30 33 Q16C Internal I/O I N/A N/A 70 90 FireWire Ports N/A N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
31 34 Q16C Internal I/O II N/A N/A 71 91 FireWire Series Term N/A N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
32 35 I2 Processor Interface N/A N/A 72 92 I2 USB Interface N/A N/A
B TABLE_TABLEOFCONTENTS_ITEM
33
TABLE_TABLEOFCONTENTS_ITEM
36 A8 MaxBus (CPU0) MULLET 08/02/2005
TABLE_TABLEOFCONTENTS_ITEM
73
TABLE_TABLEOFCONTENTS_ITEM
93 NEC USB2 Interface N/A N/A B
34 37 A8 Configuration Straps MULLET 08/02/2005 74 100 Audio Board Connector N/A N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
35 38 A8 Power (CPU0) MULLET 08/02/2005 75 110 Spacing & Physical Constraints N/A N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
36 39 CPU VCore Supply N/A N/A 76 111 Spacing & Physical Constraints 2 N/A N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
37 46 CPU AVDD Supply N/A N/A 77 112 Cross Reference Page
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
38 47 I2 Memory Interface N/A N/A 78 113 Cross Reference Page
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
39 48 Memory Series Termination N/A N/A 79 114 Cross Reference Page
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
40 50 DDR2 SO-DIMM Slot A N/A N/A 80 115 Cross Reference Page
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
DIMENSIONS ARE IN MILLIMETERS
METRIC Apple Computer Inc.
XX
A X.XX
DRAFTER DESIGN CK NOTICE OF PROPRIETARY PROPERTY A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
X.XXX PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
ENG APPD MFG APPD
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
ANGLES II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
TABLE_5_HEAD
QA APPD DESIGNER TITLE
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
TABLE_5_ITEM
DO NOT SCALE DRAWING
051-6929 1 SCHEM,MARIAS-STD,Q16C SCH1
TABLE_5_ITEM
RELEASE SCALE SCHEM,MARIAS-STD,Q16C
820-1875 1 PCBF,MLB,Q16C PCB1 CRITICAL NONE
TABLE_5_ITEM
826-4393 1 LBL,P/N LABEL,PCB,28MM X 6MM [EEE:SYU] Q16C_BST_VRAM_S SIZE DRAWING NUMBER REV.
826-4393 1 LBL,P/N LABEL,PCB,28MM X 6MM [EEE:TMK] Q16C_BST_VRAM_H
TABLE_5_ITEM
MATERIAL/FINISH
NOTED AS D 051-6929 C
THIRD ANGLE PROJECTION APPLICABLE SHT 1 OF 115
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Design-Specific Rules
TABLE_SPACING_RULE
TABLE_SPACING_RULE
STANDARD
TABLE_SPACING_RULE
BGA_P1MM
=DEFAULT
10
*
*
=DEFAULT
0.10 MM
=DEFAULT
1.25 MM
=DEFAULT
0.1 MM
=DEFAULT
12.5 MM
=DEFAULT
15.0 MM
GND_CHASSIS_UPPER_DVI
CHASSIS GND CONNECTIONS
MAKE_BASE=TRUE
VOLTAGE=0V
=GND_CHASSIS_DVI_HOLE
=GND_CHASSIS_DVI2
2
57
BOARD HOLES
TABLE_SPACING_RULE MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm =GND_CHASSIS_DVI4 57 HEATSINK MOUNTS
BGA_P2MM
TABLE_SPACING_RULE
DEFAULT
20 *
*
0.20 MM
0.1 MM
1.25 MM
2.5 MM
0.1 MM
0.15 MM
12.5 MM
10.0 MM
15.0 MM
15.0 MM
GND_CHASSIS_FW_LOWER_DVI
MAKE_BASE=TRUE
=GND_CHASSIS_FW_HOLE
=GND_CHASSIS_DVI1
2 CHASSIS MOUNTS
TABLE_SPACING_ASSIGNMENT
VOLTAGE=0V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm =GND_CHASSIS_DVI3
57
57
ZT0200
HOLE-VIA-P5RP25
D TABLE_SPACING_ASSIGNMENT "1MM" area defined around BGAs to =GND_CHASSIS_TV 57 1 LEFT CPU ZT0210
HOLE-VIA-P5RP25 D
* * 1MM BGA_P1MM reduce DRCs caused by fan-out. =GND_CHASSIS_ENET
TABLE_SPACING_ASSIGNMENT
=GND_CHASSIS_FW_PORT1
67
2 =GND_CHASSIS_DVI_HOLE 1 DVI
AGP_STB
TABLE_SPACING_ASSIGNMENT
* 1MM BGA_P2MM
"BGA_P2MM" rule ensures these critical =GND_CHASSIS_FW_PORT2
70
70
ZT0201
HOLE-VIA-P5RP25
CLOCK * 1MM BGA_P2MM signals do not fan-out routed next =GND_CHASSIS_FW_EMI 70 1
UPPER RT GPU
TABLE_SPACING_ASSIGNMENT
to any other signals.
RAM_DIFF * 1MM BGA_P2MM
GND_CHASSIS_LCD
MAKE_BASE=TRUE
=GND_CHASSIS_LCD1 56
ZT0202 ZT0211
HOLE-VIA-P5RP25 1394
VOLTAGE=0V =GND_CHASSIS_LCD2
TABLE_PHYSICAL_RULE MIN_LINE_WIDTH=0.5 mm
56
HOLE-VIA-P5RP25 LWR CPU 2 =GND_CHASSIS_FW_HOLE 1
MIN_NECK_WIDTH=0.25 mm =GND_CHASSIS_LCD3 56 1
TABLE_PHYSICAL_RULE =GND_CHASSIS_LCD4 56
STANDARD * =DEFAULT =DEFAULT =DEFAULT =DEFAULT
TABLE_PHYSICAL_RULE
GND_CHASSIS_INVERTER
MAKE_BASE=TRUE
=GND_CHASSIS_INV_GND_CLIP 2 ZT0203
HOLE-VIA-P5RP25
BATT. CHGR
DEFAULT * Y 0.100 MM 0.100 mm 1.25 MM VOLTAGE=0V
MIN_LINE_WIDTH=0.5 mm
=GND_CHASSIS_INVERTER1 56
1 LWR RT GPU ZT0212
MIN_NECK_WIDTH=0.25 mm =GND_CHASSIS_INVERTER2 56
HOLE-VIA-P5RP25
Layer-specific rules for 90-ohm differential impedance GND_CHASSIS_BATT_CHGR 2 =GND_CHASSIS_BATTCHGR_HOLE 1
TABLE_SPACING_RULE =GND_CHASSIS_BATTCHGR_HOLE 2
MAKE_BASE=TRUE
VOLTAGE=0V =GND_CHASSIS_SLEEP_LED 30
TABLE_SPACING_RULE MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
90_OHM_DIFF
TABLE_SPACING_RULE
TOP,BOTTOM 2.5 MM 0.200 MM 2.5 MM 1.0 MM MECH. HOLES INVERTER
90_OHM_DIFF * 2.5 MM 0.200 MM 2.5 MM 1.0 MM
ZT0221
HOLE-VIA-P5RP25 2 =GND_CHASSIS_INV_GND_CLIP 1
TABLE_PHYSICAL_RULE
TP_LEFT_KYBRD_SCREW 1
2
SH0200
OG-503040
TABLE_PHYSICAL_RULE SHLD-SM-LF
90_OHM_DIFF
TABLE_PHYSICAL_RULE
TOP,BOTTOM Y 0.118 MM 0.1 MM 5 MM ZT0222
HOLE-VIA-P5RP25
3
90_OHM_DIFF * Y 0.125 MM 0.1 MM 5 MM TP_RT_KYBRD_SCREW 1
Layer-specific rules for 100-ohm differential impedance
TABLE_SPACING_RULE
Layer-specific rules for 60-ohm single-ended impedance
TABLE_PHYSICAL_RULE
ZT0223
HOLE-VIA-P5RP25
1
C TABLE_SPACING_RULE
100_OHM_DIFF TOP,BOTTOM 2.5 MM 0.200 MM 2.5 MM 1.0 MM
TABLE_PHYSICAL_RULE
60_OHM_SE * Y 0.076 MM =50_OHM_SE =50_OHM_SE
TP_OPTICAL_DRIVE_SCREW
C
TABLE_SPACING_RULE
100_OHM_DIFF * 2.5 MM 0.200 MM 2.5 MM 1.0 MM
Layer-specific rules for 50-ohm single-ended impedance
TABLE_SPACING_RULE
TABLE_PHYSICAL_RULE
TABLE_PHYSICAL_RULE
TABLE_SPACING_RULE
BOARD STACK-UP AND CONSTRUCTION
50_OHM_SE * 2.5 MM 0.125 MM 2.5 MM 1.0 MM
100_OHM_DIFF TOP,BOTTOM Y 0.092 MM 0.1 MM 5 MM SEE BOARD FILE FOR DETAILED INFORMATION
TABLE_PHYSICAL_RULE TABLE_PHYSICAL_RULE
CONVENTIONAL CONSTRUCTION WITH Pxx TH VIA
100_OHM_DIFF * Y 0.100 MM 0.1 MM 5 MM
TABLE_PHYSICAL_RULE
50_OHM_SE * Y 0.100 MM 0.100 MM 1.25 MM SIGNAL (1/2 OZ + COPPER PLATING)
Layer-specific rules for 110-ohm differential impedance
TABLE_SPACING_RULE 1
PREPREG GROUND (1/2 OZ)
TABLE_SPACING_RULE
110_OHM_DIFF
TABLE_SPACING_RULE
TOP,BOTTOM 2.5 MM 0.330 MM 2.5 MM 1.0 MM
2 CORE SIGNAL (1/2 OZ)
110_OHM_DIFF * 2.5 MM 0.300 MM 2.5 MM 1.0 MM
3
TABLE_PHYSICAL_RULE PREPREG SIGNAL (1/2 OZ)
TABLE_PHYSICAL_RULE NO_TEST Properties