Text preview for : Acer_Ferrari_1200.zip part of acer Acer Ferrari 1200 acer Acer_Ferrari_1200.zip
Back to : Acer_Ferrari_1200.zip | Home
5 4 3 2 1
PCB Layer Stackup
Ferrari 7 GT Block Diagram
L1: Component
2008/09/01 L2: GND
L3: Signal
Project code:91.4BA01.001 L4: VCC
DDR2 SODIMM PCB P/N :08225
D DIMM1
DDR II 667/800
AMD L5: GND
L6: Signal D
DDR2 SODIMM Giffin Port Replicator L7: GND
L8: Component
DDR II 667/800
DIMM2 S1g2 Socket
CPU V_CORE
Power Switch USB
OUT
16x16 HyperTransport ISL6265HR 37
IN
G577BR91U
RJ45/CRT//DVI-D/SPDIF/MIC INPUT OUTPUT
New card PCI-E x 1 in/Line in/Line out/AC Jack DCBATOUT VCC_CORE_S0
www.kythuatvitinh.com
Mini Card PCI-E x 1 SYSTEM DC/DC
802.11a/b/g/n
AMD INPUT
TPS51124
OUTPUT
1D2V_S0
38
DCBATOUT 1D1V_S0
C C
RJ45 XFORM LAN CLK GEN. TPS51120 40
Broadcom
5764M
PCI-E x 1
RS780M CRT
ICS 9LPRS480BKLTF
14.318MHz
INPUT
DCBATOUT
OUTPUT
5V_S5
3D3V_S5
LVDS TPS51117 39
25MHz
INPUT OUTPUT
12.1" LCD
INT. MIC Array
G792 A-Link PCI-E x 4
DCBATOUT 1D8V_S3
SYSTEM LDO
Line In G2997 41
MS/MS Pro/xD/ INPUT OUTPUT
USB RTL5158
Codec AZALIA MMC/SD 5 in 1 1D8V_S3 0D9V_S3
ALC268 G9161
B
MIC In AMD PCI BUS
JMicron 1394
INPUT
3D3V_S5
OUTPUT
1D2V_S5
B
G9166
JMB380 CONN
AMP
G1431 SB700 24.576MHz
25MHz
32.768KHz
INPUT
3D3V_S0
G957
OUTPUT
2D5V_S0
32.768KHz INPUT OUTPUT
INT.SPKR
AZALIA
3D3V_S0 1D5V_S0
AMP LPC BUS
KBC
Winbond SPI
G1412 WPC775F
Line Out
USB Battery Charger
(No-SPDIF)
MODEM USB MAX8371 43
16/17/18/19/20 Touch INT. BIOS FIR INPUTS OUTPUTS
RJ11 MDC Card Pad KB MX25L1605DM2I
AD+ DCBATOUT
USB x 3
BAT+
SATA CCD
USB
A A
SB
USB
HDD Digitally signed by dd Incorporated
Wistron
DN: cn=dd, o=dd,21F, 88, TaipeiTai Wu Rd
ou=dd,
Hsichih,
Hsin
USB MINI USB Title [email protected], c=US
CDROM SATA Finger print Interactive Circuit Map
3 Port BlueTooth Size Document Number 2009.12.04 19:26:53
Date: Rev
A3
Date:
+07'00' 2008
F7-GT
Monday, September 01, Sheet 1 of 47
SB
5 4 3 2 1
5 4 3 2 1
3D3V_S0 3D3V_CLK_VDD
Do Not Stuff 3D3V_S0
1 2 R349
R180 1 2 3D3V_48MPWR_S0
1
1
1
1
1
1
1
1
C276 C275 C559 C557 C283 C535 C536 C554 Due to PLL issue on current clock chip, the SBlink clock
Do Not Stuff
1
1
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
2R3J-GP C267 C539
SC1U10V2KX-1GP need to come from SRC clocks for RS740 and RS780.
DY
2
2
2
2
2
2
2
2
Future clock chip revision will fix this.
2
2
3000mA.80ohm
D D
Clock chip has internal serial terminations
3D3V_S0 for differencial pairs, external resistors are
R179 reserved for debug purpose.
1 2 GEN_XTAL_IN
1D2V_S0 0R3-0-U-GP 1D1V_CLK_VDDIO
R367
1 2 C272
2 1
1
1
1
1
1
1
1
2
Do Not Stuff C274 C280 C537 C551 C540 C560 C558 3D3V_CLK_VDD X2 SC33P50V2JN-3GP
1
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
DY R176 X-14D31818M-35GP
U29 82.30005.891
Do Not Stuff
2
2
2
2
2
2
2
1D1V_CLK_VDDIO 2ND = 82.30005.951
26 61
DY C271 SC33P50V2JN-3GP
20080724
1
2
VDDATIG X1 GEN_XTAL_OUT
25 VDDATIG_IO X2 62 2 1
CL=20pF