datasheets 74ls569 free download

File name 74ls569.pdf

SN54/74LS569A FOUR-BIT UP/DOWN COUNTER WITH THREE-STATE OUTPUTS The SN54 / 74LS569A is designed as programmable up/down BCD and Binary counters respectively. These devices have 3-state outputs for use in bus organized systems. With the exception of output enable (OE) and FOUR-BIT UP / DOWN COUNTER asynchronous clear (ACLR), all functions occur on the positive edge of the WITH THREE-STATE OUTPUTS clock pulse (CP). LOW POWER SCHOTTKY When the LOAD input is LOW, the outputs will be programmed by the parallel data inputs (A, B, C, D) on the next clock edge. Enabling of the counters occurs only when CEP and CET are LOW and LOAD is HIGH. Direction of the count is controlled by the up-down input (U/D), HIGH counts up and LOW counts down. High-speed counting and cascading is implement- ed by internal look-ahead carry logic and an active LOW ripple carry output J SUFFIX (RCO). On the LS569A, the RCO is LOW at binary 15 during up-count and CERAMIC during down-count it is also LOW at binary 0. During normal cascading CASE 732-03 operation RCO connected to the succeeding block at CET is the only 20 requisite. When counting and when RCO is LOW, the clocked carry output 1 (CCO) provides a HIGH-LOW-HIGH pulse for a duration equal to the LOW time of the clock pulse. Two active LOW reset lines are provided, a master N SUFFIX reset asynchronous clear (ACLR) and a synchronous clear (SCLR). When in PLASTIC a HIGH state, the output control (OE) input forces the counter output into a CASE 738-03 HIGH impedance state and when LOW, the counter outputs are enabled. 20