arete_arix CSS Bus Spec free download

File name CSS_Bus_Spec.pdf

-2- 1. CSS Bu, 1.1 CSS Bu, Overview The system bus is an N-port time-division multiplexed transmission switch. AIly of the N ports (backplane positions/slots) can send (receive) transmissions to (from) any of the N ports, including itself. Each transmission consists of a source port address, a destination port address, a transmission type and 8 bytes of "data n. The transmission type determines what the ndata" field contains. Error detection is provided for the source slot address, destination slot address and transmission type fields and optionally provided for the "data" field. The design value of N is 14 (ports); the design clock rate is 20 MHz. Modules installed in bus ports interact with each other by exchanging transmissions over the bus. There are two types of transmissions, COMMANDS and RESPONSES. A module on the bus begins an interaction with another module by sending a OOMMAND. The source of the OOMMAND is the MASTER for that interaction; the destination of the OOMMAND is the SLAVE. The SLAVE sends a RESPONSE back to the MASTER if required to complete the interaction. 1.2 CSS BU8 Operation The OSS bus arbiter controls access to the bus. To transmit on the bus, a module issues a request, a request modifier and a destination port address to the arbiter. If the request is to send a COMMAND, the arbiter checks that the destination port has a COMMAND input buffer available. A port with a COMMAND input buffer available is said to be READY. If the request is to send a RESPONSE, the destination port is required to have to have enough RESPONSE buffer space available for the size of the RESPONSE it requested. Ports wanting to send COMMANDS to destinations that are READY and ports wanting to send RESPONSES arbitrate for time slots on the bus. Arbitration occurs for each time slot. Arbitration priority is determined by the port number of requesting port. Port N has the highest priority, and port 0 the lowest. Computational modules as a group are assigned the lowest priorities. A bus bandwidth spreading scheme insures that all computational modules get about the same amount of access to the bus. A module on the bus is READY to receive a COMMAND when it has at least one COMMAND buffer free. Each module indicates to the arbiter how many OOMMAND buffers it has free. The arbiter maintains a count of free OOMMAND buffers for each module and decrements the count for the destination module as permission to send each COMMAND is GRANTED. Each module in turn signals the arbiter to increment its free huffer (READY) count whenever one of the module's COMMAND buffers becomes free. The bus arbiter also supports interlocked sequences of operations. These sequences are required to to support the TAS, OAS and CAS2 instructions of the Motorola 68020 and are a generalization of the READ/MODIFY/WRITE operation. Interlocked sequences are atomic to each other and are composed of any number of READ and WRITE commands. The signal LOOK is asserted by the arb