VIA Cyrix III free download

File name cyrix3db.pdf

Cyrix III Processor DataBook Socket 370 Compatible x86 CPU Featuring MMXTM and 3DNow!TM Technology ©2000 Copyright Via-Cyrix Corporation. All rights reserved. Printed in the United States of America Trademark Acknowledgments: Cyrix is a registered trademark of Via Cyrix Corporation. Cyrix III is a trademark of Via-Cyrix Corporation. MMX is a trademark of Intel Corporation. All other brand or product names are trademarks of their respective companies. Via-Cyrix Corporation 2703 North Central Expressway Richardson, Texas 75080-2010 United States of America Via-Cyrix Corporation (Cyrix) reserves the right to make changes in the devices or specifications described herein without notice. Before design-in or order placement, customers are advised to verify that the information is current on which orders or design activities are based. Via-Cyrix warrants its products to conform to current specifications in accordance with Via-Cyrix' standard warranty. Testing is performed to the extent necessary as determined by Via-Cyrix to support this warranty. Unless explicitly specified by customer order requirements, and agreed to in writing by Via-Cyrix, not all device characteristics are necessarily tested. Via-Cyrix assumes no liability, unless specifically agreed to in writing, for customers' product design or infringement of patents or copyrights of third parties arising from the use of Via-Cyrix devices. No license, either express or implied, to Cyrix patents, copyrights, or other intellectual property rights pertaining to any machine or combination of Via-Cyrix devices is hereby granted. Via-Cyrix products are not intended for use in any medical, life saving, or life sustaining system. Information in this document is subject to change without notice. ii Cyrix III REVISION HISTORY Date 1/25/00 3/22/99 3/17/99 Version 1.0 0.53 0.52 Revision Final Specs updated for production Changed name from MXs to Cyrix III processor. Pages 1-9, 1-10: Both L1 and L2 caches are unified. Page 1-11 Remove paragraph concerning Scratch Pad Cache Memory Page 2-36 and similar pages Replace "Don't care" with xxxxb. Page 2-56 Added Clock Ratio Table for BIOS Core/Bus Frequency Ratios Added CPUPRES# signal. Changed X32 pin to GND Changed Z32 pin to Vcc Changed name VDD-2.5 to VCC_2.5 Changed AD32 pin to Vcc Added IERR# signal Added BRO# Modified Figure 5.3 Voltage Connections Changed REF7 to VREF7 in pin diagrams. Corrected Pages 5-1 and 5-2 Pin Assignment Diagrams Corrected Pages 5-3 and 5-4 Pin Signal List Added power diagram Page 5-6 Figure 5-3. Page 2-33 Updated and completed CPU Configuration Register Table Page 2-43 Added question marks --Does CCR7 exist? Page 2-48 Updated RCRn bit 0 RCD/RCE Page 2-53 Added Clock Ratio Table for DIR3 TYPE Field Bullet Page:Added Programmable Clock/Bus Ratio, new ratio Page 3-1 Made several changes to Figure 3-1. Page 3-2 Removed subname explanation. Page 3-2 Redefined ADS#. Page 3-3 LOCK# is now I/O. Page 3-5 Many changes to Table 3-2, non