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Application Note 127 Cyrix III CPU MotherBoard Design Considerations Cyrix Processors REVISION HISTORY Date 5/20/99 4/5/99 Version 1.0 0.54 Revision Added Diagrams Page 5, Table 1, Pin AK30 Description. Changed description. Page 5, Table 1, Moved third column and changed heading. Other minor editing on pages 7, 8, 9,and 13 . Typo Page 5, AK30 pin BSEL1 changed to 1 = 133 MHz, 0 =100 MHz Changed MXs processor name to Cyrix III. Corrected typos. Added paragraphs to pages 4, 7, 8 and 9 Renamed document to include the word "Considerations" Renamed document to better reflect the content. Repaired Table 1-4. BSEL0 and BSEL1 columns were reversed. Changed BSEL66# to BSEL0, Changed BSEL133# to BSEL1. BSEL1 now requires pull-down 10K resistor instead of 200 ohm pull-up resistor. Pins now listed in Table 1-2. Bus speed signals redefined in Table 1-4. Initial Version C:\documentation\joshua\appnotes\cIII_board.fm 4/2/99 3/22/99 3/15/99 3/12/99 3/11/99 2/26/99 2/26/99 0.53 0.52 0.51 0.5 0.4 0.3 0.2 2/25/99 0.1 Application Note 127 Cyrix III Board Design Considerations and AC/DC Specifications 1. Introduction The Cyrix III is the next generation processor from Cyrix. This application note describes board design considerations unique to the Cyrix III processor. In this document, pin differences are described and design considerations are discussed. Also the AC/DC Specifications are presented to a aid in proper timing design. The Cyrix III CPU is designed to be compatible with the Intel Celeron CPU. It is a socket 370 compatible processor and thus is intended to work with the common Socket 370 motherboards. There are however some differences between the Cyrix III as the Intel Celeron that impact motherboard design. Cyrix III Board Design Considerations and AC/DC Specifications There are four major differences between the Cyrix III and Celeron CPUs that are important to motherboard designers: 1) Core voltages: the Cyrix III operates at 2.2 volts and the Celeron operates at 2.0 volts. It thus requires the VID4 pin to be tied to cpu and VR. 2) Bus speed: the Cyrix III can run with a bus at high as 133 MHz bus whereas the Celeron can run with a bus as high as 100 MHz. 3) Clock multiplier: the Cyrix III built in default clock multiplier can be changed (either by jumpers or by BIOS), whereas the Celeron has a inflexible built-in clock multiplier. 4) BIOS update: BIOS needs to be programmed to identify Cyrix III cpu and set up all cpu registers. Performance Rating must be added to CPU name. Operating the Cyrix III processor at 100 MHz and 133 MHz bus speeds requires careful board design. Signal timing analysis and signal integrity analysis must be done to ensure reliable operation. Factors such as clock skew, board and connector parasitics, and signal overshoot and ringback must be considered. Refer to 100MHz GTL+ Layout Guidelines (Intel document 243330-001) and Cyrix Application Notes 101 and 113 for implementation suggestions. 4 Application Note 127